Claims
- 1. A sense amplifier for reading the contents of a memory cell, the sense amplifier comprising:
a low impedance driver coupled to the memory cell and generating an output signal indicative of the contents of said memory cell; and a comparator coupled to the output of the low impedance driver and to at least one reference voltage signal to generate at least one comparison signal indicative of the relation between the output signal and the corresponding at least one reference voltage signal.
- 2. A sense amplifier for reading the contents of a memory cell, the sense amplifier comprising:
a wide output gain stage coupled to the memory cell and generating an output signal indicative of the contents of said memory cell; and a comparator coupled to the output of the wide output gain stage and to at least one reference voltage signal to generate at least one comparison signal indicative of the relation between the output signal and the corresponding at least one reference voltage signal.
- 3. A sense amplifier for reading the contents of a memory cell, the sense amplifier comprising:
a feedback cascode circuit coupled to the memory cell via a bitline and having an output generating an output signal indicative of the contents of said memory cell in response to a signal on the bitline; and a comparator coupled to the output of the feedback cascode circuit and to at least one voltage signal to generate at least one comparison signal indicative of the relation between the output signal and the corresponding at least one reference voltage signal.
- 4. A sense amplifier for reading the contents of the memory cell, the sense amplifier comprising:
a replica precharge stage coupled to the memory cell via a bit line to precharge the bitline at a level replicating a bias level applied to the bitline; and a comparator coupled of the replica precharge circuit and to at least one reference voltage signal to generate at least one comparison signal indicative of the relation between the output signal and the corresponding at least one reference voltage signal.
- 5. A sense amplifier for reading the contents of the memory cell, the sense amplifier comprising:
an input stage for loading of a bitline coupled to the memory cell and having an output for providing an output signal indicative of the contents of said memory cell; and a comparator coupled to the output of the input stage and to at least one reference voltage signal to generate at least one comparison signal indicative of the relation between the low impedance driver signal and the corresponding at least one voltage signal, the comparator providing an analog bootstrap between said at least one comparison signal and the output signal of the input stage.
- 6. A sense amplifier for reading the contents of a memory cell, the sense amplifier comprising:
an input stage for loading of a bit line coupled to the memory cell and having an output for providing a low impedance driver signal indicative of the contents of said memory cell; and a comparator coupled to the output of the input stage and to at least one reference voltage line to generate at least one comparison signal indicative of the relation between the low impedance driver signal and the corresponding at least one reference voltage.
- 7. The sense amplifier of claim 6 wherein the input stage comprises a load for loading of said bit line and an output stage having a low output impedance.
- 8. The sense amplifier of claim 7 wherein the load comprises a PMOS transistor including a first terminal coupled to the bit line, and including a gate and a second terminal, each coupled to a power supply terminal.
- 9. The sense amplifier of claim 7 wherein the load comprises an NMOS transistor including a first terminal coupled to the bit line, including a second terminal coupled to the power supply line and including a gate terminal coupled to the second terminal.
- 10. The sense amplifier of claim 7 wherein the load comprises an NMOS transistor including a first terminal coupled to the bit line, including a second terminal coupled to a power supply terminal, and including a gate coupled to a bias voltage source.
- 11. The sense amplifier of claim 7 wherein the load comprises a PMOS transistor including a first terminal coupled to the bit line, including a second terminal coupled to a power supply terminal, and including a gate, and further comprising a linear voltage source for biasing said gate.
- 12. The sense amplifier of claim 11 wherein the linear voltage source comprises a resistor divider circuit.
- 13. The sense amplifier of claim 7 wherein the load comprises a resistor coupled between a voltage source and the bit line.
- 14. The sense amplifier of claim 6 wherein the input stage includes wide output gain between the loading and the low impedance driver signal.
- 15. The sense amplifier of claim 6 wherein the input stage further comprises a wide output gain stage, the wide output gain stage comprising:
a first transistor of the first type including a first terminal coupled to a power terminal, including a second terminal spaced apart from said first terminal with a channel therebetween, and including a gate for controlling current in said channel and coupled to a bit line; a first transistor of a second type including a first terminal coupled to the second terminal of the first transistor of the first type, including a second terminal spaced apart from said first terminal with a channel therebetween, and including a gate for controlling current in said channel and coupled to said first terminal; a second transistor of the second type including a first terminal coupled to the first transistor of the second type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to a ground terminal, and including a gate for controlling current in said channel and coupled to the first terminal of the first transistor of the second type; a second transistor of the first type including a first terminal coupled to the power terminal, including a second terminal spaced apart from said first terminal with a channel therebetween and forming a data node, and including a gate for controlling current in said channel and coupled to said second terminal; a third transistor of the second type including a first terminal coupled to the second terminal of the second transistor of the second type, including a second terminal spaced apart from said first terminal with a channel therebetween, and including a gate for controlling current in said channel and coupled to the second terminal of the first transistor of the first type; and a fourth transistor of the second type including a first terminal coupled to the second terminal of the third transistor of the second type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to ground, and including a gate for controlling current in said channel and coupled to the gate of the third transistor of the second type.
- 16. The sense amplifier of claim 15 wherein the wide output gain stage further comprises a third transistor of the first type including a first terminal coupled to the power terminal, including a second terminal spaced apart from said first terminal of the channel therebetween and coupled to the second terminal of the second transistor of the first type, and including a gate for controlling current in said channel and coupled to the power terminal.
- 17. The sense amplifier of claim 6 wherein the input stage comprises a wide output gain stage including:
an operational amplifier having a first input coupled to the bit line, having a second input, and having an output coupled to an output node; a first resistor having a first terminal coupled to the output of the operational amplifier and a second terminal coupled to the second input of the operational amplifier; and a second resistor having a first terminal coupled to the second terminal of the first resistor and having a second terminal coupled to a ground terminal.
- 18. The sense amplifier of claim 6 wherein the input stage further comprises:
a wide output gain stage including a PMOS transistor including a first terminal coupled to a power terminal, including a second terminal spaced apart from said first terminal with a channel therebetween, and including a gate for controlling current in said channel and coupled to the bit line; and a resistor having a first terminal coupled to the second terminal of the PMOS transistor and having a second terminal coupled to a ground terminal.
- 19. The sense amplifier of claim 6 wherein the input stage includes a wide output gain stage comprising:
a PMOS transistor including a first terminal coupled to a power terminal, including a second terminal spaced apart from said first terminal with a channel therebetween and including a gate for controlling current in said channel and coupled to the bit line; and an NMOS transistor including a first terminal coupled to the second terminal of the PMOS transistor, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to a ground terminal, and including a gate for controlling current in said channel and coupled to said first terminal.
- 20. The sense amplifier of claim 19 further comprising:
a resistor having a first terminal coupled to the power terminal and having a second terminal, and a second NMOS transistor having a first terminal coupled to the second terminal of the resistor, including a second terminal spaced apart from said first terminal with a channel therebetween coupled to a ground terminal and including a gate for controlling current in said channel and coupled to the second terminal of the PMOS transistor.
- 21. The sense amplifier of claim 6 wherein the input stage has an output impedance that is independent of the current of the memory cell.
- 22. The sense amplifier of claim 6 wherein the input stage includes a low impedance output stage.
- 23. The sense amplifier of claim 22 wherein the low impedance output stage comprises a first transistor of a first type including a first terminal coupled to a power terminal, including a second terminal spaced apart from said first terminal with a channel therebetween and providing the low impedance driver signal and including a gate for controlling current in said channel coupled to receive a signal indicative of the contents of the memory cell;
a first transistor of a second type including a first terminal coupled to the second terminal of the first transistor of the first type, including a second terminal spaced apart from said first terminal with a channel therebetween and including a gate for controlling current in said channel in response to a bias voltage; and a second transistor of the second type including a first terminal coupled to the second terminal of the first transistor of the first type including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to a ground terminal, and including a gate for controlling current in said channel and coupled to the bias voltage.
- 24. The sense amplifier of claim 22 wherein the low impedance output stage comprises:
an operational amplifier having a first input coupled to receive a signal indicative of the contents of the memory cell, having a second input, and having an output for providing a low impedance driver signal; a first variable resistor having a first terminal coupled to the output of the operational amplifier and having a second terminal coupled to the second input of the operational amplifier; and a second variable resistor having a first terminal coupled to the second terminal of the first variable resistor and having a second terminal coupled to a ground terminal.
- 25. The sense amplifier of claim 22 wherein the low impedance output stage comprises:
a current source having a first terminal coupled to a power terminal, and having a second terminal providing the low impedance driver signal; and a PMOS transistor including a first terminal coupled to the second terminal of the current source, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to a ground terminal, and including a gate for controlling current in said channel and coupled to receive a signal indicative of the contents of the memory cell.
- 26. The sense amplifier of claim 6 further comprising a precharge circuit to precharge the bit line before receiving said contents of the memory cell.
- 27. The sense amplifier of claim 26 wherein the precharge circuit comprises:
a first transistor of a first type including a first terminal coupled to a power terminal, including a second terminal spaced apart from said first terminal with a channel therebetween, and including a gate for controlling current in said channel and coupled to an enable signal; and a first transistor of a second type including a first terminal coupled to the second terminal of the first transistor of the first type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the bit line, and including a gate for controlling current in said channel in response to a bias voltage.
- 28. The sense amplifier of claim 27 wherein the precharge circuit further comprises:
a current source; a second transistor of the second type including a first terminal coupled to the current source and the gate of the first transistor of the second type, including a second terminal spaced apart from said first terminal with a channel therebetween, including a gate for controlling current in said channel and coupled to said first terminal; and a third transistor of the second type including a first terminal coupled to the second terminal of the second transistor of the second type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to a ground terminal, and including a gate for controlling current in said channel and coupled to said first terminal.
- 29. The sense amplifier of claim 6 further comprising a precharge circuit to precharge the output of the input stage.
- 30. The sense amplifier of claim 29 wherein the precharge circuit comprising:
a first transistor of a first type including a first terminal coupled to a power terminal, including a second terminal spaced apart from said first terminal with a channel therebetween, and including a gate for controlling current in said channel and coupled to receive a precharge signal; and a first transistor of a second type including a first terminal coupled to the second terminal of the first transistor of the first type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the output of the input stage, and including a gate for controlling current in said channel and coupled to a bias signal.
- 31. The sense amplifier of claim 30 wherein the precharge signal is a pulse signal.
- 32. The sense amplifier of claim 30 wherein the bias signal is a reference voltage corresponding to a reference voltage of contents of the memory cell.
- 33. The sense amplifier of claim 6 further comprising a feedback cascode circuit coupled between the input stage and the bit line.
- 34. The sense amplifier of claim 6 further comprising a first transistor of a first type including a first terminal coupled to the bit line, including a second terminal coupled to the input stage and spaced apart from said first terminal with a channel therebetween, and including a gate for controlling current in said channel.
- 35. The sense amplifier of claim 6 wherein the first transistor of the first type is an NMOS enhancement transistor.
- 36. The sense amplifier of claim 6 wherein the first transistor of the first type is an NMOS native low voltage transistor.
- 37. The sense amplifier of claim 34 wherein said gate of the first transistor of the first type is coupled to a fixed bias voltage terminal.
- 38. The sense amplifier of claim 34 further comprising a common source amplifier including a current load coupled to the gate of the first transistor of the first type.
- 39. The sense amplifier of claim 34 further comprising a common source amplifier and a PMOS transistor operating in saturation and coupled to the gate of the first transistor of the first type.
- 40. The sense amplifier of claim 34 further comprising a common source amplifier and a PMOS transistor operating in a linear mode and coupled to the gate of the first transistor of the first type.
- 41. The sense amplifier of claim 34 further comprising a cascode circuit for biasing said gate of the first transistor of the first type in response to the voltage on the bit line.
- 42. The sense amplifier of claim 34 further comprising:
a second transistor of the first type including a first terminal coupled to a ground terminal, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the gate of the first transistor of the first type, and including a gate for controlling current in said channel and coupled to the first terminal of the first transistor of the first type; and a first transistor of a second type including a first terminal coupled to the second terminal of the second transistor of the first type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to a power terminal, and including a gate for controlling current in said channel and coupled to a bias voltage terminal.
- 43. The sense amplifier of claim 42 further comprising a diode circuit coupled between the second terminal of the first transistor of the second type and the ground terminal.
- 44. The sense amplifier of claim 6 further comprising:
a first transistor of the first type including a first terminal coupled to the bit line, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the input stage and including a gate for controlling current in said channel, a second transistor of the first type including a first terminal coupled to a ground terminal, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to the gate of the first transistor of the first type, and including a gate for controlling current in said channel and coupled to the first terminal of the first transistor of the first type, a first transistor of the second type including a first terminal coupled to the second terminal of the second transistor of the first type, including a second terminal spaced apart from said first terminal with a channel therebetween, and including a gate for controlling current in said channel and coupled to an enable signal terminal, and a second transistor of the second type including a first terminal coupled to the second terminal of the second transistor of the second type, including a second terminal spaced apart from said first terminal with a channel therebetween and coupled to a power terminal, and including a gate for controlling current in said channel and coupled to a bias voltage terminal.
- 45. The sense amplifier of claim 44 further comprising a diode circuit coupled between the second terminal of the first transistor of the second type and the ground terminal.
- 46. A sense amplifier for reading memory cells storing data have multilevel voltages, the sense amplifier comprising:
a high speed load stage coupled to the memory cells to sense the content of the memory cells; a wide output gain stage coupled to the high speed load stage to provide a first detected voltage signal in response to the sensed content; a low impedance output stage to provide a second detected voltage signal in response to the first detected voltage signal; a comparator stage for comparing the data to at least one reference voltage level and generating corresponding comparison signals for the at least one reference voltage levels; a latch for storing the comparison signals.
- 47. The sense amplifier of claim 46 wherein the high speed load stage comprises a load and a cascode circuit.
- 48. The sense amplifier of claim 46 wherein the comparator stage comprises a differential amplifier.
- 49. The sense amplifier of claim 48 wherein the comparator stage comprises a latch.
- 50. The sense amplifier of claim 48 wherein the comparator stage comprises a latch including an initial latching amplification circuit.
- 51. The sense amplifier of claim 50 wherein the initial latching amplification circuit includes an analog bootstrap circuit.
- 52. The sense amplifier of claim 50 wherein the comparator stage comprises a post latching amplification circuit.
- 53. The sense amplifier of claim 46 further comprising a precharge circuit to precharge a voltage on a bit line coupling the memory cell to the high speed load stage.
- 54. A sense amplifier comprising:
means for sensing at high speed content of a memory cell; means for driving a load independent of the sensed current of the memory cell; means for comparing the sensed content to at least one reference voltage.
- 55. A sense amplifier of claim 54 further comprising means for matching at least one compared data.
- 56. The sense amplifier of claim 55 further comprising means for decoding the latched content.
- 57. The sense amplifier of claim 54 further comprising means for precharging a line connecting said loading means and said memory cell.
- 58. The sense amplifier of claim 54 further comprising means for amplifying the sensed content of the memory cell, and wherein the means for driving further drives the load in response to the amplified sensed content.
- 59. A memory comprising:
a plurality of data memory cells, each data memory cell configurable to store one of a plurality of signal levels; a plurality of reference memory cells, each reference memory cell configurable to store one of a plurality of reference levels; a plurality of data sense amplifiers, each data sense amplifier being coupled to a group of said data memory cells; and a plurality of reference sense amplifiers, each reference sense amplifier being coupled to one of said reference cells, the data sense amplifiers and the reference sense amplifiers having a similar circuit structure.
- 60. The memory of claim 59 wherein each data sense amplifier comprises:
an input stage coupled to said group of data memory cells and having an output for providing a low impedance driver signal indicative of the contents of a selected one of said group of data memory cells; and a comparator coupled to the output of the input stage and to at least one reference voltage signal to generate at least one comparison signal indicative of the relation between the low impedance driver signal and the corresponding at least one reference voltage, wherein each reference sense comprises: an input stage coupled to said group of data memory cells and having an output for providing a low impedance driver signal indicative of the contents of a selected one of said group of data memory cells, the input stage of the reference sense amplifier having a similar circuit structure as the input stage of the data sense amplifier; and a comparator coupled to the output of the input stage and to at least one reference voltage signal to generate at least one comparison signal indicative of the relation between the low impedance driver signal and the corresponding at least one reference voltage, the comparator of the reference sense amplifier having a similar circuit structure as comparator of the data sense amplifier.
- 61. The memory of claim 59 further comprising:
a plurality of redundant memory cells, each redundant memory cell configurable to store one of a plurality of signal levels, the redundant memory cells being coupled to one of the plurality of reference sense amplifiers.
- 62. The memory of claim 61 wherein the reference sense amplifier comprises a feedback and precharge circuit to multiplex the reference memory cells and the redundant memory cells to a comparator for detecting the contents therein.
- 63. A memory comprising:
a plurality of data memory cells, each data memory cell configurable to store one of a plurality of signal levels; a plurality of reference memory cells, each reference memory cell configurable to store one of a plurality of reference levels; a plurality of redundant memory cells, each redundant memory cell configurable to store one of a plurality of signal levels; a plurality of data sense amplifiers, each data sense amplifier being coupled to a group of said data memory cells; and a plurality of first sense amplifiers, each first sense amplifier being coupled to one of said reference cells and to at least one redundant memory cells.
- 64. The memory of claim 63 wherein the first sense amplifiers comprise a feedback and precharge circuit to multiplex the reference memory cells and the redundant memory cells to a comparator for detecting the contents therein.
- 65. A memory comprising:
a plurality of data memory cells, each data memory cell configurable to store one of a plurality of signal levels; a plurality of reference memory cells, each reference memory cell configurable to store one of a plurality of reference levels; a plurality of data sense amplifiers, each data sense amplifier being coupled to a group of said memory cells; a plurality of reference sense amplifiers, each reference sense amplifier being coupled to one of said reference cells; and a plurality of reference cascode pull up circuits, each reference cascode pull up circuit being coupled to a corresponding one of said reference memory cells and one of said plurality of data memory cells.
- 66. A memory comprising:
a plurality of data memory cells, each data memory cell configurable to store one of a plurality of signal levels; a plurality of reference memory cells, each reference memory cell configurable to store one of a plurality of reference levels; a plurality of data sense amplifiers, each data sense amplifier being coupled to a group of said data memory cells; a plurality of reference sense amplifiers, each reference sense amplifier being coupled to one of said reference cells; a reference cascode circuit coupled to the reference sense amplifiers for controlling the reference sense amplifiers, the reference cascode circuit comprising a low impedance stage for providing a low impedance drivers signal to the reference sense amplifier, the data sense amplifiers including an input stage for loading a bitline coupled to the memory cell and having an output providing a low impedance driver signal indicative of the contents of a corresponding data memory cell, the sizing of the low impedance stage of the reference cascode circuit and the input stage of the data sense amplifier being in a relation to maintain a DC operating condition substantially the same for said input stages.
- 67. The memory of claim 66 wherein the reference cascode circuit includes a selectable pull-up circuit for selectable pull-up ratios, the reference levels.
- 68. A memory array comprising:
a plurality of memory cells arranged in a plurality of columns, a plurality of bit lines coupled to a corresponding one of said plurality of columns of memory cells; a plurality of sense amplifiers, each amplifier being disposed adjacent a group of said memory cells; each sense amplifier comprising:
an input stage for loading of a bit line coupled to the memory cell and having an output for providing a low impedance driver signal indicative of the contents of said memory cell; and a comparator coupled to the output of the input stage and to at least one reference voltage signal to generate at least one comparison signal indicative of the relation between the low impedance driver signal and the corresponding at least one reference voltage signal.
- 69. The memory of claim 68 further comprising a plurality of current sources disposed in a direction substantially perpendicular to the direction of the bit line to compensate for current changes in said direction.
- 70. A method for setting reference voltage levels in a multilevel memory system, the method comprising:
programming a first plurality of memory cells with global reference voltage levels; and programming a second plurality of memory cells with local reference voltage levels, each of the second plurality of memory cells being adjacent a corresponding plurality of data memory cells.
- 71. The method of claim 70 wherein said programming said second plurality of memory cells includes incremental programming.
- 72. The method of claim 71 wherein said incremental programming includes incrementally increasing a voltage to program in one of said plurality of memory cells and comparing said programmed voltage to a corresponding global reference voltage level, and repeating said increasing and comparison until the comparison indicates a match.
- 73. The method of claim 70 wherein said programming a first plurality of memory cells comprises verifying a programmed voltage in said memory cells by reading said memory cell and comparing said memory cell to sequentially comparing the read memory cell to a plurality of different voltage levels to determine the voltage level stored in said memory cell.
- 74. A method for reading a memory cell in a multilevel memory system, the method comprising:
comparing a voltage detected in said memory cell to a voltage stored in one of a plurality of local reference memory cells in series; and indicating the data stored in said read memory cell in the event that the said comparison indicates a read voltage of the memory cell above one above the local reference voltage levels and below the next highest local reference voltage level.
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is related to U.S. patent application Ser. No. 10/241,266, filed on even date herewith, entitled “Differential Sense Amplifier For Multilevel Non-Volatile Memory”, inventors Hieu Van Tran, Jack Edward Frayer, William John Saiki, and Michael Stephen Briner, the disclosure of which is incorporated herein by reference.