HIGH-SPEED CRYPTOGRAPHIC SYSTEM USING CHAOTIC SEQUENCES

BACKGROUND OF THE INVENTION

1. Statement of the Technical Field

The invention concerns cryptographic systems. More particularly, the invention concerns a high-speed cryptographic system utilizing digitally generated chaotic sequences.

2. Description of the Related Art

For many types of electronic records, such as medical records, email communications, credit cards records, and customer records, data is generally stored in unencrypted databases. Although numerous linear and non-linear cryptographic algorithms exist, such algorithms are typically not used for database encryption due to the latency issues, processing requirements, and/or security limitations.

In the case of database cryptographic systems using linear algorithms, the non-computation intensive nature of the encryption and decryption processes allow a user to quickly and efficiently decrypt one or more portions of the encrypted database. However, the linear nature of the encryption algorithm (i.e., non-complex) also means that the encryption scheme can be discovered within a reasonable time, allowing third parties access to the encrypted data. As a result, linear encryption algorithms are typically not suited for providing robust security to a determined cryptographer.

In contrast, non-linear encryption algorithms typically rely on a mathematical problem for which no efficient means of obtaining a solution is available and typically provide secure encryption. However, the complex nature of the non-linear algorithm also means that a computation intensive decryption process is typically required to decrypt even the smallest collection of data. More importantly, the nonlinear processes typically fail to permit decryption of an arbitrary portion of the data, requiring decryption of large amounts of data even when only a small portion of the plaintext is required. Accordingly, such algorithms are generally limited to low data rate transfer applications, such as text messaging or particularly high value information.

For example, multiple pseudo-random number generators can generate exceedingly complex pseudo-random sequences for encoding databases. However, such cryptographic systems generally produce complex pseudo-random number sequences that still possess statistical artifacts. Accordingly, such pseudo-random sequences typically require generation of the full sequence in order to decrypt any portion of an encrypted data store. Furthermore, the sequences are typically difficult to unravel and exploit as the mappings become more complex; the encryption process and decryption process are typically asymmetric, placing a computational burden on one side of the process. A desirable cryptographic system for large stores of data will have symmetric computational requirements as well as common processing components. As a result the latency and computing requirements for such encrypted data stores generally becomes prohibitive as the size of the data store is increased.

As a result of the limitations of linear and non-linear encryption algorithms, many data stores are typically retained using little or no amount of encryption. Therefore, there is a need for a high-speed cryptographic system with moderate security for encryption of large stores and transfers of data as present in databases, email, medical records, or internet transfers. There is also a need for such cryptographic systems to have reduced latency and computing requirements when decrypting only a portion of the data. Additionally, there is a desire that the computational requirements and/or components used in encrypting and decrypting the information be relatively symmetric.

SUMMARY

Embodiments of the invention provide systems and methods for high-speed cryptography using chaotic sequences. In a first embodiment of the invention, a cryptographic decryption system is provided. The system includes a data stream receiving device configured for receiving a modified data stream, the modified data stream includes an input data stream representing a plurality of data entries encrypted using a chaotic sequence of digits. The system also includes a user processing device configured for receiving user access information or generating user information from user characteristics, the user access information specifying an initial value for the chaotic sequence of digits and data field location information associated with selected ones of the plurality of data entries. The system further includes a chaotic sequence generator coupled to the user processing device, the chaotic sequence generator configured for generating one or more decryption sequences based on the initial value and the data field location information specified in the user access information. The system additionally includes a decrypter coupled to the chaotic sequence generator and the data stream receiving device, the decrypter configured for generating an output data stream from the modified data stream by applying the decryption sequences to the modified data stream.

In a second embodiment of the invention, a cryptographic encryption system is also provided. The system includes a data stream receiving device configured for receiving an input data stream including a plurality of data entries. The system also includes a user processing device configured for receiving user access information or generating user information from user characteristics, the user access information specifying an initial value for generating a chaotic sequence of digits and data field location information associated with selected ones of the plurality of data entries. The system further includes a chaotic sequence generator coupled to the user processing device, the chaotic sequence generator configured for generating one or more encryption sequences based on the initial value and the data field location information specified in the user access information. The system additionally includes an encrypter coupled to the chaotic sequence generator and the data stream receiving device, the encrypter configured for generating a modified data stream from the input data stream by applying the encryption sequences to the input data stream.

In a third embodiment of the invention, a method for secure communications using a modified data stream is provided. In the method, the modified data stream is based on an input data stream representing a plurality of data entries and a chaotic sequence of digits. The method includes decrypting the modified data at a decryption device, the decrypting including the steps of receiving the modified data stream and receiving user access information, the user access information specifying an initial value for the chaotic sequence of digits and data field location information associated with selected ones of the plurality of data entries. The decrypting also includes generating one or more decryption sequences based on the initial value and the data field location information specified in the received user access information, and utilizing the decryption sequences to the modified data stream to generate an output data stream from the modified data stream. The method can also include the step of encrypting an input data stream, prior to the decrypting of the modified data stream, at an encryption device to produce the modified data stream. This encryption step to produce the modified data stream may optionally be followed by storage of the modified data in a data store, such as a database, for later retrieval or access.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments will be described with reference to the following drawing figures, in which like numerals represent like items throughout the figures, and in which:

FIG. 1 is a conceptual diagram of a chaotic sequence generator in accordance with an embodiment of the invention.

FIG. 2 is a flow diagram of an exemplary method for generating a chaotic sequence in accordance with an embodiment of the invention.

FIG. 3 is a block diagram of an exemplary chaotic sequence generator in accordance with an embodiment of the invention.

FIG. 4 is a conceptual diagram of the relationship between an exemplary data stream representing a database and an exemplary chaotic sequence generated in accordance with an embodiment of the invention.

FIG. 5 is a block diagram of an exemplary cryptographic system in accordance with an embodiment of the invention.

FIG. 6 is a block diagram of the encryption device for FIG. 6 in accordance with an embodiment of the invention.

FIG. 7 is a block diagram of the decryption device of FIG. 6 in accordance with an embodiment of the invention.

FIG. 8 is a flow diagram of an exemplary method for encrypting and decrypting database information in accordance with an embodiment of the invention.

DETAILED DESCRIPTION

In the various embodiments of the invention, systems and methods are provided for cryptographic systems using a digitally generated chaotic sequence. Such chaos-based cryptographic systems include chaotic encryption systems and chaotic decryption systems that include chaos generators, which are capable of producing a chaotic sequence. In particular, the various embodiments of the invention provide systems and methods in which one or more portions of the chaotically encrypted data are decrypted using a permission-based user key. The user key specifies which records in a database a particular user is allowed to decrypt and how to generate the chaotic sequence for decrypting these records.

The invention will now be described more fully hereinafter with reference to accompanying drawings, in which illustrative embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. For example, the invention can be embodied as a method, a system, or a computer program product. Accordingly, the invention can take the form as an entirely hardware embodiment, an entirely software embodiment or a hardware/software embodiment.

Generation of Chaotic Sequences

One aspect of the invention provides for a digitally generated chaotic sequence that is used to modify a data stream by increasing its entropy, a process commonly called encryption. In this regard, it should be appreciated that the presence of any discernible pattern in a chaotic sequence is much more difficult to identify as compared to patterns that emerge over time with conventional pseudo-random number sequences. As such, a chaotic sequence is characterized by a greater degree of apparent randomness, more precisely measured as entropy, as compared to these conventional pseudo-random number sequences, providing a higher degree of security. The same digital chaotic sequence used in encryption of data is then capable of decrypting the data, returning it to its prior state.

Referring now to FIG. 1, there is provided a conceptual diagram of a chaotic sequence generator 100 in accordance with the various embodiments of the invention. As shown in FIG. 1, generation of the chaotic sequence begins at a processing devices 102₀, . . . , 102_N-1where N polynomial equations f₀(x(nT)), . . . , f_N-1(x(nT)) are selected. The N polynomial equations f₀(x(nT)), . . . , f_N-1(x(nT)) can be selected as the same polynomial equation or as different polynomial equations. In the various embodiments of the invention, the N polynomial equations f₀(x(nT)), . . . , f_N-1(x(nT)) are selected as irreducible polynomial equations having chaotic properties in Galois field arithmetic. Such irreducible polynomial equations include, but are not limited to, irreducible cubic polynomial equations and irreducible quadratic polynomial equations. The phrase “irreducible polynomial equation” as used herein refers to a polynomial equation that cannot be expressed as a product of at least two nontrivial polynomial equations over the same Galois field. For example, the polynomial equation f(x(nT)) is irreducible if there does not exist two (2) non-constant polynomial equations g(x(nT)) and h(x(nT)) in x(nT) with rational coefficients such that f(x(nT))=g(x(nT))·h(x(nT)).

As will be understood by one of ordinary skill in the art, each of the N polynomial equations f₀(x(nT)), . . . , f_N-1(x(nT)) can be solved independently to obtain a respective solution. Each solution can be expressed as a residue number system (RNS) residue value using RNS arithmetic operations, i.e. modulo operations. Modulo operations are well known to one of ordinary skill in the art. Thus, such operations will not be described in great detail herein. However, it should be appreciated that a RNS residue representation for some weighted value “a” can be defined by mathematical Equation (1).

R={a modulo m₀, a modulo m₁, . . . , a modulo m_N-1} (1)

where R is a RNS residue N-tuple value representing a weighted value “a”. Further, R(nT) can be a representation of the RNS solution of a polynomial equation f(x(nT)) defined as R(nT)={f₀(x(nT)) modulo m₀, f₁(x(nT)) modulo m₁, . . . , f_N-1(x(nT)) modulo m_N-1}. m₀, m₁, . . . , m_N-1respectively are the moduli for RNS arithmetic operations applicable to each polynomial equation f₀(x(nT)), f_N-1(x(nT)).

From the foregoing, it will be appreciated that the RNS employed for solving each of the polynomial equations f₀(x(nT)), . . . , f_N-1(x(nT)) respectively has a selected modulus value m₀, m₁, . . . , m_N-1. The modulus value chosen for each RNS moduli is preferably selected to be relatively prime numbers p₀, p₁, . . . , p_N-1. The phrase “relatively prime numbers” as used herein refers to a collection of natural numbers having no common divisors except one (1). Consequently, each RNS arithmetic operation employed for expressing a solution as an RNS residue value uses a different prime number P₀, p₁, . . . , p_N-1as a moduli m₀, m₁, . . . , m_N-1.

Those of ordinary skill in the art will appreciate that the RNS residue value calculated as a solution to each one of the polynomial equations f₀(x(nT)), . . . , f_N-1(x(nT)) will vary depending on the choice of prime numbers p₀, p₁, . . . p_N-1selected as a moduli m₀, m₁, . . . , m_N-1. Moreover, the range of values will depend on the choice of relatively prime numbers p₀, p₁, . . . , p_N-1selected as a moduli m₀, m₁, . . . , m_N-1. For example, if the prime number five hundred three (503) is selected as modulus m₀, then an RNS solution for a first polynomial equation f₀(x(nT)) will have an integer value between zero (0) and five hundred two (502). Similarly, if the prime number four hundred ninety-one (491) is selected as modulus m₁, then the RNS solution for a second polynomial equation f₀(x(nT)) has an integer value between zero (0) and four hundred ninety (490).

According to an embodiment of the invention, each of the N polynomial equations f₀(x(nT)), . . . , f_N-1(x(nT)) is selected as an irreducible cubic polynomial equation having chaotic properties in Galois field arithmetic. Each of the N polynomial equations f₀(x(nT)), . . . , f_N-1(x(nT)) can also be selected to be a constant or varying function of time. The irreducible cubic polynomial equation is defined by a mathematical Equation (2).

f(x(nT))=Q(k)x³(nT)+R(k)x²(nT)+S(k)x(nT)+C(k,L) (2)

where n is a sample time index value. k is a polynomial time index value. L is a constant component time index value. T is a fixed constant having a value representing a time increment. Q, R, and S are coefficients that define the polynomial equation f(x(nT)). C is a coefficient of x(nT) raised to a zero power and is therefore a constant for each polynomial characteristic. In one embodiment, a value of C is selected which empirically is determined to produce an irreducible form of the stated polynomial equation f(x(nT)) for a particular prime modulus. For a given polynomial with fixed values for Q, R, and S more than one value of C can exist, each providing a unique iterative sequence. Still, the invention is not limited in this regard.

According to another embodiment of the invention, the N polynomial equations f₀(x(nT)) . . . f_N-1(x(nT)) are identical exclusive of a constant value C. For example, a first polynomial equation f₀(x(nT)) is selected as f₀(x(nT))=3x³(nT)+3x²(nT)+x(nT)+C₀. A second polynomial equation f₁(x(nT)) is selected as f₁(x(nT))=3x³(nT)+3x²(nT)+x(nT)+C₁. A third polynomial equation f₂(x(nT)) is selected as f₂(x(nT))=3x³(nT)+3x²(nT)+x(nT)+C₂, and so on. Each of the constant values C₀, C₁, . . . , C_N-1is selected to produce an irreducible form in a residue ring of the stated polynomial equation f(x(nT))=3x³(nT)+3x²(nT)+x(nT)+C. In this regard, it should be appreciated that each of the constant values C₀, C₁, . . . , C_N-1is associated with a particular modulus m₀, m₁, . . . , m_N-1value to be used for RNS arithmetic operations when solving the polynomial equation f(x(nT)). Such constant values C₀, C₁, . . . , C_N-1and associated modulus m₀, m₁, . . . , m_N-1values which produce an irreducible form of the stated polynomial equation f(x(nT)) are listed in the following Table (1).

TABLE 1

Sets of constant values

Moduli values m₀, m₁, . . . , m_N−1:
C₀, C₁, . . . , C_N−1:

3
{1, 2}

5
{1, 3}

11
{4, 9}

29
{16, 19}

47
{26, 31}

59
{18, 34}

71
{10, 19, 20, 29}

83
{22, 26, 75, 79}

101
{27, 38, 85, 96}

131
{26, 39, 77, 90}

137
{50, 117}

149
{17, 115, 136, 145}

167
{16, 32, 116, 132}

173
{72, 139}

197
{13, 96, 127, 179}

233
{52, 77}

251
{39, 100, 147, 243}

257
{110, 118}

269
{69, 80}

281
{95, 248}

293
{37, 223}

311
{107, 169}

317
{15, 55}

347
{89, 219}

443
{135, 247, 294, 406}

461
{240, 323}

467
{15, 244, 301, 425}

479
{233, 352}

491
{202, 234}

503
{8, 271}

Still, the invention is not limited in this regard.

The number of discrete magnitude states (dynamic range) that can be generated with the system shown in FIG. 1 will depend on the quantity of polynomial equations N and the modulus values m₀, m₁, . . . , m_N-1selected for the RNS number systems. In particular, this value can be calculated as the product M=m₀·m₁, ·m₃·m₄· . . . ·m_N-2.

Referring again to FIG. 1, it should be appreciated that each of the RNS solutions Nos. 1 through N is expressed in a binary number system representation. As such, each of the RNS solutions Nos. 1 through N is a binary sequence of bits. Each bit of the sequence has a zero (0) value or a one (1) value. Each binary sequence has a bit length selected in accordance with a particular moduli.

According to an embodiment of the invention, each binary sequence representing a residue value has a bit length (BL) defined by a mathematical Equation (3).

BL=Ceiling[Log 2(m)] (3)

where m is selected as one of moduli m₀, m₁, . . . , m_N-1. Ceiling[u] refers to a next highest integer with respect to an argument u.

In order to better understand the foregoing concepts, an example is useful. In this example, six (6) relatively prime moduli are used to solve six (6) irreducible polynomial equations f₀(x(nT)), . . . , f₅(x(nT)). A prime number p₀associated with a first modulus m₀is selected as five hundred three (503). A prime number p₁associated with a second modulus m₁is selected as four hundred ninety one (491). A prime number p₂associated with a third modulus m₂is selected as four hundred seventy-nine (479). A prime number p₃associated with a fourth modulus m₃is selected as four hundred sixty-seven (467). A prime number p₄associated with a fifth modulus m₄is selected as two hundred fifty-seven (257). A prime number p₅associated with a sixth modulus m₅is selected as two hundred fifty-one (251). Possible solutions for f₀(x(nT)) are in the range of zero (0) and five hundred two (502) which can be represented in nine (9) binary digits. Possible solutions for f₁(x(nT)) are in the range of zero (0) and four hundred ninety (490) which can be represented in nine (9) binary digits. Possible solutions for f₂(x(nT)) are in the range of zero (0) and four hundred seventy eight (478) which can be represented in nine (9) binary digits. Possible solutions for f₃(x(nT)) are in the range of zero (0) and four hundred sixty six (466) which can be represented in nine (9) binary digits. Possible solutions for f₄(x(nT)) are in the range of zero (0) and two hundred fifty six (256) which can be represented in nine (9) binary digits. Possible solutions for f₅(x(nT)) are in the range of zero (0) and two hundred fifty (250) which can be represented in eight (8) binary digits. Arithmetic for calculating the recursive solutions for polynomial equations f₀(x(nT)), . . . , f₄(x(nT)) requires nine (9) bit modulo arithmetic operations. The arithmetic for calculating the recursive solutions for polynomial equation f₅(x(nT)) requires eight (8) bit modulo arithmetic operations. In aggregate, the recursive results f₀(x(nT)), . . . , f₅(x(nT)) represent values in the range from zero (0) to M−1. The value of M is calculated as follows: p₀·p₁·p₂·p₃·p₄·p₅=503·491·479·467·257·251=3,563,762,191,059,523. The binary number system representation of each RNS solution can be computed using Ceiling[Log 2(3,563,762,191,059,523)]=Ceiling[51.66]=52 bits. Because each polynomial is irreducible, all 3,563,762,191,059,523 possible values are computed resulting in a sequence repetition time of M times T seconds, i.e, a sequence repetition times an interval of time between the computation of each values in the sequence of generated values. Still, the invention is not limited in this regard.

Referring again to FIG. 1, the generation of a chaotic sequence continues with mapping operation performed by a mapping device 104. The mapping operations involve mapping the RNS solutions Nos. 1 through N to a weighted number system representation to form a chaotic sequence output. The phrase “weighted number system” as used herein refers to a number system other than a residue number system. Such weighted number systems include, but are not limited to, an integer number system, a binary number system, an octal number system, and a hexadecimal number system.

In some embodiments of the invention, the RNS solutions Nos. 1 through N are mapped to a weighted number system representation by determining a series of digits in the weighted number system based on the RNS solutions Nos. 1 through N. The term “digit” as used herein refers to a symbol of a combination of symbols to represent a number. For example, a digit can be a particular bit of a binary sequence. In other embodiments of the invention, the RNS solutions Nos. 1 through N are mapped to a weighted number system representation by identifying a number in the weighted number system that is defined by the RNS solutions Nos. 1 through N. According to yet another embodiment of the invention, the RNS solutions Nos. 1 through N are mapped to a weighted number system representation by identifying a truncated portion of a number in the weighted number system that is defined by the RNS solutions Nos. 1 through N. The truncated portion can include any serially arranged set of digits of the number in the weighted number system. The truncated portion can also be exclusive of a most significant digit of the number in the weighted number system. The phrase “truncated portion” as used herein refers to a chaotic sequence with one or more digits removed from its beginning and/or ending. The phrase “truncated portion” also refers to a segment including a defined number of digits extracted from a chaotic sequence. The phrase “truncated portion” also refers to a result of a partial mapping of the RNS solutions Nos. 1 through N to a weighted number system representation.

In some embodiments of the invention, a mixed-radix conversion method is used for mapping RNS solutions Nos. 1 through N to a weighted number system representation. “The mixed-radix conversion procedure to be described here can be implemented in” [modulo moduli only and not modulo the product of moduli.] See Residue Arithmetic and Its Applications To Computer Technology, written by Nicholas S. Szabo & Richard I. Tanaka, McGraw-Hill Book Co., New York, 1967. [In a mixed-radix number system,] “a number x may be expressed in a mixed-radix form:

$\begin{matrix} x = a_{N} \prod_{i = 1}^{N - 1} R_{i} + \dots + a_{3} R_{1} R_{2} + a_{2} R_{1} + a_{1} & (4) \end{matrix}$

where the R_iare the radices, the a_iare the mixed-radix digits, and 0≦a_i<R_i. For a given set of radices, the mixed-radix representation of x is denoted by (a_n, a_n-1, . . . , a₁) where the digits are listed order of decreasing significance.” See Id. “The multipliers of the digits a_iare the mixed-radix weights where the weight of a_iis

$\begin{matrix} \prod_{j = 1}^{i - 1} R_{j} for i \neq 1. ” See Id . & (5) \end{matrix}$

For conversion from the RNS to a mixed-radix system, a set of moduli are chosen so that m_i=R_i. A set of moduli are also chosen so that a mixed-radix system and a RNS are said to be associated. “In this case, the associated systems have the same range of values, that is

$\begin{matrix} \prod_{i = 1}^{N} m_{i} . & (6) \end{matrix}$

The mixed-radix conversion process described here may then be used to convert from the [RNS] to the mixed-radix system.” See Id.

“If m_i=R_i, then the mixed-radix expression is of the form:

$\begin{matrix} x = a_{N} \prod_{i = 1}^{N - 1} m_{i} + \dots + a_{3} m_{1} m_{2} + a_{2} m_{1} + a_{1} & (7) \end{matrix}$

where a_iare the mixed-radix coefficients. The a_iare determined sequentially in the following manner, starting with a₁.” See Id.

$\begin{matrix} x = a_{N} \prod_{i = 1}^{N - 1} m_{i} + \dots + a_{3} m_{1} m_{2} + a_{2} m_{1} + a_{1} & (8) \end{matrix}$

is first taken modulo m₁. “Since all terms except the last are multiples of m₁, we have x_m₁=a₁. Hence, a₁is just the first residue digit.” See Id.

“To obtain a₂, one first forms x−a₁in its residue code. The quantity x−a₁is obviously divisible by m₁. Furthermore, m₁is relatively prime to all other moduli, by definition. Hence, the division remainder zero procedure [Division where the dividend is known to be an integer multiple of the divisor and the divisor is known to be relatively prime to M] can be used to find the residue digits of order 2 through N of

$\frac{x - a_{1}}{m_{1}} .$

Inspection of

$\begin{matrix} [x = a_{N} \prod_{i = 1}^{N - 1} m_{i} + \dots + a_{3} m_{1} m_{2} + a_{2} m_{1} + a_{1}] & (9) \end{matrix}$

shows then that x is a₂. In this way, by successive subtracting and dividing in residue notation, all of the mixed-radix digits may be obtained.” See Id.

“It is interesting to note that

$\begin{matrix} a_{1} = {〈 x 〉}_{m_{1}}, a_{2} = {〈 ⌊ \frac{x}{m_{1}} ⌋ 〉}_{m_{2}}, a_{3} = {〈 ⌊ \frac{x}{m_{1} m_{2}} ⌋ 〉}_{m_{3}} & (10) \end{matrix}$

and in general for i>1

$\begin{matrix} a_{i} = {〈 ⌊ \frac{x}{m_{1} m_{2} \dots m_{i - 1}} ⌋ 〉}_{m_{i}} & (11) \end{matrix}$

.” See Id. From the preceding description it is seen that the mixed-radix conversion process is iterative. The conversion can be modified to yield a truncated result. Still, the invention is not limited in this regard.

In some embodiments of the invention, a Chinese remainder theorem (CRT) arithmetic operation is used to map the RNS solutions Nos. 1 through N to a weighted number system representation. The CRT arithmetic operation can be defined by a mathematical Equation (12).

$\begin{matrix} Y (nT) = {〈 \begin{matrix} [{〈 (3 x_{0}^{2} (nT) + 3 x_{0}^{2} (nT) + x_{0} (nT) + C_{0}) b_{0} 〉}_{p_{0}}] \frac{M}{p_{0}} + \dots + \\ [{〈 (3 x_{N - 1}^{3} (nT) + 3 x_{N - 1}^{2} (nT) + x_{N - 1} (nT) + C_{N - 1}) b_{N - 1} 〉}_{p_{N - 1}}] \frac{M}{p_{N - 1}} \end{matrix} 〉}_{M} & (12) \end{matrix}$

where Y(nT) is the result of the CRT arithmetic operation. n is a sample time index value. T is a fixed constant having a value representing a time interval or increment. x₀-x_N-1are RNS solutions Nos. 1 through N. p₀, p₁, . . . , p_N-1are prime number moduli. M is a fixed constant defined by a product of the relatively prime numbers p₀, p₁, . . . p_N-1. b₀, b₁, . . . , b_N-1are fixed constants that are chosen as the multiplicative inverses of the product of all other primes modulo p₀, p₁, . . . , p_N-1, respectively. Equivalently,

$\begin{matrix} b_{j} = {(\frac{M}{p_{j}})}^{- 1} \mod p_{j} . & (13) \end{matrix}$

The b_j's enable an isomorphic and equal mapping between an RNS N-tuple value representing a weighted number and said weighted number. However without loss of chaotic properties, the mapping need only be unique and isomorphic. As such, a weighted number x can map into a tuple y. The tuple y can map into a weighted number z. The weighted number x is not equal to x as long as all tuples map into unique values for z in a range from zero (0) to M−1. Therefore, in some embodiments of the invention, all b_j's can be set equal to one or more values without practical loss of the chaotic properties. Different values of b_japply a bijective mapping within the RNS, but do not interfere with the CRT combination process.

The chaotic sequence output Y(nT) can be expressed in a binary number system representation. As such, the chaotic sequence output Y(nT) can be represented as a binary sequence. Each bit of the binary sequence has a zero (0) value or a one (1) value. The chaotic sequence output Y(nT) can have a maximum bit length (MBL) defined by a mathematical Equation (15).

MBL=Ceiling[Log 2(M) (15)

where M is the product of the relatively prime numbers p₀, p₁, . . . , p_N-1selected as moduli m₀, m₁, . . . , m_N-1. In this regard, it should be appreciated the M represents a dynamic range of a CRT arithmetic operation. The phrase “dynamic range” as used herein refers to a maximum possible range of outcome values of a CRT arithmetic operation. Accordingly, the CRT arithmetic operation generates a chaotic numerical sequence with a periodicity equal to the inverse of the dynamic range M. The dynamic range requires a Ceiling[Log 2(M)] bit precision.

In some embodiments of the invention, M equals three quadrillion five hundred sixty-three trillion seven hundred sixty-two billion one hundred ninety-one million fifty-nine thousand five hundred twenty-three (3,563,762,191,059,523). By substituting the value of M into Equation (6), the bit length (BL) for a chaotic sequence output Y expressed in a binary system representation can be calculated as follows: BL=Ceiling[Log 2(3,563,762,191,059,523)=52 bits. As such, the chaotic sequence output Y(nT) is a fifty-two (52) bit binary sequence having an integer value between zero (0) and three quadrillion five hundred sixty-three trillion seven hundred sixty-two billion one hundred ninety-one million fifty-nine thousand five hundred twenty-two (3,563,762,191,059,522), inclusive. Still, the invention is not limited in this regard. For example, the chaotic sequence output Y(nT) can be a binary sequence representing a truncated portion of a value between zero (0) and M−1. In such a scenario, the chaotic sequence output Y(nT) can have a bit length less than Ceiling[Log 2(M)]. It should be noted that while truncation affects the dynamic range of the system it has no effect on the periodicity of a generated sequence.

As one of ordinary skill in art will recognize, the above-described chaotic sequence generation can be iteratively performed. In such a scenario, a feedback mechanism (e.g., a feedback loop) can be provided so that a variable “x” of a polynomial equation can be selectively defined as a solution computed in a previous iteration. Mathematical Equation (2) can be rewritten in a general iterative form: f(x(nT)=Q(k)x³((n−1)T)+R(k)x²((n−1)T)+S(k)x((n−1)T)+C(k,L). For example, a fixed coefficient polynomial equation is selected as f(x(n·1 ms))=3x³((n−1)+1 ms)+3x²((n−1)·1 ms)+x((n−1)·1 ms)+8 modulo 503. n is a variable having a value defined by an iteration being performed. x is a variable having a value allowable in a residue ring. In a first iteration, n equals one (1) and x is selected as two (2) which is allowable in a residue ring. By substituting the value of n and x into the stated polynomial equation f(x(nT)), a first solution having a value forty-six one (46) is obtained. In a second iteration, n is incremented by one and x equals the value of the first solution, i.e., forty-six (46) resulting in the solution 298, 410 mod 503 or one hundred thirty-one (131). In a third iteration, n is again incremented by one and x equals the value of the second solution.

Referring now to FIG. 2, there is provided a flow diagram of an exemplary method 200 for generating a chaotic sequence according to an embodiment of the invention. As shown in FIG. 2, the method 200 begins with step 202 and continues with step 204. In step 204, a plurality of polynomial equations f₀(x(nT)), . . . , f_N-1(x(nT)) are selected. In this regard, it should be appreciated that the polynomial equations f₀(x(nT)), . . . , f_N-1(x(nT)) can be selected as the same polynomial equation except for a different constant term or different polynomial equations. After step 204, step 206 is performed where a determination for each polynomial equation f₀(x(nT)), . . . , f_N-1(x(nT)) is made as to which combinations of RNS moduli m₀, m₁, . . . , m_N-1used for arithmetic operations and respective constant values C₀, C₁, . . . , C_N-1generate irreducible forms of each polynomial equation f₀(x(nT)), . . . , f_N-1(x(nT)). In step 208, a modulus is selected for each polynomial equation f₀(x(nT)), . . . , f_N-1(x(nT)) that is to be used for RNS arithmetic operations when solving the polynomial equation f₀(x(nT)), . . . , f_N-1(x(nT)). In this regard, it should be appreciated that the modulus is selected from the moduli identified in step 206. It should also be appreciated that a different modulus must be selected for each polynomial equation f₀(x(nT)), . . . , f_N-1(x(nT)).

As shown in FIG. 2, the method 200 continues with step 210. In step 210, a constant C_mis selected for each polynomial equation f₀(x(nT)), . . . , f_N-1(x(nT)) for which a modulus is selected. Each constant C_mcorresponds to the modulus selected for the respective polynomial equation f₀(x(nT)), . . . , f_N-1(x(nT)). Each constant C_mis selected from among the possible constant values identified in step 206 for generating an irreducible form of the respective polynomial equation f₀(x(nT)), . . . , f_N-1(x(nT)).

After step 210, the method 200 continues with step 212. In step 212, a value for time increment “T” is selected. Thereafter, an initial value for “x” is selected. In this regard, it should be appreciated that the initial value for “x” can be any value allowable in a residue ring. Subsequently, step 216 is performed where RNS arithmetic operations are used to iteratively determine RNS solutions for each of the stated polynomial equations f₀(x(nT)), . . . , f_N-1(x(nT)). In step 218, a series of digits in a weighted number system are determined based in the RNS solutions. This step can involve performing a mixed radix arithmetic operation or a CRT arithmetic operation using the RNS solutions to obtain a chaotic sequence output.

After step 218, the method 200 continues with a decision step 220. If a chaos generator is not terminated (220: NO), then step 224 is performed where a value of “x” in each polynomial equation f₀(x(nT)), . . . , f_N-1(x(nT)) is set equal to the RNS solution computed for the respective polynomial equation f₀(x(nT)), f_N-1(x(nT)) in step 216. Subsequently, the method 200 returns to step 216. If the chaos generator is terminated (220: YES), then step 222 is performed where the method 200 ends.

One of ordinary skill in the art will appreciate that the method 200 is only one exemplary method for generating a chaotic sequence. However, the invention is not limited in this regard and any other method for generating a chaotic sequence can be used without limitation.

Referring now to FIG. 3, there is illustrated an exemplary chaotic sequence generator 300 in accordance with an embodiment of the invention. The chaotic sequence generator 300 is comprised of hardware and/or software configured to generate a digital chaotic sequence. In this regard, it should be appreciated that the chaotic sequence generator 300 is comprised of computing processors 302₀-302_N-1. The chaotic sequence generator 300 is also comprised of a mapping processor 304. Each computing processor 302₀-302_N-1is coupled to the mapping processor 304 by a respective data bus 306₀-306_N-1. As such, each computing processor 302₀-302_N-1is configured to communicate data to the mapping processor 304 via a respective data bus 306₀-306_N-1. The mapping processor 304 can be coupled to an external device (not shown) via a data bus 308. In this regard, it should be appreciated that the external device (not shown) includes, but is not limited to, a cryptographic device configured to combine or modify a signal in accordance with a chaotic sequence output.

Referring again to FIG. 3, the computing processors 302₀-302_N-1are comprised of hardware and/or software configured to solve N polynomial equations f₀(x(nT)), . . . , f_N-1(x(nT)) to obtain a plurality of solutions. The N polynomial equations f₀(x(nT)), . . . , f_N-1(x(nT)) can be irreducible polynomial equations having chaotic properties in Galois field arithmetic. Such irreducible polynomial equations include, but are not limited to, irreducible cubic polynomial equations and irreducible quadratic polynomial equations. The N polynomial equations f₀(x(nT)) . . . f_N-1(x(nT)) can also be identical exclusive of a constant value. The constant value can be selected so that a polynomial equation f₀(x(nT)), . . . , f_N-1(x(nT)) is irreducible for a predefined modulus. The N polynomial equations f₀(x(nT)), . . . , f_N-1(x(nT)) can further be selected as a constant or varying function of time.

Each of the solutions can be expressed as a unique residue number system (RNS) N-tuple representation. In this regard, it should be appreciated that the computing processors 302₀-302_N-1employ modulo operations to calculate a respective solution for each polynomial equation f₀(x(nT)), . . . , f_N-1(x(nT)) using modulo based arithmetic operations. Each of the computing processors 302₀-302_N-1are comprised of hardware and/or software configured to utilize a different relatively prime number p₀, p₁, . . . , p_N-1as a moduli m₀, m₁, . . . , m_N-1for modulo based arithmetic operations. The computing processors 302₀-302_N-1are also comprised of hardware and/or software configured to utilize modulus m₀, m₁, . . . , m_N-1selected for each polynomial equation f₀(x(nT)), . . . , f_N-1(x(nT)) so that each polynomial equation f₀(x(nT)), . . . , f_N-1(x(nT)) is irreducible. The computing processors 302₀-302_N-1are further comprised of hardware and/or software configured to utilize moduli m₀, m₁, . . . , m_N-1selected for each polynomial equation f₀(x(nT)), . . . , f_N-1(x(nT)) so that solutions iteratively computed via a feedback mechanism 310₀-310_N-1are chaotic. In this regard, it should be appreciated that the feedback mechanisms 310₀-310_N-1are provided so that the solutions for each polynomial equation f₀(x(nT)), . . . , f_N-1(x(nT)) can be iteratively computed. Accordingly, the feedback mechanisms 310₀-310_N-1are comprised of hardware and/or software configured to selectively define a variable “x” of a polynomial equation as a solution computed in a previous iteration.

Referring again to FIG. 3, the computing processors 302₀-302_N-1are further comprised of hardware and/or software configured to express each of the RNS residue values in a binary number system representation. In this regard, the computing processors 302₀-302_N-1can employ an RNS-to-binary conversion method. Such methods are generally known to one of ordinary skill in the art and therefore will not be described in great detail herein. However, it should be appreciated that any such method can be used without limitation. It should also be appreciated that the residue values expressed in binary number system representations are hereinafter referred to as moduli solutions Nos. 1 through N comprising the elements of an RNS N-tuple.

According to an embodiment of the invention, the computing processors 302₀-302_N-1are further comprised of memory based tables (not shown) containing pre-computed residue values in a binary number system representation. The address space of each memory table is at least from zero (0) to m_mfor all m, m₀through m_N-1. On each iteration, the table address is used to initiate the sequence. Still, the invention is not limited in this regard.

Referring again to FIG. 3, the mapping processor 304 is comprised of hardware and/or software configured to map the moduli (RNS N-tuple) solutions Nos. 1 through N to a weighted number system representation. The result is a series of digits in the weighted number system based on the moduli solutions Nos. 1 through N. For example, the mapping processor 304 can be comprised of hardware and/or software configured to determine the series of digits in the weighted number system based on the RNS residue values using a Chinese Remainder Theorem process. In this regard, it will be appreciated by one of ordinary skill in the art that the mapping processor 304 is comprised of hardware and/or software configured to identify a number in the weighted number system that is defined by the moduli solutions Nos. 1 through N.

In the various embodiments of the invention, the mapping processor 304 can be comprised of hardware and/or software configured to identify a truncated portion of a number in the weighted number system that is defined by the moduli solutions Nos. 1 through N. For example, the mapping processor 304 can also be comprised of hardware and/or software configured to select the truncated portion to include any serially arranged set of digits of the number in the weighted number system. Further, the mapping processor 304 can include hardware and/or software configured to select the truncated portion to be exclusive of a most significant digit when all possible weighted numbers represented by P bits are not mapped, i.e., when M−1<2^P. P is a fewest number of bits required to achieve a binary representation of the weighted numbers. Still, the invention is not limited in this regard.

Referring again to FIG. 3, the mapping processor 304 is comprised of hardware and/or software configured to express a chaotic sequence in a binary number system representation. In this regard, it should be appreciated that the mapping processor 304 can employ a weighted-to-binary conversion method. Such methods are generally known to one of ordinary skill in the art and therefore will not be described in great detail herein. However, it should be appreciated that any such method can be used without limitation.

One of ordinary skill in the art will appreciate that the chaotic generator 300 shown in FIG. 3 is an exemplary architecture for a chaotic generator. However, the invention is not limited in this regard and any other chaotic generator architecture can be used without limitation.

High-Speed Cryptography Using Chaotic Sequences

As, previously described, one aspect of the invention is to provide a permission-based user key for decrypting one or more portions of a large collection of data, such as a database, using chaotic encryption without requiring intense computation. A key, as used herein, refers to any piece of information that determines the functional output of a cryptographic algorithm. That is, a key provides information that allows the cryptographic algorithm to generate a resulting encryption data sequence or decryption data sequence used for encrypting or decrypting data. Although the various embodiments of the invention will be described with respect to exemplary key management techniques, transmission methods, and handling precautions, the various embodiments of the invention are not limited in this regard. Any mechanism for allocating and distributing keys to users, in a fashion that ensures distinct users or user groups have distinct keys that are protected from dissemination to unintended users, can be used with the various embodiments of the invention.

FIG. 4 shows a conceptual diagram of the relationship between an exemplary encrypted data stream 402, representing a database, and an exemplary chaotic sequence of digits 404 generated in accordance with an embodiment of the invention. In FIG. 4, the data stream 402 represents a database having a plurality of entries A1-A4, B1-B4, C1-C4, and D1-D4 associated with fields Ax, Bx, Cx, and Dx, respectively. However, the invention is not limited in this regard and any database including any number of entries and/or fields, having the same or variable lengths, can be used with the various embodiments of the invention. As shown in FIG. 4, the data stream 402 can be associated with a chaotic sequence 404, which provided the encryption digits 406 for each bit in the data stream 402. In FIG. 4, each entry is associated with a particular range of digits 406. More precisely, with reference to FIGS. 1-3, each entry is associated with a particular interval of time of the chaotic sequence. For example, entry A1 is associated with the digits 406 generated between t0 and t1. Entry B1 is associated with the digits 406 between t1 and t2. Likewise, the remaining entries C1-D4 are associated in the same manner with digits 406 generated during other time intervals.

Because each of the entries A1-D4 is associated with a particular range of digits 406, the properties of the digital chaos generator, as described above, allow particular ones of entries A1-D4 to be selectively decrypted. That is, if the initial value for the chaotic sequence 404 is provided or calculated from the user key and the time interval associated with the particular ones of the entries A1-D4, the associated digits 406 of the chaotic sequence 404 can be directly calculated and used to selectively decrypt the particular entries. For example, to decrypt the data corresponding to entry A3, the decryption sequence need only calculate the digits 406 corresponding to the time interval between t8 and t9, based on the initial conditions used by the encryption system. In another example, to decrypt all entries for a particular field Dx, the decryption sequence need only calculate the digits 406 corresponding to the time intervals between t3 and t4, t7 and t8, t11 and t12, and t15 and t16, based on the initial conditions used by the encryption system. Thus, decryption of particular entries would not require calculation of the entire sequence, as in most non-linear encryption algorithms, but the chaotic nature of the encryption algorithm provides sufficient security, similar to non-linear cryptosystems.

Accordingly, in the various embodiments of the invention, a cryptographic system can be configured to operate with a user key that provides the necessary information for performing a selective decryption of the encrypted database. Such a user key can be generated prior to encryption of the data and can identify which entries a user is permitted to access. In particular, the generated user key specifies the initial value for the chaotic sequence and the particular portions of the chaotic sequence associated with the particular entries the user is allowed to access. Note that the “key” may consist of multiple subsidiary keys or related algorithm keying parameters as are used to define a distinct cryptonet within the cryptosystem. Such keys can be transmitted using any available secure transmission methods or can have security features to prevent third parties from using the user key. As described previously, any key management mechanism may be used without limitation. Afterwards, during decryption, the decryption system accesses the user key to selectively decrypt the data stream by generating the one or more sequences needed to decrypt the selected portions of the database based on the information specified in the user key. The components and operation of an exemplary system operating with user keys is illustrated in FIGS. 5-7.

Referring now to FIG. 5, there is provided a block diagram of an exemplary cryptographic system 500 in accordance with the various embodiments. Notably, the cryptographic system 500 has an increased security feature as compared to conventional linear cryptographic systems. In this regard, it should be understood that the cryptographic system 500 includes a device to encrypt a data stream utilizing a chaotic sequence. In effect, reverse engineering of mathematical patterns present in an encrypted data stream generated by the cryptographic system 500 is more difficult than reverse engineering of mathematical patterns present in an encrypted data stream generated by a conventional linear cryptographic system due to the absence of cyclostationary features.

Referring again to FIG. 5, the cryptographic system 500 is comprised of a data stream source 502, a user access/identity information source 503, an encryption device 504, a user access/identity information source 505, and a decryption device 506. The data stream source 502 can be comprised of hardware and/or software configured to generate a data stream. The data stream can include payload data, such as voice data, video data, user identification data, signature data and/or the like. The data stream can also be a digital data stream. The data stream source 502 is also comprised of hardware and/or software configured to communicate the data stream to the encryption device 504.

The user access/identity information source 503 can be comprised of hardware and/or software configured to generate data representing a user's access/identity information and permissions. The user data can include any type of user authentication data, such as user code data, user key(s), user signature data, user biometric data, and/or the like. The user access data can also include user access level data, user permission data, and/or any other type of data that specifies which fields of a particular data store that the user is allowed to access. In addition, the user access information may include metadata defining which fields a user wishes to access. In the various embodiments of the invention, such access can be specified directly or indirectly according to a key management/access rules. That is, the user data can identify specific entries the user is allowed to access or the user data can identify categories or properties of entries the user is allowed to access. The generated user data can also be protected from the user in some cases, generating the user access information as used in the encryption device 504, yet without direct access or knowledge of the actual user access information by the user. The user data source 502 is also comprised of hardware and/or software configured to communicate the user data to the encryption device 504.

The encryption device 504 is comprised of hardware and/or software configured to generate an encryption sequence. The encryption sequence is a configurable chaotic sequence. Although the chaotic sequence is a sampled data sequence having a time varying value expressed in a digital form that has no discernable regularity or order, this sequence is configurable based on the combination of user access information provided by the user access/identity information source 503. The encryption device 504 is also comprised of hardware and/or software configured to perform actions to encrypt (or modify) the data stream using the encryption sequence. The encryption device 504 is further comprised of hardware and/or software configured to communicate a modified ciphertext data stream directly to the decryption device 506. However, in some embodiments, the ciphertext data stream can be stored in a database or data repository 507 for decryption and/or access by the user at a later time. The encryption device 504 will be described in greater detail below in relation to FIG. 6.

The decryption device 506 is comprised of hardware and/or software configured to generate one or more decryption sequences for selected portions of the data. The decryption sequences are generated based on the information contained in the user access information generated by the user access/identity information source 505. The description of user access/identity information source 503 is sufficient to understand the operation of user access/identity information source 505. However, it should be noted that the user access information used in the decryption of a set of data is substantially similar to that used in the decryption of the same set of data. The user access/identity information source 505 is configured to provide user access information to the decryption device 506. The decryption device 506 is configured to accept user access information from the user access/identity information source 505. The decryption sequences are configurable chaotic sequences chosen based on the corresponding encryption sequence and encryption method. The chaotic sequences are sampled data sequences having a time varying value expressed in a digital form that has no discernable regularity or order. The decryption sequences can be one or more portions of the encryption sequence generated by the encryption device 504. In some embodiments of the invention, these sequences can be generated at decryption device 506. However, the invention is not limited in this regard. In other embodiments, the decryption sequences can be stored, such as in an external data store or data repository 507. The decryption device 506 is also comprised of hardware and/or software configured to perform actions to interpreting the user access information/keys and extracting information from the user access information/keys. The decryption device 506 is further comprised of hardware and/or software configured to perform actions to decrypt the received modified data stream. The decryption device 506 is also comprised of hardware and/or software configured to communicate the partially or completely decrypted data to an external device (not shown). The decryption device 506 will be described in greater detail below in relation to FIG. 7.

In some embodiments the various components in FIG. 5 can be controlled and/or configured via one or more user access terminals 508, depending on the configuration of system 500. For example, in a system in which encryption and decryption occurs at different physical locations, user access terminals 508 can be provided at the locations of the encryption device and the decryption device. In other embodiments, one or more of the components in FIG. 5 may be incorporated into terminals 508. In still other embodiments, encryption and decryption components can be remotely located and accessed remotely via user access terminal(s) 508.

Referring now to FIG. 6, there is provided an exemplary block diagram, according to an embodiment of the invention, of the encryption device 504 of FIG. 5. As shown in FIG. 6, the encryption device 504 is comprised of a data stream receiving device (DSRD) 602, an encrypter 604, a chaotic sequence generator (CSG) 300, and a user processing device 605. The user processing device 605 can include a user data receiving device (UDRD) 606 and a user parameter generator (UPG) 608.

As shown in FIG. 6, the DSRD 602 is configured to receive an input data stream from an external device, such as the data stream source 502 (described above in relation to FIG. 5). In some embodiments, the input data stream can be received in a format that is ready to be encrypted. In other embodiments the DSRD 602 can be configured to reformat the input data stream into the format required by the encrypter 604. The DSRD 602 is also configured to communicate the input data stream to the encrypter 604.

Referring again to FIG. 6, the UDRD 606 is configured to receive user access information from an external device, such as the user access/identity information source 503 (described above in relation to FIG. 5). In some embodiments, the input data stream can be received in a format that is ready to generate the chaotic sequence parameters for a chosen encryption operation. In other embodiments, the UDRD 606 can be configured to reformat the input data stream into the format required by the UPG 608. The UDRD 606 is also configured to communicate the user access information to the UPG 608. The UPG 608 formats and performs any necessary calculations to translate the provided user access information into chaotic sequence parameters. The UPG 608 is electronically coupled to the chaotic sequence generator 300, providing all chaotic sequence generation parameters needed for synchronized generation of the encryption sequence. The UPG 608 is also configured to communicate data field location information to the encrypter 604, synchronized to the resulting digital chaotic sequence. The combination of chaotic sequence generator parameters and data field location information can be chosen to encrypt a designated set or plurality of subsets of plaintext (as described in relation to fields Dx and associated time intervals in FIG. 5) in the input data stream.

The CSG 300 is configured to receive state synchronization information, key(s), or other user access information from an external device (such as user access/identity information source 503 of FIG. 5). State synchronization information and keys are well known to those skilled in the art, and therefore will not be described in great detail herein. The CSG 300 is also configured to generate an encryption sequence. The encryption sequence is a chaotic sequence having a time varying value expressed in a digital form that has no discernable regularity or order. In this regard, it should be appreciated that the CSG 300 is comprised of a plurality of computing processors 302₀, . . . , 302_N-1and a mapping processor 304. The discussion provided above in relation to FIG. 3 is sufficient for understanding the CSG 300.

The CSG 300 is electronically coupled to the encrypter 604. The encrypter 604 is configured to generate a modified data stream by incorporating or combining the encryption sequence with the input data stream. More particularly, the encrypter 604 is configured to perform a combination method for masking one or more portions of the data stream. That is, even though the encrypter 604 can be configured to encrypt the data, as received, in its entirety, one of ordinary skill in the art will recognize that in some cases, only a partial encryption is necessary or desired. For example, it may be desired to only encrypt actual entry data. Such an embodiment can be necessary when the data stream contains both data and database structure information. In particular, the encrypter 604 is configured to receive data field location information from the UPG 608, which is used to synchronize the encryption operations of either a plurality of partial data subsets or the entirety of the data stream received by the encrypter 604 with the associated digital chaotic sequence.

The encrypter 604 can utilize any combination method, including, but not limited to, multiplication within a Galois extension field, addition modulo q, subtraction modulo q, bitwise logic operations, or any other standard combination method. In this regard, it should be appreciated that the encrypter 604 can include a multiplier, an adder, a digital logic device, a feedback mechanism or a similar combining function device. In additional embodiments of the invention, the encryption device 504 may be utilized multiple times to provide multiple levels of encryption with unique keys. The encrypter 604 is configured to provide its encrypted or modified ciphertext data stream to an external device (not shown), such as a data store (e.g. database or hard drive) or a decrypter (such as decryption device 506 discussed in relation to FIG. 5).

A person skilled in the art will appreciate that FIG. 6 only illustrates an exemplary architecture for encryption device 504 in FIG. 5. However, the invention is not limited in this regard and any other encryption device architecture can be used without limitation.

Referring now to FIG. 7, there is provided an exemplary block diagram, according to an embodiment of the invention, of the decryption device 506 of FIG. 5. The decryption device 506 is comprised of a modified data stream receiving device (MDSRD) 702, a chaotic sequence generator (CSG) 300, a decrypter 704, and a user processing device 705. The user processing device 705 can include a user data receiving device (UDRD) 706 and a user parameter generator (UPG) 708.

As shown in FIG. 7, the MDSRD 702 is comprised of hardware and/or software configured to receive a modified data stream from an external device (not shown), such as the encryption device 504 described above in relation to FIGS. 5 and 6 or an external data store (e.g. data repository 507). The MDSRD 702 is also comprised of hardware and/or software configured to communicate the modified data stream to the decrypter 704. In this regard, it should be appreciated that the MDSRD 702 is electronically connected to the decrypter 704.

The UDRD 706 is comprised of hardware and/or software configured to receive user access information from an external device (not shown), such as the encryption device 504 described above in relation to FIGS. 5 and 6. The UDRD 706 is also comprised of hardware and/or software configured to communicate this user access information to the UPG 708. The operation of the UDRD 706 and UPG 708 are substantially similar to the operation of the UDRD 606 and UPG 608 described in relation to FIG. 6, so will not be described in further detail. However, it should be understood that the combined processing of the UDRD 706 and UPG 708 results in generation of synchronized chaotic sequence parameters and data field location information for use by the chaotic sequence generator 300 and the decrypter 704. The UPG 708 is configured to communicate this chaotic sequence parameter information to the chaotic sequence generator 300 and the synchronized data field location information to the decrypter 704. In this regard, it should be appreciated that the UKPD 706 is electronically connected to the CSG 300 and the decrypter 704.

The CSG 300 is configured to receive state synchronization information or a chaotic sequence parameter set from the processed user access information. The CSG 300 is also configured to receive data field location information specified in the user key from the UPG 708. The CSG 300 in decryption device 506 is further configured to generate one or more decryption sequences based on the information within the user key. Accordingly, the CSG 300 only generates the portions of the decryption sequence associated with fields the user is allowed to decrypt. The decryption sequences are generated based on the chaotic encryption sequence and the combination method used in the encryption device 504. The decryption sequences may be chaotic sequences having a time varying value expressed in a digital form that has no discernable regularity or order, where each of the sequences is associated with a particular portion of the modified data stream. In this regard, it should be appreciated that the CSG 300 is comprised of a plurality of computing processors 302₀, . . . , 302_N-1and a mapping processor 304. The discussion provided above in relation to FIG. 3 is sufficient for understanding the CSG 300. Furthermore, the discussion of how a chaotic sequence can be generated using an initial value “x” and a time interval “T” in relation to FIG. 2 is sufficient for understanding and how only a portion of the encryption sequence can be generated based on the state information and the data field location information included in the user access information.

The UPG 708 and the CSG 300 are electronically coupled to the decrypter 704. Using the data field location information extracted from the user key by the UPG 708 and the corresponding digital chaotic decryption sequences, the decrypter 704 is configured to decrypt at least a portion of the modified input data stream by performing a decryption method in which the data field decryption sequences are applied to the portions of the modified data stream to be decrypted. Decryption methods are well known to persons skilled in the art, and therefore will not be described in great detail herein. One of ordinary skill in the art will recognize that in some cases, only a partial decryption is necessary or desired. For example, it may be desired to only decrypt actual entry data. Such an embodiment can be necessary when the data stream contains both data and database structure information. In particular, the decrypter 704 is configured to receive data field location information from the UPG 708, which is used to synchronize the decryption operations of either a plurality of partial data subsets or the entirety of the data stream received by the decrypter 704 with the associated digital chaotic sequence.

A person skilled in the art will appreciate that FIG. 7 only illustrates an exemplary architecture for decryption device 506 in FIG. 5. However, the invention is not limited in this regard and any other decryption device architecture can be used without limitation.

Referring now to FIG. 8, there is provided a flow diagram of an exemplary method 800 for encrypting and decrypting data, according to an embodiment of the invention. As shown in FIG. 8, the method 800 begins with step 802 and continues with step 804. In some embodiments, the method 800 can be prompted by a user request for information. In other embodiments, the method 800 can be prompted by the owner of the data wishing to send updated versions of a database to users. In step 804, an input data representing a database can be received by the encryption system. In the various embodiments, the data can be received in any form, as previous described with regards to FIG. 6. Subsequently, or in combination with step 804, user data can be received in step 806. As previously described, the user data can include not only user access rights data, but can also include any type of user identification or authentication data. The input data can then be encrypted in steps 808 and 810. First, in step 808, an initial value is used to generate the digit sequence to be used for encrypting the received data. That is, as described in reference to FIG. 2, the initial value “x” is selected and a sequence of digits is generated. Second, in step 810, the sequence generated in step 808 is combined, as previously described, with the input data to produce modified ciphertext data.

Subsequently, or in combination with step 810, method 800 proceeds by assembling at least one user access parameter in step 812. In the various embodiments, the user access parameters are translated into the initial value “x” used for generating the chaotic sequence with user data and data field location information associated with the chaotic sequence, as previously described with respect to FIGS. 5 and 6. However, as previously described, not all data field location information for the modified input database is included into the user access information. Rather, only data field location information for those fields that the user is allowed to access is included in the user access information. In some embodiments, as previously described, additional security features can be added to the user access information to prevent access by unapproved users. The modified data can then be transmitted to a user system in step 814. One of ordinary skill in the art will recognize that a single chaotic sequence can be used to generate user access information for any number of users with differing levels of access. In some embodiments, the user access information is also transmitted at step 814. This information can be transmitted separately to reduce the risk of a security breach.

After the modified data (and the user access information) is transmitted to the user system in step 814, the user decryption system can access the modified data and the user access information in step 816. In some embodiments, the receipt of data can trigger an automatic decryption of the received data. However, in other embodiments, the user decryption system can be configured to await user instructions before proceeding. In such embodiments, the modified data is transmitted to a storage device, such as data repository 507 in FIG. 5. The modified data therefore remains encrypted until the user decryption system receives a command requiring decryption of the modified data. For example, the system can await a command from a user access terminal to access, modify, or retrieve one or more portions of the modified data. Once the modified data and the user access information have been received in step 816, the initial value for creating the decryption sequence and the data field location information can be extracted from the user access information in step 818.

Once the information in the user key has been extracted, the digits of the portions of the chaotic sequence needed for decryption can be generated in step 820. That is, the data field location information is used to identify the portion of the modified input data to be decrypted and the portion of the encryption sequence used to encrypt particular portions of the modified ciphertext data, as previously described. The sequences for these portions can be generated, based on the initial value “x” stored in the user access information and using the data field location information to specify the time interval values “T”, as described in reference to FIG. 2. These sequences can then be used in step 822, along with the data field location information to decrypt one or more selected portions of the modified input data. After step 822, method 800 proceeds to step 824, where method 800 ends.

In light of the foregoing description of the invention, it should be recognized that the invention can be realized in hardware, software, or a combination of hardware and software. A method of generating a chaotic sequence according to the invention can be realized in a centralized fashion in one processing system, or in a distributed fashion where different elements are spread across several interconnected processing systems. Any kind of computer system, or other apparatus adapted for carrying out the methods described herein, is suited. A typical combination of hardware and software could be a general purpose computer processor, with a computer program that, when being loaded and executed, controls the computer processor such that it carries out the methods described herein. Of course, an application specific integrated circuit (ASIC), and/or a field programmable gate array (FPGA) could also be used to achieve a similar result.

The invention can also be embedded in a computer program product, which comprises all the features enabling the implementation of the methods described herein, and which, when loaded in a computer system, is able to carry out these methods. Computer program or application in the present context means any expression, in any language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function either directly or after either or both of the following a) conversion to another language, code or notation; b) reproduction in a different material form. Additionally, the description above is intended by way of example only and is not intended to limit the invention in any way, except as set forth in the following claims.

All of the apparatus, methods and algorithms disclosed and claimed herein can be made and executed without undue experimentation in light of the present disclosure. While the invention has been described in terms of preferred embodiments, it will be apparent to those of skill in the art that variations may be applied to the apparatus, methods and sequence of steps of the method without departing from the concept, spirit and scope of the invention. More specifically, it will be apparent that certain components may be added to, combined with, or substituted for the components described herein while the same or similar results would be achieved. All such similar substitutes and modifications apparent to those skilled in the art are deemed to be within the spirit, scope and concept of the invention as defined.

HIGH-SPEED CRYPTOGRAPHIC SYSTEM USING CHAOTIC SEQUENCES

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