Patent Application
20160275905
The present disclosure relates generally to electronic devices and, more particularly, to reducing artifacts of high-bandwidth display interfaces of the electronic devices.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Organic light-emitting diode (OLED) displays and Liquid crystal displays (LCDs) are commonly used as screens or displays for a wide variety of electronic devices, including consumer electronics such as televisions, computers, and handheld devices (e.g., cellular telephones, audio and video players, gaming systems, and so forth). Such devices typically provide a flat display in a relatively thin package that is suitable for use in a variety of electronic goods.
Typically, LCD panels include an array of pixels for displaying images. Image data related to each pixel may be sent by a processor to the LCD panel through a driver integrated circuit (IC). The driver IC then processes the image data and transmits corresponding voltage signals to the individual pixels. As the resolution of these LCDs increase, an increased amount of data may be transferred from the processor to the LCD panel. Unfortunately, increasing data transfer bandwidth may be costly and/or result in display artifacts.
A summary of certain embodiments disclosed herein is set forth below. It should be understood that these aspects are presented merely to provide the reader with a brief summary of these certain embodiments and that these aspects are not intended to limit the scope of this disclosure. Indeed, this disclosure may encompass a variety of aspects that may not be set forth below.
Embodiments of the present disclosure relate to devices and methods for reducing artifacts and/or costs of a high bandwidth display. By way of example, a method for reducing artifacts and/or costs of a high bandwidth display may include receiving an indication of a refresh rate of content to be displayed on the electronic device. Compression artifacts may be more observable in low-speed content than high-speed content. Accordingly, in some embodiments, based upon the refresh rate indication, the content may be selectively compressed. For example, low-speed content (e.g., 60 Hz or less) may be transferred for processing without compression, while higher-speed content (e.g., greater than 60 Hz, 120 Hz, etc.) may be compressed and then transferred for processing. In some embodiments, a number of transmission lanes and/or transmission pipelines may be activated, based upon the refresh rate indication. For example, more transmission pipelines and/or transmissions lanes may be activated for higher-speed content than low-speed content.
Various refinements of the features noted above may be made in relation to various aspects of the present disclosure. Further features may also be incorporated in these various aspects as well. These refinements and additional features may exist individually or in any combination. For instance, various features discussed below in relation to one or more of the illustrated embodiments may be incorporated into any of the above-described aspects of the present disclosure alone or in any combination. The brief summary presented above is intended only to familiarize the reader with certain aspects and contexts of embodiments of the present disclosure without limitation to the claimed subject matter.
Various aspects of this disclosure may be better understood upon reading the following detailed description and upon reference to the drawings in which:
One or more specific embodiments of the present disclosure will be described below. These described embodiments are only examples of the presently disclosed techniques. Additionally, in an effort to provide a concise description of these embodiments, all features of an actual implementation may not be described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.
When introducing elements of various embodiments of the present disclosure, the articles “a,” “an,” and “the” are intended to mean that there are one or more of the elements. The terms “comprising,” “including,” and “having” are intended to be inclusive and mean that there may be additional elements other than the listed elements. Additionally, it should be understood that references to “one embodiment” or “an embodiment” of the present disclosure are not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the recited features.
With the foregoing in mind, a general description of suitable electronic devices that may employ touch-sensitive displays having capabilities to operate in a reduced power mode will be provided below. In particular,
Turning first to
By way of example, the electronic device 10 may represent a block diagram of the notebook computer depicted in
In the electronic device 10 of
The display 18 may be a touch-screen (e.g., touch-sensitive) liquid crystal display (LCD), for example, which may allow users to interact with a user interface of the electronic device 10. In some embodiments, the electronic display 18 may be a MultiTouch™ display that can detect multiple touches concurrently. For example, the display 18 may be a capacitive-touch-sensitive display capable of detecting projected capacitive touch (PCT) touch input gestures, such as a single touch, a double touch, a drag, a flick, a pinch, a rotate, a zoom, or combinations thereof. As will be described further detail, to reduce implementation costs (e.g., power savings) and/or reduce display 18 artifacts, the dynamic bandwidth control circuitry 21 may be used to control various aspects relating to content transmission to the display 18 based upon a refresh rate of the content.
The input structures 22 of the electronic device 10 may enable a user to interact with the electronic device 10 (e.g., pressing a button to increase or decrease a volume level). The I/O interface 24 may enable electronic device 10 to interface with various other electronic devices, as may the network interfaces 26. The network interfaces 26 may include, for example, interfaces for a personal area network (PAN), such as a Bluetooth network, for a local area network (LAN), such as an 802.11x Wi-Fi network, and/or for a wide area network (WAN), such as a 3G or 4G cellular network. The power source 28 of the electronic device 10 may be any suitable source of power, such as a rechargeable lithium polymer (Li-poly) battery and/or an alternating current (AC) power converter.
The electronic device 10 may take the form of a computer or other type of electronic device. Such computers may include computers that are generally portable (such as laptop, notebook, and tablet computers) as well as computers that are generally used in one place (such as conventional desktop computers, workstations and/or servers). In certain embodiments, the electronic device 10 in the form of a computer may be a model of a MacBook®, MacBook® Pro, MacBook Air®, iMac®, Mac® mini, or Mac Pro® available from Apple Inc. By way of example, the electronic device 10, taking the form of a notebook computer 30A, is illustrated in
The handheld device 30B may include an enclosure 36 to protect interior components from physical damage and to shield them from electromagnetic interference. The enclosure 36 may surround the display 18, which may display indicator icons 38. The indicator icons 38 may indicate, among other things, a cellular signal strength, Bluetooth connection, and/or battery life. The I/O interfaces 24 may open through the enclosure 36 and may include, for example, a proprietary I/O port from Apple Inc. to connect to external devices.
User input structures 40, 42, 44, and 46, in combination with the display 18, may allow a user to control the handheld device 30B. For example, the input structure 40 may activate or deactivate the handheld device 30B, the input structure 42 may navigate a user interface to a home screen, a user-configurable application screen, and/or activate a voice-recognition feature of the handheld device 30B, the input structures 44 may provide volume control, and the input structure 46 may toggle between vibrate and ring modes. A microphone 48 may obtain a user's voice for various voice-related features, and a speaker 47 may enable audio playback and/or certain phone capabilities. A headphone input 49 may provide a connection to external speakers and/or headphones. As also noted above, to reduce artifacts and costs of high refresh rate content, the electronic device 10 (e.g., the display 18, the display interface 21, and/or the processor 12) may be equipped with the dynamic bandwidth control circuitry 21, and thereby may be used to control various aspects of content transmission to the display 18 based upon a refresh rate of the content.
The transmitter component 52 may be communicatively coupled to the processor 12 and to the receiver component 54, and the receiver component 54 may be communicatively coupled to a timing controller 56 (TCON) of the display 18 and the transmitter component 52. The timing controller 56 may control the timing of when pixels, light emitting diodes (LEDs), or other display components in the display 18 may operate. As such, the timing controller 56 may receive image data or video data that may have originated at the processor 12, such that the image data or video data may indicate how the display components should operate.
In certain embodiments, the image data or video data may be routed to the timing controller 56 from the processor 12 via the interface 20. The image data or video data may be routed according to, for example, an Embedded DisplayPort (eDP) standard. However, it should be noted that the image data or video data may be routed to the timing controller 56 from the processor 12 using any other suitable display protocol.
When transmitting video data 58, the processor 12 may transmit video data 58 via a number of alternating current (AC) coupled differential pair cables (e.g., 4 micro-coaxial cables) to the transmitter component 42. In one embodiment, the video data 58 may include image data or video data that corresponds to the images or video to be depicted on the display 18. As such, the processor 12 may send the video data 58 via high-bandwidth communication mediums (e.g., four differential pair cables) that operate at, for example, 1.62 Gbps, 2.7 Gbps, 5.4 Gbps, or the like to ensure that the video data 58 is received by the transmitter component 42 in a timely manner. In one embodiment, the communication of the video data 58 to the transmitter component 52 may be unidirectional or transmitted from the processor 12 to the display 18, but not vice-versa.
In addition to the video data 58, the processor 12 may also send auxiliary data 60 to the transmitter component 52. The auxiliary data 60 may include sideband data that may be used for link training protocols, hand shaking protocols, control signals, clock signals, and the like. Generally, the auxiliary data 60 may originate from the processor 12 or the timing controller 56. As such, the auxiliary data 60 may be transmitted via a bi-directional communication medium (e.g., single bi-directional differential pair) to facilitate communication between the processor 12 and the timing controller 56, and vice-versa. In certain embodiments, the auxiliary data 60 may include a significantly smaller amount of data as compared to the video data 58 and thus may be communicated via an AC-coupled lower-bandwidth communication medium that operates at, for example, 1 Mbps or the like.
At some point during the transmission of the data 58 and/60 from the processor 12 to the timing controller 56 (and/or source driver 84 of
Once the modifications are made to the pixel pipelines and/or data 58 and/or 60, the data 58 and/or 60 may be transmitted to the receiver component 54 (e.g., in a compressed format and/or via particularly selected and/or activated pixel pipelines, depending on the modifications made by the pixel pipeline selection circuitry 68 and/or the compression selection circuitry 70).
The receiver component 54 may, in turn, receive the transmitted data 58 and/or 60. If the data 58 and/or 60 was compressed by the dynamic bandwidth control circuitry 21 (e.g., the compression selection circuitry 70), then the receiver component 54 (or another component of the display 18 and/or interface 20 may decompress the compressed data, such that the decompressed data corresponds to the video data 58 and/or the auxiliary data 60 provided by the processor 12. The receiver component 54 may then transmit the video data 58 and/or the auxiliary data 60 to the timing controller 56, which may be used to control the operation of the display 18 to display images or video embedded within the video signal 58.
The timing controller 56 may also communicate with the processor 12 via the interface 20 in a similar manner as described above. That is, the timing controller 56 may transmit auxiliary data 60 and a Hot Plug Detection (HPD) signal 64 to the receiver component 54, which may be used to forward the auxiliary data 60 and the HPD signal 64 to the processor 12. The HPD signal 64 may provide an indication to the processor 12 that the display 18 is present and communicatively coupled to the processor 12. As such, the HPD signal 64 may be a uni-directional signal that may be transmitted from the timing controller 56 to the processor 12, but not vice-versa. In certain embodiments, the HPD signal 64 may pulse and provide an interrupt to the timing controller 56.
After receiving the auxiliary data 60 and the HPD signal 64 from the timing controller 56, the receiver component 54 may send the auxiliary data 60 and the HPD signal 64 to the transmitter component 52. The transmitter component 52 may receive the auxiliary data 60 and the HPD signal 64 provided by the timing controller 56. The transmitter component 52 may then transmit the auxiliary data 60 and the HPD signal 64 to the processor 12, thereby facilitating the communication between the timing controller 56 and the processor 12.
As illustrated, the processors 12 may include a power management unit (PMU) 86 and a system on chip (SOC) 88. The PMU 86 may be used to manage the power of the electronic device 10, and may control when power is supplied to, and removed from, other components of the electronic device 10. For example, the PMU 86 may supply power 87 to the display 18. Specifically, the PMU 86 may supply power 87 to both the display subsystem 80 and the touch subsystem 82.
As illustrated, the SOC 88 provides image data 90 to the display 18. Furthermore, the SOC 88 provides a synchronization signal 92 (e.g., VSYNC) to the display 18 to cause the display 18 to refresh image data stored in pixels of the display 18. As may be appreciated, one or more of the image data 90, the synchronization signal 92, and the mode signal 94 may be provided from the SOC 88 to the display 18 via the interface 20 (e.g., a communication link (e.g., via a mobile industry processor interface (MIPI))).
As will be discussed in more detail below, the electronic device 10 may include dynamic bandwidth control circuitry 21. The dynamic bandwidth control circuitry 21 may be used to modify attributes (e.g., a selection of and/or activation) of the pixel pipelines used for transmission of image data 90 to the display subsystem 80 and/or modify attributes of the image data 90 itself to provide more efficient transmission of the image data 90. Thus, increased cost efficiencies and/or reduced image artifacts may be achieved. The dynamic bandwidth control circuitry 21 may be communicatively coupled to the SOC 88 and/or the source driver 84 to enable dynamic bandwidth allocation of data transmission between these components. Further, all and/or portions of the dynamic bandwidth control circuitry 21 may be part of the interface 20, the source driver 84, and/or a processor 12 (e.g., the SOC 88).
Turning now to a more detailed circuit view of the electronic display 18,
In the presently illustrated embodiment, each unit pixel 102 includes a thin film transistor (TFT) 108 for switching a data signal supplied to a respective pixel electrode 110. The potential stored on the pixel electrode 110 relative to a potential of a common electrode 112, which may be shared by other pixels 102, may generate an electrical field sufficient to alter the arrangement of a liquid crystal layer of the display 18. In the depicted embodiment of
When activated, a TFT 108 may store the image signals (e.g., image data signal 90) received via the respective source line 106 as a charge upon its corresponding pixel electrode 110. As noted above, the image signals stored by the pixel electrode 110 may be used to generate an electrical field between the respective pixel electrode 110 and a common electrode 112. This electrical field may align the liquid crystal molecules within the liquid crystal layer to modulate light transmission through the pixel 102. Thus, as the electrical field changes, the amount of light passing through the pixel 102 may increase or decrease. In general, light may pass through the unit pixel 102 at an intensity corresponding to the applied voltage from the source line 106.
As discussed with regard to
As discussed herein, the dynamic bandwidth control circuitry 21 may be useful to dynamically alter a selection of pixel pipelines used to supply pixel data to the source driver 120 or data supplied to a timing controller. Additionally or alternatively, the dynamic bandwidth control circuitry may be used to dynamically compress high-bandwidth content (e.g., content that has a refresh rate of over 60 Hz). Thus, using the dynamic bandwidth control circuitry 21, content may be served with multiple content refresh rates, while reducing artifacts and/or power consumption.
In certain embodiments, the dynamic bandwidth control circuitry 21 may store instructions in a storage device 130. The instructions may be used to control aspects of the image data 90 and/or pixel transmission pipeline activations between the processor 12 and the source driver 120. Such instructions may be based on a received indication of the image data 90 refresh rate, as described herein. As may be appreciated, the storage device 130 may be any suitable article of manufacture having a tangible, computer-readable media for storing instructions for the dynamic bandwidth control circuitry 21. For example, the storage device 130 may be an EEPROM device.
The source driver 120 also may couple to a gate driver integrated circuit (IC) 124 that may activate or deactivate rows of unit pixels 102 via the gate lines 104. As such, the source driver 120 may provide timing signals 126 to the gate driver 124 to facilitate the activation/deactivation of individual rows (i.e., lines) of pixels 102. In other embodiments, timing information may be provided to the gate driver 124 in some other manner. The display 18 may include a Vcom source 128 to provide a Vcom output to the common electrodes 112. In some embodiments, the Vcom source 128 may supply a different Vcom to different common electrodes 112 at different times. In other embodiments, the common electrodes 112 all may be maintained at the same potential (e.g., a ground potential) while the display 18 may be on.
As illustrated in
Further, the number of lanes 156 may be interpolated based upon one or more thresholds, the number of lanes 156 within a pipeline 154, etc. For example, the number of lanes 156 within the pipelines may be reduced when less than full pipeline 158 bandwidth in needed. For example, in the embodiment of
Once the number of pipelines 154 and/or lanes 156 are determined, the proper number of pipelines 154 and/or lanes 156 are activated (e.g., by interconnection/rerouting in the fabric 152) (block 186). From there the data is presented to the display panel 164, via the proper pipelines 154 and/or proper lanes 156 (block 188). The process 180 may begin again and continue until there is no more data to be displayed at the display 18.
Using the above process 180 and circuitry 68, a more granular decision may be made regarding the number of pipelines 154 and/or lanes 156 to use for particular refresh rates. This may result in increased efficiencies, such as power-consumption efficiencies, etc.
Referring back to the 120 Hz content rendering example in
In contrast, if the same number of pipelines were active for the processing of lower-speed content (e.g., 60 Hz content), the frame would be extended using a larger vertical blanking window, as illustrated in painting 194. For example, the vertical blanking period of the painting 194 may replace the 120 Hz active frame region of the second 8 milliseconds of each 16 milliseconds of painting 192.
In embodiments where an additional pipeline is activated for painting 192 high-speed content (e.g., 120 Hz content), but not painting 196 lower-speed content (e.g., 60 Hz content) the active frame region may be extended, painting at a 60 Hz active frame region rate. This results in a relatively small vertical blanking period and an extended active frame region timing as compared to painting 194 using the 120 Hz active frame region timing.
Another way to dynamically control bandwidth allocation is to compress data. For example, lossy compression, color-subsampling, reduced color-depth ranges, etc. may be used to reduce an amount of data that is transferred between the SOC 88 and the timing controller 56 and/or source driver 84.
Starting first with
The source display engine 202 may also actuate a switch 208 at the end of the compression and non-compression pathways. When the refresh rate indicates that compression is to be used, the switch 208 may be actuated to receive data from the compression pathway (e.g., compressed data from the compression circuitry 206). Further, when the refresh rate indicates that compression is not to be implemented, the source display engine 202 may actuate the switch to receive data from the non-compression pathway (e.g., un-compressed image data).
The data may then be received from the proper pathway, and provided to the display interface 20 (e.g., a low-power display port (LPDP) interface). Because the higher-speed content (e.g., 120 Hz content) is now compressed, the interface 20 may support lower-refresh rate transmission (e.g., 60 Hz).
Discussing now the process 230 using a 120 Hz compression threshold example, 120 Hz content may be written to the frame buffer 200. The 120 Hz refresh rate may be obtained (e.g., by a frame buffer read operation) (block 232). The refresh rate information is used to determine if the refresh rate is high enough for compression (decision block 234). For example, if the source display engine 202 is set to compress data that has a refresh rate of 120 Hz or higher, the threshold is met for compressing the data. Thus, the data is compressed (e.g., by setting the switches 204 and 208 to activate the compression pathway containing compression circuitry 206 (block 236). Once the compression is complete or if the refresh rate does not warrant compression (e.g., does not reach the compression refresh rate threshold), the data is provided for further processing (e.g., provided to the interface 20) for further transmission.
For example, as illustrated in
If the content was compressed, the content is decompressed (block 256). As discussed above, this may occur, in some embodiments, by actuating a switch to route the content to decompression circuity. Once decompression is complete or no previous compression occurred, the content is provided to the timing controller 56 and/or source driver 84 (block 288).
Though the current embodiment bases compression and/or decompression on refresh rate information, in some embodiments, other information (e.g., flags, etc.) may be used to control the switches. Accordingly, in some embodiments, the refresh rate of the content does not need to be observed at portion 70A of
By using the dynamic compression described herein, increased bandwidth may be provided for faster content, while retaining the same data transmission rate. For example,
As illustrated in row 304, for faster content, the interface 20 link rate is equal to the link rate in row 302. As mentioned above, the link rate is the number of lanes times the throughput of each of the lanes. Accordingly, similar to row 302, the link rate is 4×1.62 Gbps. However, in contrast to the slower content, which is uncompressed, the faster content may be compressed. Accordingly, the content may be rendered by the panel 164 faster (e.g., two 120 Hz frames may be compressed into 16.7 milliseconds). Thus, roughly double the amount of frames may be rendered in a substantially similar amount of time.
The specific embodiments described above have been shown by way of example, and it should be understood that these embodiments may be susceptible to various modifications and alternative forms. It should be further understood that the claims are not intended to be limited to the particular forms disclosed, but rather to cover all modifications, equivalents, and alternatives falling within the spirit and scope of this disclosure.
