Claims
- 1. A delta-sigma digital-to-analog converter having a digital input and an analog output comprising:a storage means having stored outputs of a delta-sigma converter fed by a number of predetermined interpolated samples of a delta-sigma converter corresponding to all possible values of said digital input, said storage means coupled to receive said digital input, a plurality of digital-to-analog converters coupled to said storage means to receive said stored outputs, said plurality of digital-to-analog converters clocked by multi-phase clocks wherein each phase applied to each of said plurality of digital to analog converters is delayed with respect to a next one by an oversampling period equal to the Nyquist period divided by the number of predetermined interpolated samples; and a summer coupled to said plurality of digital-to-analog converters for summing all output from said plurality of digital-to-analog converters to generate said analog output.
- 2. The delta-sigma digital-to-analog converter of claim 1 wherein said storage means is a read/write programmable memory.
- 3. The delta-sigma digital-to-analog converter of claim 1 wherein said storage means is a read only memory.
- 4. A delta-sigma digital-to-analog converter having a digital input and an analog output comprising:a storage means having stored compressed outputs of a delta-sigma converter fed by a number of predetermined interpolated samples of a delta-sigma converter corresponding to all possible values of said digital input, said storage means coupled to receive said digital input; an expansion unit coupled to said storage means for expanding said compressed outputs; a plurality of digital-to-analog converters coupled to said expansion unit to receive said expanded stored outputs, said plurality of digital-to-analog converters clocked by multi-phase clocks wherein each phase applied to each of said plurality of digital to analog converters is delayed with respect to a next one by an oversampling period equal to the Nyquist period divided by the number of predetermined interpolated samples; and a summer coupled to said plurality of digital-to-analog converters for summing all output from said plurality of digital-to-analog converters to generate said analog output.
- 5. A method for converting a digital signal to an analog signal comprising the steps of:generating sigma-delta digital output patterns for all possible digital inputs; storing said output patterns in a table of a storage means; addressing said storage means by a digital input signal; retrieving corresponding sequence pattern stored in said table of said storage means; applying said output pattern to a plurality of digital-to-analog converters; shifting each of said plurality of digital-to-analog converters by multi-phase clocks wherein each phase is delayed with respect to a next digital-to-analog converter by the oversampling period, equal to the Nyquist period divided by the number of predetermined interpolated samples; and summing the outputs of the plurality of digital-to-analog converters.
- 6. A method for converting a digital signal to an analog signal comprising the steps of:generating sigma-delta digital output patterns for all possible digital inputs; storing said output patterns in a table of a storage means; addressing said storage means by a digital input signal; retrieving corresponding sequence pattern stored in said table of said storage means; applying said output pattern to a plurality of digital-to-analog converters; shifting each of said plurality of digital-to-analog converters by multi-phase clocks wherein each phase is delayed with respect to a next digital-to-analog converter by the oversampling period equal to the Nyquist period divided by the number of predetermined interpolated samples; subtracting the output of said plurality of digital-to-analog converters from a delayed version of the sampled digital input signal to form an error signal the amount of delay being substantially the same as the delay through the filter; determining a number of taps and tap weight coefficients of said plurality of digital-to-analog converters to reduce the error signal; adjusting the number of taps and the tap weight coefficients of said plurality of digital-to-analog converters; and summing the outputs of said adjusted outputs of said plurality of digital-to-analog converters.
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of provisional application No. 60/169,819 filed Dec. 8, 1999.
This invention applies to the cellular base station having high-speed, high resolution digital-to-analog converter from our copending application (TI-29961), Ser. No. 09/725,665, filed Nov. 29, 2000. This application is incorporated by reference herein.
US Referenced Citations (12)
Non-Patent Literature Citations (1)
Entry |
A Second-Order Double-Sampled Delta-Sigma Modulator Using Individual-Level Averaging; Chuc K. Thanh et al., 1997 IEEE Journal of Solid-State Circuits, vol. 32, No. 8, Aug. 1997, pp. 1269-1273. |
Provisional Applications (1)
|
Number |
Date |
Country |
|
60/169819 |
Dec 1999 |
US |