Patent Application
20060050731
1. Field of the Invention
This invention relates generally to IEEE 1394 communications systems and, more specifically, to a High-speed IEEE 1394 Link Interface.
2. Description of Related Art
A key technology for digital traffic, and in particular, high-speed communications with remote devices such as digital TV's, external hard drives, printers and other devices is the IEEE 1394 multimedia bus. Also known as “firewire” in the United States, this bus and associated protocol was developed to be “plug and play” and to efficiently handle the movement of data while connected systems are busy with other tasks or applications.
In defining the IEEE 1394 protocol, one must first understand the environment that is defined by the protocol; this can be best understood by consideration of
While the IEEE 1394 standard does include expansion into ultra-high-speed communications, it is currently only commercially viable in two modes: 1394A or 1394B. 1394A is for a 400 MBS data transfer rate and 1394B is for an 800 NBS serial bus speed (between the Phy and Link layers). The pertinent portions of the operation of these two protocols is discussed in connection with
Prior Art Operational Sequence
Generally, when the Phy is powered up and RSTB is released, the LLC is activated with the LKON signal and PCLK begins toggling. The Link then configures the Phy for operation by programming the Phy's internal registers. Finally, standard register settings such as Contender may be set as needed. After configuration, the LLC resets the Phy and the Phy begins operation with the new parameters. When a cable is connected, the Phy automatically detects the format and speed of the remote device and activates the port. The Phy then notifies the Link of bus activity, and the Link may request the bus for data transmission.
Serial bus activity begins with a discovery protocol. Discovery protocol is biased towards producing Beta Mode (8B/10B) connections over Legacy Mode (Data/Strobe) connections. The discovery protocol begins by sending bursts of tones over the serial cable, while at the same time listening for tones from a remote device. When tones are detected from the remote device, the two devices trade speed capability information and negotiate an operating speed for the connection. After the devices agree on an operating speed, both devices start transmitting symbols at this speed.
If no tones are detected for a period of time, the Phy will check for the existence of TpBias or connect_detect, indicating that the other device is operating in Legacy Mode. If TpBias or connect_detect is detected, the Phy will wait another period of time and try toning again in case the remote device is capable of Beta Mode operation. If toning is now detected, the above speed negotiation occurs. Otherwise, the connection is started in Legacy Mode with both devices transmitting IDLE.
If no tones are detected and both TpBias and connect_detect are false, the Phy will set its own TpBias to try to wake up the remote device that is listening for Legacy Mode devices. If TpBias is now detected, the Phy will again try toning in case the remote device is capable of Beta Mode operation. If toning is detected, the above speed negotiation occurs. Otherwise, the connection is started in Legacy Mode with both devices transmitting IDLE. If TpBias is not detected from the remote device after the local Phy has generated TpBias, then the discovery procedure begins again with toning and will continue looping through toning, bias/connect detection, and bias generation until a connection is established.
If a Beta Mode connection has been established, both devices begin transmitting training symbols to synchronize clock-and-data recovery circuits, data scramblers, and 8B/10B running sums. After all circuits have been synchronized, the devices begin a loop-test procedure intended to prevent loops in the bus architecture. Before a port on a device is activated, a check is run to see if activation would result in a loop. If so, the port is disabled so that correct bus operation can begin. Otherwise, the devices are ready to begin with a Bus Reset. If a Legacy Mode connection has been established, Bus Reset begins immediately.
Bus Reset symbols are transmitted continuously for a period of time long enough for all connected devices to be able to detect it, no matter what state they may be in. When the Bus Reset period is complete, the devices begin Tree Identification, where the hierarchy of the serial bus is established. Each device notifies its connected peers that they are its “parents”, or higher-level nodes in the tree. Each port on a device that receives a notification that it is a parent sends its respective peer port a notification that it is a “child”, or lower-level node. This is considered a handshake, and it indicates that the tree identification between these two devices is complete. If two devices simultaneously notify each other that they are parents, then they will back off a period of time to resolve the conflict. After all ports on all devices have gone through the handshake procedure, then tree identification for the bus is complete and one device is left with all active ports identified as children. This device is referred to as the root node. All devices then begin the self-identification phase of startup, where they transmit information about themselves and are assigned a physical address on the bus. Before transmitting this information, each device requests permission to transmit, and these requests are passed to the parent port and towards the root node. The root node chooses a request from its children and grants that node permission to transmit. If the node that receives the grant has children that are requesting the bus, then the grant is passed on to them. This continues until a leaf node (a node with only one connection, to its parent), receives a grant, at which time it sends packets containing its identification information. This information is repeated up and down the bus such that every device sees all packets that are transmitted. After the transmitting node ends its transmission, it transitions into an IDLE state, where it is no longer requesting the bus and is simply waiting to receive packets and for the self-identification phase to complete. The parent of a node that completes its self identification transmit sequence then grants any other child port that is requesting the bus. After all of its children have completed their self identification sequence, then that device is able to transmit its own sequence, followed by a transition into IDLE. This pattern is repeated by every device until all devices have sent their self-identification information, with the last device being the root node. All devices are now in the IDLE state and ready to receive or transmit normal packets on the bus.
Before a device may transmit onto the bus, it must first arbitrate for control of the bus. Control of the arbitration of the bus differs between clouds of Legacy Mode devices and Beta Mode devices, but both have the concept of two separate intervals, the Isochronous Interval and the Asynchronous Interval. Packets to be transmitted are classified as either Isochronous or Asynchronous depending on the type of data that is carried, and these packets are only allowed during their respective intervals. Isochronous packets are given priority over Asynchronous packets, as their data is time-bounded. All requests to transmit isochronous data are honored before any requests to transmit asynchronous data. After all isochronous requests are completed, asynchronous requests are serviced until the start of the next isochronous interval begins. The beginning of the isochronous interval is called the Cycle Start, and occurs every 150 ms.
Beta Mode devices use the new BOSS arbitration, where the node that is currently transmitting on the serial bus determines which of its child nodes (or its own link) has the best outstanding request, and then grants that node after it is done its own transmission. If none of its child nodes have valid requests for the current interval, then it passes the grant on to its parent port, which in turn checks the requests of its child ports. This continues until the final node to receive the grant is the root node, which can then determine a grant to give to any node. Nodes that are not the current BOSS pass requests from their children (as well as their own link) up to the parent and towards the root, so that the root always has visibility to the best requests on the bus.
Legacy Mode devices do not use BOSS arbitration. Instead, these devices always pass requests to their parents and toward the root node. The root node always decides which of its child ports should be granted.
When new devices are introduced into an existing bus, a reset is initiated on that bus and all nodes begin the Bus Reset->Tree ID->Self ID startup sequence again. This allows the bus architecture to develop again, and potentially a new root node to be chosen.
Active devices that are not being used may enter one of several inactive states to save power: Disabled state, in which the devices to not maintain any connectivity to each other and must begin the discovery procedure to become active again; Suspended state, where devices maintain connectivity but not physical bus information, and therefore must go through Bus Reset->Tree ID->Self ID; and Standby State, available only to Beta Mode devices, where devices maintain both connectivity and physical bus information, and may be returned to active states with minimal bus interruption.
Turning to
If the BMODE_LINK is set to high 108, when the Phy is powered up 110, and after the Link programs the Phy's internal registers 112, a B or Beta Phy-Link Interface will be enabled (EEE 1394B) 114. The pertinent characteristics of the 1394B Phy-Link Interface is that the Clock speed is 100 MHz, the Data transfer rate is 800 Megabits per second, and the Control Signal Transfer speed is also 100 MHz.
Until the advent of the present invention, then, there was no way of exceeding a Phy-Link Interface data transfer rate of 800 MBS using widely-used IEEE 1394B architecture.
In light of the aforementioned problems associated with the prior devices and methods, it is an object of the present invention to provide a High-speed IEEE 1394 Link Interface. The interface device and method should be compatible with legacy IEEE 1394 devices. The device should replace a conventional 1394 physical layer interface device and should cooperatively operate with a slightly modified link layer controller. The device should further be selectively activatable and deactivatable. When activated, the device should double the clock speed, and therefore permit data transfer rates of 1600 Megabits per second, with Control Signal transfer speeds of 200 MHz.
The objects and features of the present invention, which are believed to be novel, are set forth with particularity in the appended claims. The present invention, both as to its organization and manner of operation, together with further objects and advantages, may best be understood by reference to the following description, taken in connection with the accompanying drawings, of which:
The following description is provided to enable any person skilled in the art to make and use the invention and sets forth the best modes contemplated by the inventor of carrying out his invention. Various modifications, however, will remain readily apparent to those skilled in the art, since the generic principles of the present invention have been defined herein specifically to provide a High-speed IEEE 1394 Link Interface.
The present invention can best be understood by initial consideration of
The second difference is that the conventional Link device is replaced with (or reconfigured to be) an FBE Link Layer Controller 28. The FBE Link Layer Controller 28 is a Fast Beta Mode enabled, such that in addition to the conventional attributes specified by the IEE1394A/B protocols, it can also activate the A/B/FB Phy Device 26 to operate in Fast Beta Mode (and then can manage the increased data transfer rate). The result of this increased data transfer rate, of course, is to reduce the bottleneck effect that can occur when numerous data transmissions are occurring simultaneously over the Phy-Link Interface.
Turning now to
The method 30, like the conventional Beta mode, requires that the BMODE_LINK is set to “high.” 108. When the Fast-Beta Phy is powered up 116, and the Fast-Beta-Enabled Link programs the FB Phy's internal registers 118, the initial Phy-Link Interface is enabled in Beta Mode 120, and having the parameters: clock speed of 100 MHz, Data transfer rate of 800 MBS, and Control Signal transfer speed also of 100 MHz.
What is different in this method 30, is that a Fast Beta Bit, which is a part of one of the FB Phy's internal registers, is identified to both the FB Phy and the FBE Link. The FB Phy monitors the status of this bit constantly during normal operation. If the FBE Link sets the FB bit 122, then the Phy-Link Interface will be disabled for a predetermined period of time equal to the sum of T(LPS_DISABLE) and T(RESTORE) 126. The disable period is implemented to prevent data and speed mismatch and other incompatibilities when shifting data transmission speeds.
Upon expiration of the disable period, the Fast Beta Phy-Link Interface is enabled 128. The operational parameters of this interface are that: Clock Speed is 200 MHz, Data Transfer Rate is 1600 MBS, and Control Signal Transfer speed is 200 MHz. As discussed above, this is 2× the transfer rate of a conventional IEEE 1394B Phy-Link Interface.
While in the Fast Beta mode, the FB Phy continues to monitor the FB bit 130. If the FBE Link unsets the FB bit 130, the FB Phy-Link interface will again be disabled for a predetermined period of time equal to the sum of T(LPS_DISABLE) and T(RESTORE) 132.
Upon expiration of the disable period, the conventional Beta Phy-Link Interface will be enabled 120 (actually re-enabled), until such time as the device is powered down or the FB bit is set again 122.
Link Interface
The link interface provides a means of connecting an LLC to the Phy for control, access to the serial bus, and access to the Phy's internal registers. The link interface consists of the signals D[7:0], CTL[1:0], PCLK, LCLK, LREQ, PINT, LPS, LKON, BMODE_LINK, and DIRECT. Three modes of link interface operation are supported by the SW3161/SW3168: the IEEE 1394A-2000 standard Legacy Link Interface, the IEEE 1394B-2002 standard Beta Link Interface, and the Inventor's high performance Fast Beta Link Interface. The link interface type is chosen by tying external pins and with internal programmable registers. The choice of which interface to use depends on the type of LLC that is connected to the Phy. Note that the type of LLC that is connected will not necessarily dictate the format or speed of serial bus transceiver actions, i.e. a Phy with a Legacy LLC can still operate in Beta Mode on the serial bus, and a Phy with a 100 MHz Beta Link Interface can still connect to other devices at S1600 speeds.
Link Interface Signals
For S1600 data transferred over the 200 MHz PHY-Link interface, one byte is transferred on each cycle of PClk/LClk, exactly like S800 data over the 100 MHz interface. For speeds below S1600 on the 200 MHz interface, the timing of data (and control) is exactly the same as for the 100 MHz case, meaning that the time that the data is on the control lines does not change, although the number of PClk/LClk cycles that occur while the data is on the lines will double. The same is also true for the Ctl signals. For example, S800 data passed over the 200 MHz bus will look like S400 data passed over the 100 MHz bus, i.e. data is available on the data bus for two cycles of PClk/LClk.
Data Transfer
Data transfer in Fast Beta Mode is exactly the same as with the 100 MHz Beta Mode. However, during the grant cycle the Speed Type of the grant is modified to support S1600 as follows.
Requests
Requests in Fast Beta Mode are handled exactly the same as with the 100 MHz Beta Mode. However, the speed encoding field on the LREQ serial interface is modified to support S1600 as follows.
Status
Status Transfers in Fast Beta Mode are handled exactly the same as with the 100 MHz Beta Mode, but at twice the speed.
200 MHz Link Interface Timing
Diagram 6.1 illustrates the timing for all PHY-Link interface signals operating at the 200 MHz speed, using the same nomenclature found in the IEEE 1394B specification. Because of the higher speed of the interface, higher performance drivers are required to meet the more stringent timing requirements. It is recommended that devices utilizing the 200 MHz mode take great care in the layout of the PCB to minimize distance between the PHY and link devices, resulting in lower capacitive loading and shorter propagation delay. Applications that require significant physical distance between the PHY and link devices (greater than 10 cm) should not use the 200 MHz mode. Additionally, isolation barriers, such as those suggested by the standard, must not be used, as they will affect the timing margins negatively.
As per the 1394B specification, AC measurements are taken from the 1.575 V level of PClk/LClk to the D, Ctl, or LReq levels, and assume an output load of 10 pF.
*no isolation barrier is allowed for 200 MHZ interface operation
As compared to the 100 MHz spec, the most significant changes above are the duty cycle of PClk/LClk and the rise/fall times. The turn-around time, tPL, through the link is kept as long as possible to accommodate standard IC pad specifications. The signal propagation times are lowered to imply shorter physical distances between the PHY and link.
Transfer waveform timing is described by diagrams 6.2 and 6.3 below, with timing parameters specified in table 6.1.
The delay times tpd1, tpd2, and tpd3 are significantly shortened to accommodate the higher speed PClk/LClk. Setup time tsu is thereby decreased, and care must be taken with PCB design and IC layout to insure that skew is kept to a minimum.
Registers
The register map for the SW3161/SW3168 Physical Layer IC is divided into six parts, the Common registers, Port 0 registers, Port 1 registers, Port 2 registers, Vendor specific registers, and Vendor ID registers. These registers are specified by and compliant with the register map defined in IEEE 1394B-2002. The Vendor Specific registers are unique to the SW3161/SW3168 devices.
The register map is accessed by the LLC through the use of the LREQ signal and over the serial bus by the Remote Access packet (and by the Phy Configuration packet). Each port has its own register map. To access an individual port register map, the port is first selected by writing to the Port_select field of the Common register map. Addresses 8-15 then correspond to the addresses for the selected port, and may be read or written normally. To access the Vendor Specific registers, a value of 1 must be written to the Page Select register in the Common Registers. Addresses 8-15 will then correspond to the Vendor Specific registers for read and write. Similarly, writing a 7 to the Page Select register will select the Vendor ID registers for Addresses 8-15.
Common
The Common registers control settings and status for the Phy independent of each port and select the Page and Port used for addresses 8-15.
Operation
Operation of the SW3161/SW3168 begins with powering the 3.3V supply with the active-low reset signal RSTB low. All bidirectional Phy-link interface signals should be high-impedance, and LCLK should be low. The device will then start up its internal 1.8V regulator, which will settle within 1 ms. At this point the Phy is ready for operation, and RSTB can be set high. The Phy will startup its internal PLL, and, depending on the Power Class setting (pins PC[0:2]), it will activate the Phy-link interface by toggling signal LINKON. The LLC should respond by setting signal LPS high (or toggling if the interface is differentiated). If the Power Class is set such that the Phy does not activate the Phy-link interface, the LLC may now enable the interface itself by setting LPS high. After this handshake is complete, the Phy will begin toggling PCLK. If BMODE_LINK is high, signifying that the Phy-link interface should operate in Beta Mode, then PCLK will toggle at 100 MHz and the LLC should send a buffered version of PCLK back on the signal LCLK. If BMODE_LINK is low then the Phy-link interface will operate in Legacy Mode, PCLK will toggle at 50 MHz, and the LLC should hold LCLK low. The Phy will then begin a series of steps to clear the Phy-link interface signal lines and then hand over the control of the interface to the LLC. The LLC must also take steps to clear the signal lines before handing the interface back over to the Phy. This procedure of clearing the signal lines is described in the Link Interface section of this document. At this point the Phy has been initialized, the Phy-link interface is operational, and the LLC may set the Phy configuration for specific applications.
Configuration is done by setting internal Phy registers to their desired value. These registers affect the device as a whole (node level), or on a port-by-port basis. These registers and their effects are described in the Registers section of this document. In order to maintain correct operation, the LLC must issue a soft device reset (by writing to the soft reset register bit) after changing configuration parameters that affect port operation, such as setting the maximum port speed, enabling CAT-5 operation, or setting the Listen Only parameter. Performing a soft device reset has the same effect as bringing RSTB low, except that the Phy-link interface and the internal writeable registers are not reset. In general, it is recommended that the LLC use the following sequence to configure the Phy: program the per-port registers (including vendor specific registers), soft reset, program the node level (device level) registers. The LLC may reset the entire device in exactly the same way as the RSTB signal works by writing to the hard reset register, however this will immediately disable the Phy-link interface and reset all of the configuration parameters. The soft reset and hard reset registers are self-clearing, so they will always read back zero, and it is not necessary to ever write them to zero.
If the LLC is operating in Beta Mode and it wishes to use Fast Beta Mode, it must write a one to the LINK—200 MHZ register and then disable the Phy-link interface. Then the interface is re-enabled, it will operate in Fast Beta Mode. This procedure is described in the Link Interface section of this document.
Individual ports may be disabled with the hard disable register. These ports will not maintain any connectivity with existing connections, and will not attempt to discover any new connections. If a port is not attached to a cable connector in a particular application, this bit should always be set by the LLC to minimize current drain. To disable the entire Phy, the LLC may set the RSTB signal low or set the REG_ENB signal high. If the RSTB signal is used, the internal voltage regulator, as well as the internal voltage reference circuits, will be enabled and ready for immediate operation (the internal PLL will not be running, however). If the REG_ENB signal is used to disable the device, then the regulator, all internal references, and all other circuits will be completely powered down for minimum current drain.
Those skilled in the art will appreciate that various adaptations and modifications of the just-described preferred embodiment can be configured without departing from the scope and spirit of the invention. Therefore, it is to be understood that, within the scope of the appended claims, the invention may be practiced other than as specifically described herein.
This invention claims priority from, and is filed within one year of, Provisional Application Ser. No. 60/608,207, filed Sep. 9, 2004.
| Number | Date | Country | |
|---|---|---|---|
| 60608207 | Sep 2004 | US |
