High speed linear variable gain amplifier architecture

Description

FIELD OF THE INVENTION

This invention relates to amplifiers and in particular, amplifiers having variable gain, large bandwidth and low distortion.

BACKGROUND OF THE INVENTION

Amplifiers are used to manipulate various signals within a circuit. The topology of the amplifier affects various operating aspects of the operating amplifier. For example, some amplifiers can deliver a high output current to a load. Other amplifiers can produce an output voltage swing that is approximately equal to the magnitude of the power supply of the amplifier circuit. Some amplifiers must provide an output with low cross-over distortion whereas other amplifiers are required to maintain gain and stability at high frequencies. These different requirements place constraints upon the design of the amplifier. It is often desirable in an amplifier circuit to have variable gain, large bandwidth and low distortion. Conventional solutions use attenuators as front ends followed by high gain, closed-loop amplifiers or multiple lower gain closed-loop amplifiers. Disadvantageously, these conventional solutions require much higher FT (factor of ten) amplification to achieve these results.

SUMMARY OF THE INVENTION

The present invention achieves technical advantages as a variable gain amplifier with wide bandwidth and low distortion by using two stages, a quad input stage with emitter degeneration and translinear current amplifier second stage.

The first stage quad configuration allows a constant DC output level. The output current of the quad is then fed into a resistance shunt current feedback amplifier with Darlington/level shift input stage to reduce transistor beta loading effects as well as allowing the largest dynamics out of the stage when a current to voltage and common mode feedback circuit are implemented in the same stage.

The second stage presents a low input impedance to the quad allowing optimization of the quad with minimize loss of bandwidth.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1

is a schematic circuit diagram of the present invention;

FIG. 2

is a schematic of a conventional npn current feedback topology;

FIG. 3

is a a simplified equivalent circuit shown in

FIG. 2

; and

FIG. 4

is a schematic circuit diagram of the translinear loop (Q

109

to Q

112

) of the second stage of the present invention.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

The amplifier of the present invention, shown at

10

in

FIG. 1

, is a combination of a quad

12

current drive circuit and a translinear current amplifier

14

. The quad

12

provides a constant DC output level. As used herein, quad refers to a series-parallel configuration of four transistors. The quad is modified with emitter degeneration. The output drive current of the quad

12

is fed into the translinear current amplifier

14

comprising a resistive shunt current feedback amplifier with Darlington/level shift input stage. This arrangement reduces transistor beta loading effects as well as allowing the largest dynamics out of the stage when a current to voltage and common mode feedback circuit are implemented in the same stage. Translinear loop transistors

109

(“Q

109

”),

110

(“Q

110

”),

111

(“Q

111

”) and

112

(“Q

112

”) ensure a fast conveyence of the collector currents of Q

109

(“Q

C109

”) and Q

112

(“Q

C112

”) to the output. The current gain of the second stage is given as follows:

(

IA

out1

−IA

out2

)/(

I

out1

−I

out2

)=(1+

R

123

/R

124

)·(

I

135

/I

134

)·(

A

/(1+

A

))

where A=g

mQ109

·R

124

The second stage

14

presents a low input impedance to the quad

12

allowing optimization of the quad

12

with minimum loss of bandwidth. Current to voltage conversion and common mode feedback implemented in the second stage

12

allows least delay, best distortion and highest bandwidth with such an architecture. The inherent all npn core variable gain amplifier

10

ensures the best possible bandwidth and flexibility of use on both all npn or complementary bipolar processes.

The equations below better illustrate the operation of the second stage.

FIG. 2

depicts a schematic of a conventional npn current feedback topology. From

FIG. 3

, we can derive the transfer function of FIG.

2

.

FIG. 3

is the equivalent circuit of FIG.

2

.

\frac{I_{Q109}}{I_{in}}

1. \frac{V_{i n} - V_{out}}{R_{123}} = I_{i n} -> V_{i n} = V_{out} + I_{i n} \cdot R_{123};

2. \frac{V_{out}}{R_{124}} + I_{Q109} + \frac{V_{out} - V_{i n}}{R_{123}} = 0;

I_{Q109} = g_{mQ109} \cdot V_{i n}

3. V_{i n} = \frac{I_{Q109}}{g_{mQ109}} .

Substituting equation (3) for equations (2) and (1) results in:

4. \frac{I_{Q109}}{g_{mQ109}} = V_{out} + I_{i n} R_{123} -> V_{out} = \frac{- I_{Q109}}{g_{mQ109}} - I_{i n} \cdot R_{123}

5. \frac{V_{out}}{R_{124}} + I_{Q109} + \frac{V_{out} - \frac{I_{Q109}}{g_{mQ109}}}{R_{123}} = 0

Substituting equation (4) for (5) and solving for

\frac{I_{Q109}}{I_{i n}}

provides as follows:

\begin{matrix} \frac{I_{Q109}}{I_{i n}} = \frac{g_{mQ109} (R_{123} + R_{124})}{1 + g_{mQ109} \cdot R_{124}} \\ = \frac{(g_{mQ109} \cdot R_{124})}{1 + g_{mQ109} \cdot R_{124}} \frac{(R_{123} + R_{124})}{R_{124}} \\ \frac{I_{Q109}}{I_{i n}} = \frac{A}{1 + A} (1 + \frac{R_{123}}{R_{124}}) where A = g_{mQ109} \cdot R_{124} \end{matrix}

Referencing

FIG. 4

, we can derive the transfer function for the translinear loop:

6. V_{be108} - V_{be112} + V_{be111} - V_{be110} = 0

V_{Tin} (\frac{I_{Q109}}{I_{s}}) - V_{Tin} (\frac{I_{Q112}}{I_{s}}) + V_{Tin} (\frac{I_{Q111}}{I_{s}}) - V_{Tin} (\frac{I_{Q110}}{I_{s}}) = 0

\frac{I_{Q109}}{I_{Q112}} \cdot \frac{I_{Q111}}{I_{Q110}} -> I_{Q109} \cdot I_{Q111} = I_{Q110} \cdot I_{Q112}

I

Q109

+I

Q112

=I

134

→I

Q112

=I

134

−I

Q109

7.

I

Q110

+I

Q111

=I

135

→I

Q111

=I

135

−I

Q110

8.

Substituting equation (7) and (8) for (6):

I

Q109

(

I

135

−I

Q110

)=

I

Q110

(

I

134

−I

Q109

)

(

I

Q109

·I

135

)−(

I

Q109

·I

Q110

)=(

I

Q110

I

134

)−(

I

Q109

·I

Q110

)

I

Q109

·I

135

=I

Q110

·I

134

\frac{I_{Q110}}{I_{Q109}} = \frac{I_{135}}{I_{134}}

By combining the derivation of the transfer functions of

FIGS. 3 and 4

, we obtain:

I_{Q110} = I_{out} -> \frac{I_{out}}{I_{Q109}} = \frac{I_{135}}{I_{Q134}};

Then \frac{I_{out}}{I_{i n}} = \frac{I_{out}}{I_{Q109}} \cdot \frac{I_{Q109}}{I_{i n}};

\frac{I_{out}}{I_{Q109}} \cdot \frac{I_{Q109}}{I_{i n}} = \frac{I_{135}}{I_{134}} \cdot \frac{T}{1 + T} (1 + \frac{R_{123}}{R_{124}});

Therefore : \frac{I_{out}}{I_{i n}} = (1 + \frac{R_{123}}{R_{124}}) (\frac{R_{135}}{R_{134}}) (\frac{A}{1 + A})

where A = g_{m} \cdot I_{Q109} \cdot R_{124}

Claims

1. An amplifier circuit, comprising:a first stage and a second stage, the first stage comprising a quad configuration and the second stage comprising a translinear current amplifier configuration; and a coupling circuit operably coupling the first stage and the second stage, wherein the current gain of the second stage is given by: (IAout1−IAout2)/(Iout1−Iout2)=(1+R123/R124)·(I135/I134)·(A/(1+A)) where A=gm Q109·R124; IAout1 is the amplified output collector current from Q110; IAout2 is the output collector current from transistor Q111; Iout1 is the output current from Q103 and Q105 from the first stage quad, and Iout2 is the collector current from Q104 and Q106 from the first stage quad; R123 is the resistance value of the third resistor and R124 is the resistance value of the fourth resistor; I135 is the current through the fifth current source; and I134 is the value of the current through the fourth current source.
2. The amplifier circuit recited in claim 1, wherein the first stage quad configuration is modified using emitter degeneration.
3. The amplifier circuit recited in claim 1, further comprising current to voltage conversion and common mode feedback in the second stage operable to provide high speed, low distortion and extended bandwidth.
4. The amplifier circuit recited in claim 1, wherein the amplifier is formed of bipolar devices.
5. The amplifier circuit recited in claim 1 being adapted for use in an integrated circuit.
6. The amplifier circuit recited in claim 1 being adapted for use in a variable gain amplifier.

US Referenced Citations (2)

Number	Name	Date	Kind
5901350	Stoichita et al.	May 1999	A
5907261	Jones	May 1999	A

High speed linear variable gain amplifier architecture

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CPC

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Abstract

Description

Claims

US Referenced Citations (2)