Claims
- 1. In a programmable logic device (PLD), a logic cell having a plurality of inputs and an output, comprising:
- a programmable logic circuit having a plurality of inputs coupled to the plurality of logic cell inputs, and an output;
- a logic gate, having a first input coupled to the output of the programmable logic circuit, a second programmable input coupled to an output of another logic cell and a third programmable input coupled directly to an input/output terminal of the PLD, the logic gate programmably producing a logical combination of its inputs at an output; and
- an output control circuit having an input coupled to the output of the logic gate and an output coupled to the output of the logic cell,
- wherein, set up time is significantly reduced by programming the third programmable input of the logic gate to receive an input signal directly from the input/output terminal of the PLD.
- 2. The logic cell of claim 1, wherein the programmable logic circuit is a four-input look-up table programmably generating any logic function of its inputs at an output.
- 3. The logic cell of claim 1, wherein the logic gate is a three-input NAND gate with each input coupled to a programmable element.
- 4. The logic cell of claim 1, wherein the output control circuit comprises a clocked register coupled to a selection circuit.
- 5. A logic cell for use in a programmable logic device (PLD) comprising:
- a first and a second programmable look-up table each having a plurality of inputs and an output;
- a first logic gate having a first input coupled to the output of the first programmable look-up table, a second programmable input coupled to the output of the second look-up table, and a third programmable input coupled to an output of another logic cell;
- a second logic gate having a first programmable input coupled to the first look-up table output, a second programmable input coupled the output of another logic cell and a third programmable input coupled to an input/output terminal of the PLD;
- a first register having an input coupled to the output of the first logic gate; and
- a second register having an input coupled to the output of the second logic gate,
- wherein set up time is significantly reduced by programming the programmable inputs of the first and second logic gates to receive an input signal directly from the input/output terminal of the PLD.
- 6. The logic cell of claim 5 further comprising a selection circuit having four inputs coupled respectively to the output of the first logic gate, to an output of the first register, to the output of the second logic gate, and to an output of the second register, the selection circuit for coupling two of its four inputs to a first and a second logic cell output, respectively.
- 7. The logic cell of claim 6 wherein each one of the first and the second registers is a flip-flop.
- 8. The logic cell of claim 5 wherein each one of the first and second logic gates is a NAND gate.
- 9. A logic cell for use in a programmable logic device (PLD) comprising:
- a first programmable look-up table having four inputs and an output;
- a second programmable look-up table having four input and an output;
- a first three-input NAND gate having a first input coupled to the first look-up table output, a second programmable input coupled to the second look-up table output, a third programmable input coupled to an output of another logic cell, and an output;
- a second three-input NAND gate having a first programmable input coupled to the first look-up table output, a second programmable input coupled the output of another logic cell, a third programmable input coupled directly to an input/output terminal of the PLD, and an output;
- a first register for receiving the output of the first NAND gate;
- a second register for receiving the output of the second NAND gate; and
- a selection circuit, having four inputs coupled respectively to the output of the first NAND gate, to an output of the first register, to the output of the second NAND gate, and to an output of the second register, the selection means for coupling two of its four inputs to a first and a second macrocell output, respectively.
Parent Case Info
This is a Continuation of application Ser. No. 08/086,420 filed Jul. 2, 1993 now U.S. Pat. No. 5,399,922.
US Referenced Citations (20)
Non-Patent Literature Citations (1)
Entry |
"Optimized Reconfigurabe Cell Array (ORCA) Series Field-Programmable Gate Arrays," AT&T Microelectronics Advance Data Sheet, Feb., 1993 (pp. 1-32). |
Continuations (1)
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Number |
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86420 |
Jul 1993 |
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