Claims
- 1. A parallel-prefix modulo 2n−1 adder,
- 2. The adder set forth in claim 1 wherein:
the prefix structure determines each of the carry value terms according to the associative relation (G*i,P*i)=(gi,pi)o(gi−1,pi−1)o . . . o(g0,p0)o(g−1,pn−1)o . . . o(gi+1,pi+1), where o is the logical operator and c*i=G*i.
- 3. The adder set forth in claim 2 wherein the prefix structure comprises:
a plurality of stages, a stage j having n logical operators o, 1≦j≦log2(n), each logical operator oi at bit position i, 0≦i≦n−1 in the stage j receiving a pair of inputs [gin—1(i,j−1),pin—1(i, j−1)], [gin—2(k,j−1),pin—2(k, j−1)], i≠k and k=(n−2(j−1)+i)% z, where % is the modulo arithmetic operator, and outputting a carry generate term gout(i,j) and a carry propagate term pout(i,j).
- 4. The adder set forth in claim 3 wherein the prefix stricture further comprises:
a pipeline register that receives outputs from a stage j−1 and provides inputs to a stage j.
- 5. The adder set forth in claim 4 wherein:
there is a plurality of the pipeline registers, with a stage of the prefix structure being preceded by a pipeline register and followed by another pipeline register.
- 6. The adder set forth in claim 3 wherein:
the number of stages in the plurality is log2 n.
- 7. The adder set forth in claim 3 wherein:
the adder has an operand input receiving stage with n, operators u; each operator ui produces a pair (gi,pi) of the carry generate and carry propagate inputs and an output hi from inputs ai and bi according to the relation gi=ai·bi, and pi defined either as pi=hi=ai⊕bi or pi=ai+bi.
- 8. The adder set forth in any of claims 1 through 3 wherein:
the adder has an operand input receiving stage and a result producing stage in addition to the prefix structure and does not require an additional stage to handle a carry input received from the prefix structure.
- 9. The adder set forth in any of claims 1 through 7 wherein:
all of the logical operators in the prefix structure perform the same logical operation.
- 10. The adder set forth in claim 9 wherein:
when inputs (gin—1, pin—1), (gin—2, pin—2) are applied to the logical operators in the prefix structure, they produce the output pair (gout,pout) according to the relations gout(gin—1+pin—1·gin—2) and pout=(pin—1·gin—2).
- 11. The adder set forth in any of claims 1 through 6 wherein:
the adder has an operand input receiving stage and a result producing stage made up of logical operators in addition to the prefix structure; and none of the logical operators in the adder has a fan-out of more than two.
- 12. The adder set forth in any of claims 1 through 6 wherein:
the adder has an operand input receiving stage and a result producing stage in addition to the prefix structure and the result producing stage outputs the result 0 either when both operands received in the input receiving stage are all 1's or when the operands received in the input receiving stage are complementary.
- 13. The adder set forth in any one of claims 1 through 3 wherein:
the adder has an operand input receiving stage with n operators u, each operator ui producing a pair (gi,pi) of the carry generate and carry propagate inputs and an output hi from inputs ai and bi.
- 14. The adder set forth in claim 13 wherein:
the adder has a result producing stage with n operators w; and each operator wi produces an si according to the relationship si=hi⊕K′⊕c*i−1 for 0≦i≦n−1 where K=h1·h2· . . . ·hn−1, and K′ is the complement of K and where hi=pi=ai⊕bi
- 15. The adder set forth in claim 3 wherein:
the adder has an operand input receiving stage with n operators u, and a result producing stage with n operators w; each operator ui produces a pair (gi,pi) of the carry generate and carry propagate inputs and an output hi from inputs ai and bi according to the relation gi=ai·bi, hi=ai⊕bi; and pi is defined as either pi=hi=ai⊕bi or pi=ai+bi; and each operator wi produces an si according to the relation si=hi⊕c*i−1 for i≠0 and s0=h0⊕c*n−1 for i=0.
- 16. A device that includes a modulo 2n−1 adder,
- 17. A modulo 2n−1 adder comprising:
a set of u0 . . . n−1 first logical operators, a first operator ui, 0≦i≦n−1, receiving bit ai of a first operand a0 . . . n−1 and a bit bi of a second operand b0 . . . n−1 and producing therefrom a carry generate value gi, a carry propagate value ci, and an intermediate value hi; a prefix structure that receives g0 . . . (n−1) carry generate terms and p0 . . . (n−1) carry propagate terms from the set of first logical operators and determines each of the carry value terms c*(−1 . . . (n−2)) from all of the g0 . . . (n−1) carry generate terms and p0 . . . (n−1) carry propagate terms; and a set of w0 . . . n−1 second logical operators, a second logical operator wi receiving c*(i−1) from the prefix structure and hi from ui and producing a sum si therefrom.
- 18. The adder set forth in claim 17 wherein:
the prefix structure determines each of the carry value terms according to the associative relation (G*i,P*i)=(gi,pi)o(gi−1,pi−1)o . . . o(g0,p0)o(gn−1,pn−1)o . . . o(gi+1,pi+1), where o is the logical operator and c*i=G*i.
- 19. The adder set forth in claim 18 wherein the prefix structure comprises:
a plurality of stages, a stage j having n logical operators o, 1≦j≦log2(n), each logical operator oi at bit position i, 0≦i≦n−1 in the stage j receiving a pair of inputs [gin—1(i,j−1),pin—1(i,j−1)], [gin—2(k,i−1),pin—2(k,j−1)], i≠k and k=(n−2(j−1)+i)% n, where % is the modulo arithmetic operator, and outputting a carry generate term gout(i,j) and a carry propagate term pout(i,j).
- 20. The adder set forth in claim 19 wherein the prefix structure further comprises:
a pipeline register that receives outputs from a stage j−1 and provides inputs to a stage j.
- 21. The adder set forth in claim 20 wherein:
there is a plurality of the pipeline registers, with a stage of the prefix structure being preceded by a pipeline register and followed by another pipeline register.
- 22. The adder set forth in claim 19 wherein:
the number of stages in the plurality is log2 n.
- 23. The adder set forth in claim 19 wherein:
each operator ui produces the pair (gi,pi) of the carry generate and carry propagate values and the intermediate value hi from the inputs ai and bi according to the relation gi=ai·bi, and pi defined either as pi=hi=ai⊕bi or pi=ai+bi.
- 24. The adder set forth in any of claims 17 through 23 wherein;
the adder does not require an additional stage to handle a carry input received from the prefix structure.
- 25. The adder set forth in any of claims 17 through 23 wherein:
all of the logical operators in the prefix structure perform the same logical operation.
- 26. The adder set forth in claim 25 wherein:
when inputs (gin—1, pin—1), (gin—2, pin—2) are applied to the logical operators in the prefix structure, they produce the output pair (gout,pout) according to the relations gout=(gin—1+pin—1·gin—2) and pout=(pin—1·gin—2).
- 27. The adder set forth in any of claims 17 through 23 wherein:
none of the logical operators in the adder has a fan-out of more than two.
- 28. The adder set forth in any of claims 17 through 23 wherein:
the adder outputs the result 0 either when both operands received in the input receiving stage are all 1's or when the operands received in the input receiving stage are complementary.
- 29. The adder set forth in any one of claims 17 through 23 wherein:
each operator wi produces an si according to the relationship si=hi⊕K′⊕c*i−1 for 0≦i≦n−1 where K=h1·h2· . . . ·hn−1 and K′ is the complement of K and where hi=pi=ai⊕bi.
- 30. The adder set forth in claim 19 wherein:
each operator ui produces a pair (gi,pi) of the carry generate and carry propagate values and an intermediate value hi from inputs as and bi according to the relation gi=ai·bi, hi=ai⊕bi; and pi is defined as either pi=hi=ai⊕bi or pi=ai+bi; and each operator wi produces an si according to the relation si=hi⊕c*i−1 for i≠0 and s0=h0⊕c*n−1 for i=0.
CROSS REFERENCES TO RELATED APPLICATIONS
[0001] The present patent application claims priority from U.S. provisional patent application 60/219,856, L. Kalampoukas, et al., High-speed parallel prefix modulo 2n−1 adders, filed Jul. 21, 2000.
PCT Information
Filing Document |
Filing Date |
Country |
Kind |
PCT/US01/22247 |
7/16/2001 |
WO |
|