Claims
- 1. A computer system, said system comprising:
a central processing unit connected to a host bus; a random access memory connected to a system memory bus; a peripheral component interconnect (PCI) bus, said PCI bus operating on a sequential series of clock cycles, said PCI bus capable of implementing registered PCI bus arbitration rules and bus width rules according to a registered PCI protocol; a core logic chip set connected to said host bus, to said PCI bus, and to said system memory bus; said core logic chip set configured as a first interface bridge between said host bus and said system memory bus, a second interface bridge between said host bus and said PCI bus, and a third interface bridge between said system memory bus and said PCI bus; and a registered PCI device connected to said PCI bus, said registered PCI device having a status register and a control register, said registered PCI device operating according to said registered PCI protocol, said registered PCI device capable of issuing a first command on a first clock cycle of said PCI bus according to said registered PCI protocol and a second command on a second clock cycle of said PCI bus according to said registered PCI protocol, said second command being an extended command to said first command, said registered PCI device further capable of issuing an attribute during said second clock cycle.
- 2. The computer system of claim 1, wherein said first command is issued on a C/BE[3:0]# portion of said PCI bus.
- 3. The computer system of claim 2, wherein when signals on said C/BE[3:0]# portion of said PCI bus are equivalent to 0000, then said first command is an Interrupt Acknowledge command.
- 4. The computer system of claim 2, wherein when signals on said C/BE[3:0]# portion of said PCI bus are equivalent to 0001, then said first command is a Special Cycles command.
- 5. The computer system of claim 2, wherein when signals on said C/BE[3:0]# portion of said PCI bus are equivalent to 0010, then said first command is an I/O Read command.
- 6. The computer system of claim 2, wherein when signals on said C/BE[3:0]# portion of said PCI bus are equivalent to 0011, then said first command is an I/O Write command.
- 7. The computer system of claim 2, wherein when signals on said C/BE[3:0]# portion of said PCI bus are equivalent to 0100, then said first command is Reserved.
- 8. The computer system of claim 2, wherein when signals on said C/BE[3:0]# portion of said PCI bus are equivalent to 0101, then said first command is a Reserved.
- 9. The computer system of claim 2, wherein when signals on said C/BE[3:0]# portion of said PCI bus are equivalent to 0110, then said first command is a Memory Read command.
- 10. The computer system of claim 2, wherein when signals on said C/BE[3:0]# portion of said PCI bus are equivalent to 0111, then said first command is a Memory Write command.
- 11. The computer system of claim 2, wherein when signals on said C/BE[3:0]# portion of said PCI bus are equivalent to 1000, then said first command is Reserved.
- 12. The computer system of claim 2, wherein when signals on said C/BE[3:0]# portion of said PCI bus are equivalent to 1101, then said first command is Reserved.
- 13. The computer system of claim 2, wherein when signals on said C/BE[3:0]# portion of said PCI bus are equivalent to 1010, then said first command is a Configuration Read command.
- 14. The computer system of claim 2, wherein when signals on said C/BE[3:0]# portion of said PCI bus are equivalent to 1011, then said first command is a Configuration Write command.
- 15. The computer system of claim 2, wherein when signals on said C/BE[3:0]# portion of said PCI bus are equivalent to 1100, then said first command is an alias to a Memory Read command.
- 16. The computer system of claim 2, wherein when signals on said C/BE[3:0]# portion of said PCI bus are equivalent to 1101, then said first command is a Dual Address Cycle command.
- 17. The computer system of claim 2, wherein when signals on said C/BE[3:0]# portion of said PCI bus are equivalent to 1110, then said first command is Reserved.
- 18. The computer system of claim 2, wherein when signals on said C/BE[3:0]# portion of said PCI bus are equivalent to 1111, then said first command is an alias to a Memory Write command.
- 19. The computer system of claim 1, wherein said first command is issued on a C/BE[7:4]# portion of said PCI bus.
- 20. The computer system of claim 1, wherein said second command is issued on a C/BE[3:0]# portion of said PCI bus.
- 21. The computer system of claim 20, wherein when signals on said C/BE[3:0]# portion of said PCI bus are equivalent to 0000, then said second command is a Reserved command, said second command being of transaction type Byte-enable and of extended command type validated.
- 22. The computer system of claim 20, wherein when signals on said C/BE[3:0]# portion of said PCI bus are equivalent to 0001, then said second command is a Reserved command, said second command being of transaction type Byte-enable and of extended command type validated.
- 23. The computer system of claim 20, wherein when signals on said C/BE[3:0]# portion of said PCI bus are equivalent to 0010, then said second command is a Reserved command, said second command being of transaction type Byte-enable and of extended command type validated.
- 24. The computer system of claim 20, wherein when signals on said C/BE[3:0]# portion of said PCI bus are equivalent to 0011, then said second command is a Split Completion Exception Message command, said second command being of transaction type Byte-enable and of extended command type validated.
- 25. The computer system of claim 20, wherein when signals on said C/BE[3:0]# portion of said PCI bus are equivalent to 0100, then said second command is a Reserved command, said second command being of transaction type Byte-enable and of extended command type immediate.
- 26. The computer system of claim 20, wherein when signals on said C/BE[3:0]# portion of said PCI bus are equivalent to 0101, then said second command is a Reserved command, said second command being of transaction type Byte-enable and of extended command type immediate.
- 27. The computer system of claim 20, wherein when signals on said C/BE[3:0]# portion of said PCI bus are equivalent to 0110, then said second command is a Reserved command, said second command being of transaction type Byte-enable and of extended command type immediate.
- 28. The computer system of claim 20, wherein when signals on said C/BE[3:0]# portion of said PCI bus are equivalent to 0111, then said second command is a Standard Byte-Enable Extended command, said second command being of transaction type Byte-enable and of extended command type immediate.
- 29. The computer system of claim 20, wherein when signals on said C/BE[3:0]# portion of said PCI bus are equivalent to 1000, then said second command is a Reserved command, said second command being of transaction type byte count and of extended command type validated.
- 30. The computer system of claim 20, wherein when signals on said C/BE[3:0]# portion of said PCI bus are equivalent to 1001, then said second command is a Reserved command, said second command being of transaction type byte count and of extended command type validated.
- 31. The computer system of claim 20, wherein when signals on said C/BE[3:0]# portion of said PCI bus are equivalent to 1010, then said second command is a Reserved command, said second command being of transaction type byte count and of extended command type validated.
- 32. The computer system of claim 20, wherein when signals on said C/BE[3:0]# portion of said PCI bus are equivalent to 1011, then said second command is a Split Completion command, said second command being of transaction type byte count and of extended command type validated.
- 33. The computer system of claim 20, wherein when signals on said C/BE[3:0]# portion of said PCI bus are equivalent to 1100, then said second command is an alias to a Reserved command, said second command being of transaction type Byte count and of extended command type immediate.
- 34. The computer system of claim 20, wherein when signals on said C/BE[3:0]# portion of said PCI bus are equivalent to 1101, then said second command is a Reserved command, said second command being of transaction type byte count and of extended command type immediate.
- 35. The computer system of claim 20, wherein when signals on said C/BE[3:0]# portion of said PCI bus are equivalent to 1110, then said second command is a Reserved command, said second command being of transaction type byte count and of extended command type immediate.
- 36. The computer system of claim 20, wherein when signals on said C/BE[3:0]# portion of said PCI bus are equivalent to 1111, then said second command is an alias to a Standard Byte-Count Extended command, said second command being of transaction type byte count and of extended command type immediate.
- 37. The computer system of claim 1, wherein said attribute is issued on an AD portion of said PCI bus, said AD portion of said PCI bus capable of issuing 64 signals.
- 38. The computer system of claim 37, wherein an initial sequence request attribute phase signal is issued on AD[0].
- 39. The computer system of claim 37, wherein a disconnect on first ADB attribute phase signal is issued on AD[1].
- 40. The computer system of claim 37, wherein a relaxed ordering attribute phase signal is issued on AD[2].
- 41. The computer system of claim 37, wherein a do not snoop attribute phase signal is issued on AD[3].
- 42. The computer system of claim 37, wherein a lower five bits of an initiator bus number attribute phase signal is issued on AD [8:4].
- 43. The computer system of claim 37, wherein a lower five bits of an initiator number attribute phase signal is issued on AD[13:9].
- 44. The computer system of claim 37, wherein a lower three bits of a sequence number attribute phase signal is issued on AD[16:14].
- 45. The computer system of claim 37, wherein a lower ten bits of a byte count attribute phase signal is issued on AD[26:17].
- 46. The computer system of claim 37, wherein an AD[31:27] of said PCI bus is Reserved.
- 47. The computer system of claim 37, wherein an upper three bits of an initiator bus number attribute phase signal is issued on AD[34:32].
- 48. The computer system of claim 37, wherein an upper one bit of an initiator number attribute phase signal is issued on AD[35].
- 49. The computer system of claim 37, wherein an upper one bit of a sequence number attribute phase signal is issued on AD[36].
- 50. The computer system of claim 37, wherein an upper two bits of a byte count attribute phase signal is issued on AD[38:37].
- 51. The computer system of claim 37, wherein an AD[63:39] portion of said PCI bus is Reserved.
- 52. A method of issuing commands and attributes in a computer system having a central processing unit connected to a host bus, said computer system further having a random access memory connected to a system memory bus, a peripheral component interconnect (PCI) bus operating on a sequential series of clock cycles and capable of implementing registered PCI bus arbitration rules and bus width rules according to a registered PCI protocol, a core logic chipset connected to said host bus, to said PCI bus, and to said system memory bus, said core logic chipset acting as an interface between said host bus and said system memory bus, said host bus and said PCI bus, and said memory bus and said PCI bus, and a PCI device connected to said PCI bus, said method comprising the steps of:
providing a command/byte-enable (C/BE#) portion of said PCI bus; issuing a first command on said C/BE# position of said PCI bus on a first clock cycle of said PCI bus; on a second clock cycle immediately after said first clock cycle, issuing a second command on said C/BE# portion of said PCI bus; providing an AD portion of said PCI bus; contemporaneous with said issuing of said second command, issuing an attribute on said AD portion of said PCI bus.
CROSS REFERENCE TO RELATED APPLICATION
[0001] This patent application is related to commonly owned U.S. patent applications Ser. No. [P-1429] ______, filed on ______, entitled “REGISTERED PCI” by Dwight D. Riley and Christopher J. Pettey; and Ser. No. [CP1289] ______, filed on ______, entitled “APPARATUS, METHOD AND SYSTEM FOR REGISTERED PERIPHERAL COMPONENT INTERCONNECT BUS USING ACCELERATED GRAPHICS PORT LOGIC CIRCUITS” by Sompong Paul Olarig, Dwight D. Riley, and Ronald T. Horan, and are hereby incorporated by reference for all purposes.
Continuations (1)
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Number |
Date |
Country |
Parent |
09747422 |
Dec 2000 |
US |
Child |
10424896 |
Apr 2003 |
US |