Patent Application
20090302893
This invention relates generally to “current mode logic” (CML) integrated circuit memory latches.
Complimentary metal oxide semiconductor field effect transistor (CMOS) “current mode logic” (CML) circuits are widely used for memory latches in very large scale integration (VLSI) computer chip design because they provide high switching speeds.
Three types of CML circuit designs are compared herein, i.e., (a) conventional CML latches; (b) prior art (or regular) “pseudo” CML latches; and (c) the “high speed” pseudo CML latch design(s) of the invention. Conventional CMOS CML latch designs use a three-layer “staggered” transistor circuit configuration involving a “current source” transistor along with “switch” transistor(s) and a “differential transistor pair” plus a resistive output load. However, this configuration has the disadvantage(s) of being unable to provide an acceptably large “rail-to-rail” output voltage differential “swing” (when transitioning from a low level to a high level or vice versa) and also demanding excessive power consumption since the current source transistor is always “on” in an activated state. Regular “pseudo” CML latch designs add a pair of MOSFET (timing clock enabled) switches in the first stage of the circuit to allow less power consumption and to provide higher output voltage differential “swing” than conventional CML latches, but this circuit cannot satisfactorily operate (and loses its low power advantage) at higher speed(s).
This invention overcomes disadvantages experienced with conventional (and regular “pseudo”) CML latch designs, including small output voltage “swing” differential and delayed circuit response time(s) occurring at high operating speeds. The problems experienced with prior art CML latches are solved by incorporating input voltage controlled metal oxide semiconductor field effect transistor (MOSFET) “Negative And” (NAND) logic gate switch(es) in the first stage of a regular “pseudo” CML latch circuit, in order to provide either a low-resistance (or high-resistance) current path to the circuit output node depending on the input voltage level. This circuit enables faster charging (and/or discharging) of the output node, and thus provides higher speed operation (through better response times) when using similar current as other (conventional and regular “pseudo”) CML circuit configurations.
In accordance with at least one presently preferred embodiment of the present invention, there is broadly contemplated herein the incorporation of “Negative And” (NAND) logic gate metal oxide semiconductor field effect transistor (MOSFET) switch(es) in the first stage of a “pseudo” current mode logic (CML) latch to provide a low-resistance (or high-resistance) circuit path to the output depending on the input voltage. These switch(es) are also used to deactivate (or “switch-off”) the first stage of the circuit during the second half of a timing clock cycle, so as to permit the first stage to be activated (or “switched-on”) only during the first half of a clock cycle. “Cross-coupled” inverter(s) are also used in the second stage of the circuit to provide acceptable “rail-to-rail” output voltage differential “swing” using less current. In addition, the second stage also has MOSFET switch(es) which activate (or “switch-on”) only during the second half of a timing clock cycle and are deactivated (or “switched-off”) during the first half of a clock cycle, which (in combination with operation of the first stage circuit) requires use of less current and thus reduces power consumption
The “high speed” pseudo CML latch circuit of the invention uses positive channel (“p-type”) metal oxide semiconductor field effect transistor (PMOS) switch(es) in the 1st stage circuit that are controlled by the output of NAND gate(s). During the “evaluation phase” of the timing clock cycle the state of the PMOS switch(es) is dependent on the input signal level, thus allowing for more rapid and full switching of the “tail current” to enable faster charging (and discharging) of the 1st stage output node and thus providing better performance. During the “latching phase” of the clock cycle the PMOS switch(es) remain deactivated (or “off”), thereby disconnecting the 1st stage circuit from the 2nd stage circuit to allow for quick voltage level retention (or “latching”) at the 2nd stage input(s) in order to produce a “full swing rail-to-rail” output.
In summary, one aspect of the invention provides a high speed integrated circuit memory latch device comprising a first and second current mode logic transistor circuit arrangement for providing:
a. a differential data input signal;
b. a differential output signal;
c. a differential timing clock signal; and
d. a power supply voltage and a bias voltage and a ground voltage;
wherein the differential timing clock signal activates one of the first circuit or the second circuit but not both at the same time such that:
(i). the first circuit operates to change the output signal value according to the level of the input signal; and
(ii). the second circuit operates to hold the output signal to the value set by the first circuit.
Another aspect of the invention provides a method of using a high speed integrated circuit memory latch device comprising a first and second current mode logic transistor circuit arrangement in a computerized system, the method comprising the steps of providing:
a. a differential data input signal;
b. a differential output signal;
c. a differential timing clock signal; and
d. a power supply voltage and a bias voltage and a ground voltage;
wherein the differential timing clock signal activates one of the first circuit or the second circuit but not both at the same time such that:
(i). the first circuit operates to change the output signal value according to the level of the input signal; and
(ii). the second circuit operates to hold the output signal to the value set by the first circuit.
Furthermore, an additional aspect of the invention provides a computerized system using a high speed integrated circuit memory latch device comprising a first and second current mode logic transistor circuit arrangement for providing:
a. a differential data input signal;
b. a differential output signal;
c. a differential timing clock signal; and
d. a power supply voltage and a bias voltage and a ground voltage;
wherein the differential timing clock signal activates one of the first circuit or the second circuit but not both at the same time such that:
(i). the first circuit operates to change the output signal value according to the level of the input signal; and
(ii). the second circuit operates to hold the output signal to the value set by the first circuit.
For a better understanding of the present invention, together with other and further features and advantages thereof, reference is made to the following description, taken in conjunction with the accompanying drawings, and the scope of the invention will be pointed out in the appended claims.
It will be readily understood that the components of the present invention, as generally described and illustrated in the Figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following more detailed description of the embodiments of the apparatus, system, and method of the present invention, as represented in
Reference throughout this specification to “one embodiment” or “an embodiment” (or the like) means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment.
Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided, such as examples of hardware modules, hardware circuits, hardware chips, etc., to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.
The illustrated embodiments of the invention will be best understood by reference to the drawings, wherein like parts are designated by like numerals or other labels throughout. The following description is intended only by way of example, and simply illustrates certain selected embodiments of devices, systems, and processes that are consistent with the invention as claimed herein.
As shown in the preferred embodiment of
Since the timing clock signal is differential (i.e. only one of CLK_P or CLK_N takes a high value at a given point in time) either the first stage circuit or the second stage circuit (but not both) are operating at any point in time, since the (CLK_P) PFET “switches off” the first stage circuit to allow its disconnection during operation of the second stage circuit. When CLK_P is at a high level then the first stage circuit is operating to quickly change the output signal (Out_P & Out_N) according to the input signal level (In_P & In_N). When CLK_P is at a low level (i.e. CLK_N is high) then the second stage circuit is operating to hold (or “latch”) the output signal (Out_P & Out_N) to the value set by the first stage input (In_P & In_N).
As shown in
As seen from the waveform in
Table (I) provides measured circuit response parameters at clock frequencies of one (1 GHz) and three (3 GHz) gigahertz, showing that the “high speed” pseudo CML latch performs better than other (conventional and regular “pseudo”) CML circuits at higher speed(s) since these other circuits fail to operate properly at high frequencies:
It is to be understood that the present invention, in accordance with at least one presently preferred embodiment, includes elements that may be implemented on at least one general-purpose computer. These may also be implemented on at least one Integrated Circuit or part of at least one Integrated Circuit. Thus, it is to be understood that the invention may be implemented in hardware, software, or a combination of both.
If not otherwise stated herein, it is to be assumed that all patents, patent applications, patent publications and other publications (including web-based publications) mentioned and cited herein are hereby fully incorporated by reference herein as if set forth in their entirety herein.
Although illustrative embodiments of the present invention have been described herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments, and that various other changes and modifications may be affected therein by one skilled in the art without departing from the scope or spirit of the invention.
