High speed semiconductor memory

Abstract

A semiconductor memory capable of being operated at high speed is disclosed. Each memory cell consists of a pair of cross-coupled transistors connected between two word lines. Application of the read or write pulse to one of the word lines is detected and the signal thus detected is applied to a delay circuit. The output of the delay circuit is applied to a current switch transistor connected to the other word line for turning it on during the predetermined period of time at least just after the reading or writing cycle of the selected cell, thereby quickly clamping the word lines to the predetermined potentials.

Description

LIST OF PRIOR ART C37CFR 1.56(a)

The following references are cited to show the state of the art:

Japanese laying open Pat. No. 61036/73; and Japanese laid open Pat. No. 22829/74

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor memory, and in particular to a circuit for improving the access time of a semiconductor memory.

A semiconductor memory, such as a bipolar memory, comprises a number of memory cells arranged in the form of matrix. Each cell is connected between a pair of word lines arranged in a row and a pair of digit lines arranged in a column.

When one of the memory cells is selected for writing or reading, an addressing pulse is applied to one of the word lines, which is connected to the selected cell.

The access time of this kind of memory is determined mainly by both the rising and falling time of word line potential changing in response to the addressing pulse applied thereto.

As far as the rising time of the potential on the word line is concerned, the prior art provides some successful solutions to realize a quick or abrupt rising of the potential.

However, the improvement on the falling time of the potential on the word line was considered much more difficult to achieve. In the case where a large number of memory cells are used for a memory array, it is necessary to consider the adverse effect of stray capacity between the word line and ground on the falling time of the potential on the word line. When one of the memory cells is selected for reading or writing, the word line connected thereto is switched to a high potential. This results in the stray capacity between the word line and ground being charged up. Upon the completion of a reading or writing cycle, the word line is returned to a low potential. But, due to the charge stored in the stray capcity during the reading or writing cycle, it takes a relatively long time to clamp the word line to a low potential. This slow falling of the potential on the word line prevents the memory from being operated at a high speed.

One conventional and insufficient attempt to solve this problem is to provide an additional current to the selected cell during the time that the word addressing pulse is being applied to the word line. Measurements showed, however, that the improvement by this attempt was relatively small.

SUMMARY OF THE INVENTION

One object of the present invention is to provide a semiconductor memory capable of being operated at a high speed.

Another object of the present invention is to improve the falling time of the potential on the word line at the time of the switching of the word addressing pulse applied thereto from a high level to a low level.

In accordance with these and other objects, the present invention provides that during the predetermined period of time at least immediately after the reading or writing cycle, a current switch connected to the word line is turned on. This abruptly discharges the charge stored in the stray capacity between the word line and ground.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing a prior art bipolar memory;

FIGS. 2A and 2B show potentials applied to word lines and digit lines when reading and writing respectively;

FIG. 3 shows curves of the potential on a word line, which changes in response to the word addressing pulse;

FIG. 4 is a circuit diagram showing one embodiment of the present invention;

FIG. 5 shows waveforms at various points in FIG. 4;

FIG. 6 shows curves of the potential on a word line;

FIGS. 7, 8 and 9 are circuit diagrams, each showing other embodiments of the present invention;

FIG. 10 shows waveforms at various points in FIG. 9; and

FIG. 11 is a circuit diagram illustrating another embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

THE PRIOR ART

For the purpose of better understanding the present invention, a typical prior art bipolar memory will be explained by referring to FIG. 1.

A memory array includes a large number of memory cells arranged in the form of matrix. In FIG. 1 two rows and two columns of the memory cells C.sub.0, C.sub.1, C.sub.2, and C.sub.3 are illustrated for ease of explanation.

Each of the memory cells C.sub.0 through C.sub.3 consists of a pair of cross-coupled transistors. For example, the memory cell C.sub.0 consists of transistors Q.sub.00 and Q.sub.01 having collectors connected through resistors R.sub.L00, and R.sub.L01 to a word line L.sub.X0 respectively, first emitters connected respectively to digit lines D.sub.00, D.sub.01, and second emitters coupled in common. The common emitter of the pair of transistors Q.sub.00, Q.sub.01 is connected through a resistor R.sub.E0 to a constant current source 10.sub.a which comprises a transistor Q.sub.ST0 having a resistor R.sub.ST0 connected thereto. D.C. voltage V.sub.CS is applied to the base electrode of the transistor Q.sub.ST0 so that the transistor can provide a constant current flowing through a line X.sub.ST0.

The constant current source 10.sub.a is provided for holding the state of each memory cell connected to the two word lines L.sub.X0 and X.sub.ST0 by supplying a current necessary for holding its state during its operating cycle.

The other memory cells C.sub.1, C.sub.3, each comprising a pair of cross-coupled transistors are connected in a similar way to another current source 10b.

Numerals 11, 12, 13 and 14 denote a sensing circuit, a writing control circuit, a digit addressing control circuit and a constant current source, respectively. The sensing circuit 11 includes a pair of transistors Q.sub.ref00 and Q.sub.ref01 connected at their emitter electrodes to the digit lines D.sub.00 and D.sub.01 and connected at their base electrodes by way of a line L.sub.R to a terminal R to which a reference voltage is applied.

The writing control circuit 12 includes a transistor Q.sub.W00 connected at its emitter electrode to the digit line D.sub.00 and connected at its base electrode via a line L.sub.W0 to a terminal W.sub.0. It also includes a transistor Q.sub.W01 connected at its emitter electrode to the digit line D.sub.01 and connected at its base electrode by way of a line L.sub.W1 to a terminal W.sub.1.

The digit addressing control circuit 13 comprises a pair of transistors Q.sub.Y00 and Q.sub.Y01, having emitter electrodes connected to the digit lines D.sub.00 and D.sub.01 respectively, and base electrodes connected in common to the terminal Y.sub.0.

The constant current source 14 includes transistors Q.sub.R00 and Q.sub.R01 each having a base electrode connected to DC voltage V.sub.CS so that each of the transistors can provide a constant current flowing through each digit line.

The reading operation will now be explained by referring to FIG. 2A.

It is assumed for this discussion that the memory cell C.sub.0 is to be selected for reading while the remaining cells such as C.sub.1, C.sub.2 and C.sub.3 are not. The memory cell C.sub.0 is arbitrarily defined as storing information of a logic "0" when the transistor Q.sub.00 is turned on and the transistor is Q.sub.01 turned off. Alternatively, it is defined as storing a logic "1" when the transistor Q.sub.00 is turned off and the transistor Q.sub.01 is turned on. For the purpose of explanation, it is assumed hereinafter that a logic "0" is stored in the memory cell C.sub.0.

During the reading cycle of the selected cell C.sub.0, potentials shown at V.sub.XH, V.sub.XL, V.sub.YL, V.sub.YH and V.sub.RH in FIG. 2A are respectively applied to the terminals X.sub.0, X.sub.1, Y.sub.0, Y.sub.1 and R. The terminals W.sub.0 and W.sub.1 are both at the potential shown at V.sub.WL.

The potential at the collector of the turned-off transistor Q.sub.01 as well as at the base electrode of the turned-on transistor Q.sub.00 is nearly equal to potential V.sub.XH on the word line L.sub.X0. On the other hand, the collector electrode of the transistor Q.sub.00 as well as the base electrode of the transistor Q.sub.01 is at a potential equal to (V.sub.XH -.DELTA.V.sub.S) volts, where .DELTA.V.sub.S indicates voltage drop developed across the resistor R.sub.L00.

The constant current I.sub.R00 provided by means of the transistor Q.sub.R00 is permitted to flow through one of transistors Q.sub.00, Q.sub.10, Q.sub.ref00, Q.sub.W00, Q.sub.Y00 connected to the digit line D.sub.00, whose base electrode is at the highest potential. As will be apparent from FIG. 2A, potential V.sub.XH on the word line L.sub.X0, as well as at the base electrode of the transistor Q.sub.00, is higher than any other potentials at the bases of the transistors Q.sub.10, Q.sub.ref00, Q.sub.W00 and Q.sub.Y0, so that the current I.sub.R00 can flow through the transistor Q.sub.00.

As a result, the transistor Q.sub.ref00 turns off, thereby developing a high level voltage (equal to ground potential) at the collector thereof.

On the other hand, the constant current I.sub.R01 provided by means of transistor Q.sub.R01 flows through either one of transistors Q.sub.01, Q.sub.11, Q.sub.ref01 and Q.sub.Y01 each connected to the digit line D.sub.01, whose base electrode is at the highest potential.

The base electrodes of these transistors Q.sub.01, Q.sub.11, Q.sub.ref01 and Q.sub.Y01 are at potentials of (V.sub.XH -.DELTA.V.sub.S), V.sub.XL (or V.sub.XL -.DELTA.V.sub.N), V.sub.RH, V.sub.WL and V.sub.YL respectively. Therefore, the constant current I.sub.R01 is permitted to flow through the transistor Q.sub.ref01 whose base is at a potential higher than any other base potentials of the transistors connected to the digit line D.sub.01.

As a result, because of the voltage drop developed across the resistor R.sub.S01, the collector of the transistor Q.sub.ref01 is held at low potential.

Next it is assumed that the transistor Q.sub.00 of the memory cell C.sub.0 is turned off and the transistor Q.sub.01 is turned on to store information of a logic "1". In this case, the transistor Q.sub.ref00 provides low potential at its collector electrode while the transistor Q.sub.ref01 provides high potential at its collector.

It is understood from the description discussed above that the information stored in the memory cell C.sub.0 can be read out as potentials at the collectors of the transistors Q.sub.ref00 and Q.sub.ref01.

On the other hand, with respect to the other cells C.sub.2 and C.sub.3 which are not selected, the following operation is achieved. As discussed before, when the memory cell C.sub.0 is selected, a pair of transistors Q.sub.Y10 and Q.sub.Y11 are given at their base electrodes a potential V.sub.YH which is higher than any other potentials at the base electrodes of the transistors Q.sub.20, Q.sub.30, Q.sub.ref10, Q.sub.W10, Q.sub.21, Q.sub.31, Q.sub.ref11, and Q.sub.w11. Consequently, regardless of information stored in the cells C.sub.2 and C.sub.3, the constant currents I.sub.R10 and I.sub.R11 provided by means of the transistors Q.sub.R10 and Q.sub.R11 are respectively permitted to flow through the transistors Q.sub.Y10 and Q.sub.Y11. As a result, the transistors Q.sub.ref10, Q.sub.ref11 both turn off, thereby providing a high level potential (equal to ground potential) at their collectors. This means that information stored in the memory cells C.sub.2 and C.sub.3 cannot be read out.

The operation of writing information into a selected memory cell will now be explained by referring to FIG. 2B.

It is assumed for this discussion that the memory cell C.sub.0 is selected for writing information of a logic "1". In this case, the terminals Y.sub.0, Y.sub.1, X.sub.0 and X.sub.1 are respectively given potentials shown at V.sub.YL, Y.sub.YH, V.sub.XH and V.sub.XL in FIG. 2B. Furthermore, the terminal W.sub.0 and W.sub.1 are at potentials of V.sub.WH and V.sub.WL respectively. It is noted that the potential V.sub.WH at the base electrode of the transistor Q.sub.W00 is higher than the potential at the base electrode of the transistor Q.sub.00 regardless of information stored in the selected cell C.sub.0. Therefore, the constant I.sub.R00 flows through the transistor Q.sub.W00.

On the other hand, the potential at the base of the transistor Q.sub.W01 is lower than that at the base of the transistor Q.sub.01 so that the constant current I.sub.R01 provided by means of the transistor Q.sub.R01 is permitted to flow through the transistor Q.sub.01. Both the constant currents I.sub.R00 and I.sub.R01 are usually selected in their values to be larger than the current I.sub.st so that the states of the transistors Q.sub.00 and Q.sub.01 can be determined by either the current I.sub.R00 or I.sub.R01.

In consequence, the transistor Q.sub.01, through which the constant current I.sub.R01 flows, is turned on while the transistor Q.sub.00 is turned off. Thus the writing of a logic "1" into the selected cell C.sub.0 is achieved.

In a similar manner, when information of a logic "0" is to be written into the selected cell C.sub.0, the potentials V.sub.WH and V.sub.WL are respectively applied to the terminals W.sub.0 and W.sub.1 thereby turning the transistor Q.sub.00 on and turning the transistor Q.sub.01 off.

The other memory cells not selected, for example the memory cell C.sub.2, are not affected by the operation of the writing. Their operation are explained as follows. When the cell C.sub.0 is selected, the base electrodes of the transistors Q.sub.Y10 and Q.sub.Y11 are at the potential indicated at V.sub.YH in FIG. 2B, which is higher than any other potentials at base electrodes of the transistors connected to the digit lines D.sub.10 and D.sub.11. Accordingly, the constant currents I.sub.R10 and I.sub.R11 flowing into the transistors Q.sub.R10 and Q.sub.R11 are permitted to flow through the transistors Q.sub.Y10 and Q.sub.Y11 respectively so that they do not affect any influences on the memory cell C.sub.2.

As is apparent from the above discussion, the holding of information stored in the memory cell not selected during the operation of reading and writing can be achieved by the constant current I.sub.st which is provided by means of the constant current sources 10.sub.a and 10.sub.b. On the other hand, the reading or writing of information out of or into the selected memory cell can be controlled by using the constant current sources Q.sub.R00, Q.sub.R01, Q.sub.R10 and Q.sub.R11 each providing a constant current I.sub.R. In this kind of semiconductor memory, from the viewpoint of access time thereof, it is desirable to stabley and quickly clamp the word lines at a predetermined potential in response to the word addressing pulse applied to the terminal X.sub.0, X.sub.1.

However, the stray capacity (shown at C.sub.S1, C.sub.S2) between each word line and ground, prevents the word lines from being quickly and abruptly clamped. Particularly in the case of using a large number of memory cells for a memory array, both the rising and falling of potential on the word lines are adversely affected by a relatively large value of the stray capacity necessarily existing between the word lines and ground.

FIG. 3 illustrates waveforms of potential on the word line L.sub.X0, changing when the potential applied to the terminal X.sub.0 is switched from a low level (or high level) to a high level (or low level).

In the case where a small number of memory cells are used for an array, the potential on the word line L.sub.X0 can abruptly be clamped to a high level when the word addressing pulse is applied, as shown at (a) in FIG. 3. It can also quickly be clamped to a low level when the addressing cycle is completed, as shown at (b) in FIG. 3. However in the case where a large number of memory cells are used for an array, the potential on the word line L.sub.X0 slowly rises and falls as shown at curves c and d in FIG. 3. With regard to the potential on the other word lines such as X.sub.ST0, the same tendency as discussed above was observed.

As to the rising of potential on the word line, that prior art provides a successful solution in which the word addressing pulse is applied to the word line through a transistor operating in an emitter follower mode.

However, as far as the falling time of word line potential is concerned, the improvement was considered more difficult to achieve.

PREFERRED EMBODIMENTS OF THE INVENTION

A semiconductor memory embodying the present invention will be explained by referring to FIG. 4 in which the same symbols and numerals as in FIG. 1 denote like elements.

In FIG. 4, the terminal X.sub.0 is connected by way of the word line L.sub.X0 to a signal detecting circuit 20.sub.a comprising an emitter follower transistor Q.sub.201. This transistor Q.sub.201 functions to detect the application of the word addressing pulse to the terminal X.sub.0. The output from the detecting circuit 20.sub.a is then introduced into a delay circuit 21a which includes transistors Q.sub.202 and Q.sub.203.

The detected output signal from circuit 20a flows through a resistor R.sub.201, a collector-emitter path of the transistor Q.sub.202 and a resistor R.sub.202 to a D.C voltage source V.sub.EE. By the voltage drop developed across the resistor R.sub.201, an appropriate potential is applied to the base electrode of the emitter follower transistor Q.sub.203. The potential at the base electrode of the transistor Q.sub.203 can arbitrarily be determined by the proper selection of both values of the emitter resistor R.sub.202 and the base potential of the transistor Q.sub.202. In response to the signal applied, the delay circuit 21.sub.a produces an output with a delay time which can be arbitrarily determined by the proper selection of values of the resistors R.sub.201 and R.sub.203, because these resistors serve in conjunction with stray capacitances C.sub.201 and C.sub.203 as determining the time constant of the delay circuit 21.sub.a. In practice, a speed up capacitor C.sub.202 may be connected in parallel with the resistor R.sub.201 to cancel the effect of the stray capacity C.sub.201, if the desired delay time can be obtained by means of the resistor R.sub.203 and the stray capacity C.sub.203.

The delayed signal from circuit 21a is then applied to a current switch circuit 22.sub.a which comprises a transistor Q.sub.204 having an emitter connected through a resistor R.sub.204 to DC voltage source, and a collector connected to the line X.sub.ST0.

Numerals 20.sub.b, 21.sub.b and 22.sub.b respectively denote a detecting circuit, a delay circuit and a current switch circuit which are of the same configurations as discussed above.

In operation of the memory system shown in FIG. 4, when one of memory cells, for example C.sub.0 is to be selected for either writing or reading, a high potential V.sub.XH is applied to the terminal X.sub.0. During this writing or reading cycle, the stray capacitances C.sub.S1 and C.sub.S2 may be charged up. Upon the completion of the writing or reading cycle, the terminal X.sub.0 is returned to a low potential V.sub.HL.

The transistor Q.sub.201 detects the application of the word addressing pulse S.sub.1 shown in FIG. 5 and produces an output signal S.sub.2 at its emitter.

After the predetermined delay time, a signal S.sub.3 appears at the emitter of the transistor Q.sub.203 in response to the signal S.sub.2. The signal S.sub.3 is introduced into the current switch circuit 22.sub.a. As long as the output of the transistor Q.sub.203 applies current, the transistor Q.sub.204 is turned on thereby permitting an increased current flowing through the selected word line X.sub.ST0. Since this additional current flows only through the selected word line connected to the selected cell, its amplitude can be much greater than that of the constant current I.sub.ST0 provided by the source 10.sub.a.

It should be noted that the supply of the current flowing during the period of time from t.sub.3 to t.sub.4 just aftr the completion of the reading or writing cycle (t.sub.1 to t.sub.3) serves to pull the charges out of the stray capacitances C.sub.S1 and C.sub.S2 and discharge them into ground so that the word lines can be quickly clamped to low potential. The most important thing to be considered in the present invention is that after the terminal X.sub.0 is returned to a low level potential V.sub.XL, the transistor X.sub.204 still continues to be turned on for the predetermined period of time equal to the delay time of the delay circuit 102.sub.a. For this period of time, the charges stored in the stray capacitances can be abruptly discharged by way of the transistor Q.sub.204 with the result that the rapid falling of the potentials on the word lines can be achieved.

Measurements have shown that according to the embodiment of FIG. 4, the potential on the word line L.sub.X0 quickly reaches a low level in response to the switching of potential at the terminal X.sub.0 from a high level to a low level, as shown at e in FIG. 6.

On the other hand, if the transistor Q.sub.204 turns on only during the same period of time as the reading or writing cycle for the selected cell, so that in addition to the current I.sub.st, the further current may be provided by means of the transistor Q.sub.204 to the selected word line, the falling of potential on the word line is insufficiently improved as shown at f in FIG. 6.

It is to be understood that in the embodiment of FIG. 4 some variations may be made without departing from the essential features of the invention.

For example, while the detecting circuit 20.sub.a is used for detecting the switching of potential applied to the word line in FIG. 4, it is, of course, possible to use an output from a voltage generating circuit (not shown) employed for a word line addressing. Furthermore, instead of using the delay circuit 21.sub.a, a circuit for enlarging a width of a pulse applied thereto can be connected between the detecting circuit 20.sub.a and the current switch circuit 22.sub.a. In this case, a signal waveform applied to the current switch circuit 22.sub.a is indicated as shown at S.sub.4 in FIG. 5.

In the embodiment of FIG. 4, since the resistors R.sub.201 and R.sub.203 are usually selected to have large values to provide the predetermined delay time, the power consumption by the delay circuit 20.sub.a is relatively small.

FIG. 7 shows a second embodiment of the present invention, in which word lines X.sub.ST0, X.sub.ST1 are connected respectively through diodes D.sub.301, D.sub.302 to a common constant current source 30.

This embodiment is characterized by the use of a diode having a relatively long recovery time. The recovery time is defined as the period of time during which the diode continues to be turned on after the forward voltage across it is removed. Since this kind of diode is well known to those skilled in this art, the detailed description of the structure thereof is not shown.

When no memory cell is selected for either writing or reading, all the diodes are turned off because they are all reversely biased. However, when one of the memory cells, for example C.sub.0 is selected, potential on the line X.sub.ST0 connected thereto becomes higher than that on the other lines not selected, as will be apparent from FIGS. 2A and 2B. Thus only the diode D.sub.301 is forward biased.

Upon the completion of the writing or reading cycle for the selected cell C.sub.0, the line X.sub.ST0 is returned to a low potential causing the diode D.sub.301 to be again reversely biased.

It is noted that the diode D.sub.301 becomes turned off with a delay time so that the constant current I.sub.30 can still flow through the diode D.sub.301 for the predetermined time after the completion of reading or writing cycle for a selected cell.

As discussed before, the supply of the such current I.sub.30 serves to abruptly discharging the charges stored in the stray capacitances into ground so that a relatively quick falling of potential on the word lines L.sub.XO and X.sub.STO can be accomplished.

In practice, the embodiment of FIG. 7 is characterized by the simplicity of its circuit configuration and small power consumption necessary for providing the constant current.

FIG. 8 shows a third embodiment of the present invention. A word addressing pulse generating circuit 40.sub.a comprises a pair of transistors Q.sub.405 and Q.sub.406. Between the collector electrodes of the transistors Q.sub.405, Q.sub.406 and ground, resistors R.sub.405 and R.sub.406 are respectively connected. The emitters coupled in common are connected to a constant current source 400. A low potential is applied to one of the base electrodes of the transistors Q.sub.405, Q.sub.406 and a high potential is applied to the other. The output from the collector of the transistor Q.sub.406 is applied to the word line L.sub.X by way of an emitter follower transistor Q.sub.404.

The output derived from the collector of the other transistor Q.sub.405 is applied to a delay circuit 41.sub.a consisting of a resistor R.sub.401 and a capacitor C.sub.401 and then introduced into the base electrode of a PNP type transistor Q.sub.401. A signal appearing at the collector of the transistor Q.sub.401 is applied to a current switch transistor Q.sub.402 by way of another delay circuit 42.sub.a including a capacitor C.sub.402 and a resistor R.sub.403.

In actual practice, the connection of either one of the delay circuits 41.sub.a, 42.sub.a may be sufficient to obtain the desired delay time. Furthermore, stray capacitances between the lines 43, 44 and ground may be used instead of connecting the capacitors C.sub.401, C.sub.402.

In the case where the particular type of transistor has a slow response characteristics, such when a lateral PNP type transistor is used as the transistor Q.sub.401, no additional delay circuit will be needed.

When the memory cell C.sub.O is selected for either writing or reading, a low level voltage is derived from the collector of the transistor Q.sub.405, while a high level voltage is applied to the word line L.sub.XO. The low level voltage applied to the transistor Q.sub.401 causes it to turne on. The output appearing at the collector of the transistor Q.sub.401 is applied to the base electrode of the transistor Q.sub.402 thereby turning it on to provide an additional current to the selected word line L.sub.XO.

Upon the completion of the reading or writing cycle for the selected cell C.sub.O, the word line L.sub.XO is returned to a low potential, and the transistor Q.sub.405 produces a high level output at its collector.

However, due to the delay time provided by means of the circuit 41.sub.a and 42.sub.a, the transistor Q.sub.402 continues to be turned on for a while after the completion of the reading or writing cycle. Accordingly, the same operation as discussed before with reference to FIGS. 4 and 7 can be achieved.

In FIG. 9 showing a fourth embodiment of the present invention, one of outputs from the word addressing signal generating circuit 60.sub.a is directly applied to an emitter follower transistor Q.sub.601, and the other output of reverse phase is applied to a delay circuit 61.sub.a through a transistor Q.sub.604. Both the signals from the transistor Q.sub.601 and the delay circuit 61.sub.a are applied to a gate 62.sub.a to produce an AND logic output which is applied to a current switch transistor Q.sub.602.

It is again assumed that the memory cell C.sub.O is selected for either writing or reading. The circuit 60.sub.a produces at a terminal P.sub.1 an output W.sub.1 and at a terminal P.sub.2 an output W.sub.2 as shown in FIG. 10. The signal at the terminal P.sub.2 is delayed by the circuit 61.sub.a for the desired time and then applied to the AND gate 62.sub.a. Accordingly, the AND gate 62.sub.a produces an output as shown at W.sub.3 in FIG. 10, which is applied to the current switch transistor Q.sub.602. As long as the output from the AND gate 62.sub.a is being applied to the transistor Q.sub.602, its transistor turns on so as to provide an additional current to the selected word line L.sub.XO. It should be noted, in this embodiment that the additional current is allowed to flow only during the time from t.sub.3 to t.sub.4 rather than the period of time from t.sub.2 to t.sub.4. However for the purpose of achieving the quick falling of potentials on the word lines L.sub.XO and X.sub.STO, such period of time is effectively sufficient. The foregoing description is directed to one type of a bipolar memory array, but the present invention may, of course, be adapted to any other type of memory array.

For example, FIG. 11 shows a fifth embodiment of the present invention, in which a different type of memory cell is used. Since the circuit configuration of such memory cell is well known, its detailed description will be omitted.

When the memory cell C.sub.O ' is selected, the transistor Q.sub.501 is turned on and the other transistor Q.sub.502 turned off. Upon the completion of selection of the memory cell C.sub.O ', the transistor Q.sub.501 is returned to its turned off state. However, at the time of the switching of the transistor Q.sub.501 from on to off, the slow falling of potential on the line 54.sub.a prevents the memory from being operated at a high speed.

In order to solve this problem, the same circuit arrangement as described with reference to FIG. 4 may be used. Blocks 50.sub.a, 51.sub.a and 52.sub.a denote respectively a detecting circuit, a delay circuit and a current switch circuit. These elements are of the same circuit configuration as in FIG. 4 and may operate in the same manner to provide the additional current to the selected word line. It will be appreciated therefore that this embodiment also achieves the quick falling of potential on the selected line. It is to be understood that the above-identified arrangements are simply illustrative of the application of the principles of this invention. This invention is not limited to the particular details of connections described and various variations can be readily made without departing from the essential features of invention. It is accordingly desired that the appended claims be given a broad interpretation commensurate with the scope of the invention within the art.

Claims

1. A semiconductor memory comprising:

a memory array including a number of memory cells arranged in the form of a matrix, each memory cell being connected between a first word line to which a word line addressing pulse is applied and a second word line to which a constant current source is connected;

first means for detecting said word line addressing pulse applied to the first word line;

second means, connected to said detecting means, for producing a signal, based upon said detected signal, appearing for a predetermined period of time at least just after the application of the word line addressing pulse to the selected word line;

a current switch means, connected to said second word line, for allowing a current to flow through the memory cells connected to the selected word line in addition to a current provided by means of said constant current source; and

third means for applying the output from the second means to said current switch means thereby turning it on for said predetermined period of time.

2. A semiconductor memory as defined in claim 1 wherein said second means comprises a delay circuit for delaying an output of the first means.

3. A semiconductor memory as defined in claim 1 wherein said second means comprises a circuit for enlarging a width of an output signal of the first means.

4. A semiconductor memory as defined in claim 1, wherein said first means is connected to one terminal of the first word line, opposite to the terminal of said first word line to which the word addressing voltage is applied.

5. A semiconductor memory as defined in claim 1, wherein the word line addressing pulse generating circuit includes a pair of transistors emitters commonly coupled to a constant current source, the addressing voltage being derived from the collector of the one of transistors.

6. A semiconductor memory as defined in claim 5, wherein the first means comprises means for deriving a voltage from the collector of the other transistor.

7. A semiconductor memory as defined in claim 6 in which the second means comprises;

means for delaying a signal on the word line; and

means for producing an AND logic output of said delayed signal and the output from the first means.

8. A semiconductor memory comprising:

a memory array including a number of memory cells arranged in the form of a matrix, each memory cell being connected between a first word line to which a word line addressing voltage is applied and a second word line to which a constant current source is connected;

a plurality of diodes, each having a relatively long recovery time, connected to the second word line for detecting changes in potential on the second word line, each diode being turned on when the word line addressing voltage is applied to the first word line; and

a constant current source, connected to all the diodes, for providing a current flowing through one of the diodes to the selected memory cell.

9. A semiconductor memory as defined in claim 8, wherein the recovery time of said plurality of diodes is sufficiently long to continue to apply current to the memory cells from the constant current source connected to the diodes for a sufficient period of time following the completion of a word line addressing pulse to discharge stray capacitances on the word lines.

10. A semiconductor memory as defined in claim 1, wherein said predetermined period of time includes a sufficient period of time following the completion of a word line addressing pulse to allow the additional current provided by the current switch means to discharge stray capacitances on the word lines.

11. A semiconductor memory as defined in claim 6, wherein the first means includes a sensing transistor coupled to the collector of said other transistor, and the second means includes a first delay means coupled between the sensing transistor and the collector of said other transistor and a second delay means coupled between the sensing transistor and the current switch means.