High-speed serial data transmitter architecture

Abstract

Serial data transmitter circuitry on a PLD includes a number of features that enable the transmitter to support many different communication protocols under a wide range of circuit conditions. Examples of features that the transmitter may include are (1) multiple pre-emphasis circuits of selectable strength and polarity, (2) selectable VOD, (3) selectable slew rate, (4) calibratable termination, (5) selectable common mode voltage, and (6) electrical idle mode.

Description

BACKGROUND OF THE INVENTION

This invention relates to programmable logic devices (“PLDs”) and other integrated circuits of that general type (all generically referred to for convenience as PLDs). More particularly, the invention relates to high-speed serial data transmitter circuitry for inclusion on PLDs.

PLDs are intended as relatively general-purpose devices. A PLD can be programmed (configured) to meet any need within the range of needs that the PLD is designed to support. A PLD may be equipped with high-speed serial data communication circuitry, whereby the PLD can transmit serial data to and/or receive serial data from circuitry that is external to the PLD. In that case, it is desirable for the high-speed serial data communication circuitry of the PLD to be able to support various communication protocols that various users of the PLD product may wish to employ. It is also desirable for the PLD's high-speed serial data communication circuitry to be able to perform successfully in various circuit or system contexts. This invention provides high-speed serial data transmitter circuitry that can be configured to meet a wide range of possible needs.

SUMMARY OF THE INVENTION

In accordance with the invention, serial data transmitter circuitry on a PLD may include such features as (1) multiple pre-emphasis circuits of selectable strength and polarity, (2) selectable VOD (differential output voltage), (3) selectable slew rate (steepness of transitions in the transmitter output signals), (4) calibratable termination resistor circuitry, (5) selectable common mode voltage, and/or (6) an electrical idle mode of operation. These various features may be programmably controlled (e.g., from programmable configuration random access memory (“CRAM”) cells on the PLD) and/or more dynamically controlled (e.g., from user-mode signals on the PLD). The control may involve selective enablement or disablement of a feature and/or selection of an operating characteristic or parameter for the feature.

Further features of the invention, its nature and various advantages, will be more apparent from the accompanying drawings and the following detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified schematic block diagram of an illustrative embodiment of circuitry in accordance with the invention.

FIG. 2 is a simplified schematic block diagram of an illustrative embodiment of circuitry in accordance with the invention that can be used with the FIG. 1 circuitry.

FIG. 3 is a simplified schematic block diagram of an illustrative embodiment of elaboration of portions of the FIG. 1 circuitry in accordance with the invention.

FIG. 4 is a simplified schematic block diagram of an illustrative embodiment of elaboration of other portions of the FIG. 1 circuitry in accordance with the invention.

FIG. 5 is another simplified depiction of what is shown in FIG. 1, etc., which also shows illustrative embodiments of some possible additional features in accordance with the invention.

FIG. 6 is still another simplified depiction of what is shown in FIG. 1, etc., which also shows an illustrative embodiment of a possible further feature in accordance with the invention.

FIG. 7 is a simplified schematic block diagram showing an illustrative context in which the invention may be used.

FIG. 8 is a simplified schematic block diagram of circuitry that can be used at various points in circuitry of earlier FIGS. in accordance with the invention.

DETAILED DESCRIPTION

A portion of illustrative transmitter circuitry 10 is shown in FIG. 1. Circuitry 10 includes the following elements: variable current sources 20, 22, 24, and 26; PMOS transistors M1, M2, M5, M6, M9, M10, M13, and M14; NMOS transistors M3, M4, M7, M8, M11, M12, M15, and M16; variable current sources 30, 32, 34, and 36; pre-driver circuits 40, 42, 44, and 46; variable termination resistors 50a and 50b, and common mode driver circuitry 60.

The serial data signal to be transmitted is applied (in differential form) to the inputs of each of pre-driver circuits 40, 42, 44, and 46. Pre-driver circuitry 40 and the circuit elements 20, 30, and M1-M4 associated with that pre-driver are the “main” driver circuitry of transmitter 10. These components typically supply a major portion of the power to the differential output terminals TX_P and TX_N of the transmitter. Accordingly, the differential output signal (TX_P, TX_N) of the transmitter is intended to correspond to the serial data signal applied to main pre-driver 40. However, output signal TX_P, TX_N may additionally be given pre- and/or post-emphasis by operation of other components of the transmitter as described below. (In general, the term pre-emphasis will be used as a generic term for all forms of pre- and post-emphasis that are shown and described herein.)

As shown in FIG. 2, the serial data signal applied to main pre-driver 40 is also applied, one bit interval earlier (and possibly inverted), to pre-driver 42, which may therefore be referred to as pre-tap pre-driver 42. In FIG. 2 each of circuit elements 110a-c delays the serial data input signal by one unit interval (“UI”) of that signal. A UI is the time duration of one bit in the data signal. The input signal to delay circuit element 110a is also applied to one selectable input terminal of multiplexer (“mux”) 120 and to inverter 122. The output signal of inverter 122 is applied to the other selectable input terminal of mux 120. Mux 120 is controlled by programmable configuration random access memory (“CRAM”) cell 124 to select as its output signal one or the other of its primary or selectable inputs. The output signal of mux 120 is applied to pre-tap pre-driver 42. Thus the circuitry shown in FIG. 2 can apply the serial data signal, either with or without inversion (depending on the state of CRAM 124), to pre-tap pre-driver 42 one UI before the data signal is applied (from the output of delay circuitry 110a) to main pre-driver 40.

Continuing with FIG. 2, the signal applied to main pre-driver 40 is delayed a further UI by delay circuit element 110b and applied to 1st post pre-driver 44. The output signal of delay circuit element 110b is delayed yet another UI by delay circuit element 110c and applied (with or without inversion) to 2nd post pre-driver 46. The circuitry for selectable inversion of this last signal is similar to that for the signal going to pre-tap pre-driver 42. In particular, this selectable inversion circuitry includes mux 130, inverter 132, and mux selection control CRAM 134.

The output signals of each of pre-drivers 40, 42, 44, and 46 can make a contribution to the final transmitter output signal TX_P, TX_N via the associated current sources 20, 22, etc., and 30, 32, etc., and the associated transistors M. For example, elements 20, 30, and M1-M4 are associated with main pre-driver 40. Elements 20, M1, M4, and 30 are connected in series between VCC and ground. Elements M2 and M3 are connected in series with one another in parallel with elements M1 and M4. TX_N is connected to the node between M1 and M4. TX_P is connected to the node between M2 and M3. The “true” output signal of main pre-driver 40 controls turn-on and turn-off of complementary transistor M1 and M4. The “complement” output signal of main pre-driver 40 similarly controls turn-on and turn-off of complementary transistors M2 and M3. For example, M1 is off and M4 is on when the true output of pre-driver 40 is high. M1 is on and M4 is off when the true output of pre-driver 40 is low. M2 is always off when M1 is on, and vice versa. Similarly, M3 is always off when M4 is on, and vice versa. When M1 and M3 are turned on, current sources from current source 20 through M1, through resistors 50b and 50a, and sinks to current source 30 through M3. This places TX_N on the high-potential side of resistors 50, and it places TX_P on the low-potential side of those resistors. When the applied data signal reverses polarity, M2 and M4 are on and M1 and M3 are off. Accordingly, current sources from current source 20 through M2, through resistors 50a and 50b, and sinks to current source 30 through M4. TX_P and TX_N are therefore driven to reverse polarity relative to their polarity when M1 and M3 were on and M2 and M4 were off.

Each of the other pre-drivers 42, 44, and 46 have associated arrangements of current sources and transistors identical to the arrangement described above for pre-driver 40. For example, associated with pre-tap pre-driver 42 are current sources 22 and 32 and transistors M13-M16. This arrangement of pre-tap circuit elements can make a contribution to signals TX_P and TX_N by the same means that the above-described main circuit elements can make. Of course, the contributions actually made by these two groups of circuit elements, at any given time, are typically different from one another. But whatever these contributions are, they are added together by virtue of being applied in parallel to the conductors leading to TX_P and TX_N.

Everything said in the preceding paragraph is equally applicable to the circuitry associated with 1st post pre-driver 44 (i.e., current sources 24 and 34 and transistors M5-M8). It is also equally applicable to the circuitry associated with 2nd post pre-driver 46 (i.e., current sources 26 and 36 and transistors M9-M12).

The strength of each of the above-mentioned contributions to TX_P and TX_N is controlled by the strength of the associated variable current sources 20, 22, etc., and 30, 32, etc. The strength of each current source is preferably programmably controlled, e.g., as shown in FIG. 3. In particular, FIG. 3 shows several CRAM cells 210a-c being used to control the strength of a representative variable current source. For example, each CRAM cell that is programmed logic 1 may turn on an additional one of several parallel transistors in the current source, thereby increasing the strength of the current source. Current sources that are associated with one another (e.g., 20 and 30) may be controlled similarly, in tandem, or in common. However, each such pair of associated current sources may be controlled independently of other pairs. Thus, for example, the control 210 for current sources 20 and 30 may be independent of the control 210 for current sources 22 and 32.

The strength of current sources 20 and 30 controls the VOD (differential offset voltage) parameter of transmitter 10. VOD is the basic or nominal voltage difference between TX_P and TX_N during transmission of data. (Of course, the polarity of this difference reverses each time the data changes from 0 to 1 or vice versa.) In an illustrative embodiment, VOD can be selected to have any of several values in the range from 200 mv to 1400 mv. This selection is made by appropriately programming the CRAM cells 210 that control the strength of main current sources 20 and 30. The stronger these current sources are, the higher VOD is.

The strength of the other current sources controls the strength of the contribution to TX_P and TX_N from pre-tap pre-driver 42 and its associated circuitry, from 1st post pre-driver 44 and its associated circuitry, and from 2nd post pre-driver 46 and its associated circuitry. For example, the strength of current sources 22 and 32 controls the strength of the pre-emphasis contribution from circuit elements 22, 32, 42, and M13-M16. The strength of current sources 24 and 34 controls the strength of the 1st post emphasis contribution from circuit elements 24, 34, 44, and M5-M8. The strength of current sources 26 and 36 controls the strength of the 2nd post emphasis contributions from circuit elements 26, 36, 46, and M9-M12. In each case, the strength of the current sources mentioned in this paragraph may be programmably controlled in the manner generically illustrated by FIG. 3. It may be desirable to have more different strength options to select from for main currents sources 20 and 30. Somewhat fewer strength options may be sufficient for secondary current sources 22, 24, 26, 32, 34, and 36.

Another transmitter control feature that is shown in FIG. 1 is slew rate control (see also FIG. 4). Slew rate control determines the edge rate of each of pre-drivers 40, 42, 44, and 46. Edge rate is the steepness of transitions (from 1 to 0 and vice versa) in the output signals of a pre-driver in response to a change in polarity of the data signals applied to that pre-driver. The programmed state of CRAM 310 determines whether this edge rate is relatively fast (relatively steep output transitions) or relatively slow (relatively less steep output transitions). Slew rate may be controlled in common for all of pre-drivers 40, 42, 44, and 46 (e.g., from one common CRAM 310), or there can be more individual slew rate control for the pre-drivers (e.g., by providing a separate CRAM 310 for each pre-driver).

Still another transmitter control feature that is shown in FIG. 1 is TX_ELEC_IDLE. (See also FIG. 4 again.) When this signal is asserted, all of pre-drivers 40, 42, 44, and 46 go into a tri-state-type mode in which they turn off all of the transistors M connected to their outputs. One possible use of this condition is in a receiver detect mode of operation of the circuitry. This mode is described later in this specification. Because it may be desired to assert or negate TX_ELEC_IDLE at various times during operation of the circuitry, this signal may come from a dynamic signal source (such as state machine circuitry on the PLD) rather than from a more static source such as a CRAM cell.

Although elements 50a, 50b, and 60 are shown in FIG. 1, it may be easier to see them in FIG. 5 (in which the remainder of the circuitry from FIG. 1 is greatly simplified in triangle 12 (labeled TX Driver)). Accordingly, the following discussion of these elements will refer primarily to FIG. 5.

Termination resistors 50a and 50b are connected in series across the leads to TX_P and TX_N. Common mode driver circuitry 60 is connected in series between the node between resistors 50 and ground.

Each of resistors 50 has variable resistance, which is selectable by signals from CRAM cells 410. For example, each of resistors 50 may have resistance that is selectable to be 50 ohms, 60 ohms, or 75 ohms, depending on the programmed state of CRAM cells 410. Accordingly, the termination resistance connected across TX_P and TX_N can be 100, 120, or 150 ohms. This feature can be used to help transmitter 10 better match the impedance of whatever external circuitry the transmitter is driving.

Common mode driver circuitry 60 is a variable voltage source. Vtt_CONTROL signals 420 can be used to control the voltage circuitry 60 maintains at its upper (positive) terminal. This is the so-called common mode voltage (“VCM”) of transmitter 10. Accordingly, the circuitry allows the VCM of transmitter 10 to be selected to have any of several possible values. Because some communication protocols may require VCM to be different at different times during operation of the PLD, Vtt_CONTROL signals 420 may come from a relatively dynamic signal source such as state machine circuitry on the PLD. Alternatively, if it desired for VCM to be selectable but not dynamically changeable, Vtt_CONTROL signals 420 may come from programmable CRAM cells on the PLD.

Some communication protocols such as PCI-Express require support for an electrical idle mode and a receiver detect capability. Receiver detect is the ability to detect the presence or absence of receiver circuitry at the other end of a communication link. FIG. 6 shows typical receiver detect circuitry. To do a receiver detect, transmitter 10 is placed in electrical idle mode as described earlier in this specification. VCM is then varied by changing Vtt_CONTROL as described above. The effect of this change in VCM on the TX_P and TX_N will depend on whether or not receiver circuitry 620 (FIG. 7) is connected at the other end of communication link 610. Receiver detect circuitry 510 (FIG. 6) is operable to detect whether the signals on TX_P and TX_N are indicative of the presence of a receiver 620 or not.

We now recapitulate the many capabilities of the transmitter architecture described above. As the industry introduces more and more communication standards to cover a vast application space, the solution provided by a programmable transceiver becomes more demanding. The data rates span from as low as 600 MBps to 6 GBps. To make it more difficult, even the bandwidth keeps increasing. To keep the cost of the system down, the interconnect materials stay the same as the previous generation(s). That translates to a degrading performance of the medium at higher frequencies, resulting in a big challenge to the transceiver design.

The present invention provides one transmitter design to meet the different electrical specifications for such parameters as VOD, termination, rise/fall time, etc. This transmitter design satisfies a wide range of signal integrity requirements. For example, this transmitter architecture can be used to send signals through mediums that have frequency-dependent characteristics as shown in the balloon above communication link 610 in FIG. 7. This architecture addresses the fact that power consumption increases with high frequency, and so do noises. This architecture also supports special feature requirements of certain communication protocols (e.g., the above-described requirements of PCI-Express for electrical idle mode and receiver detect capability).

The transmitter driver architecture of this invention employs the following features to enhance performance and power. First, the architecture employs H-tree driver circuitry for high performance, coupled with efficient power/area/noise reduction. (See, for example, commonly assigned, co-pending Asaduzzaman et al. U.S. patent application Ser. No. 11/192,607, filed Jul. 29, 2005.) Second, the architecture employs separation of powers for the pre-driver and driver circuitries. Note in connection with this second point that FIG. 1 shows current sources 20, 22, etc., and 30, 32, etc. powering the driver portion of the circuitry, but not pre-drivers 40, 42, 44, and 46. These pre-drivers can have power separate from elements 20, 22, and so on.

The following controls are programmable or selectable: VOD, pre-emphasis pre-tap, two post-taps, inversion for pre-tap and second post-tap, slew-rate switch, calibration termination, and common mode driver.

With regard to VOD, the transmitter is required to produce differential output voltage for different specifications. It is capable, in an illustrative embodiment, of driving a differential peak-to-peak signal ranging from 200 mv to 1400 mv. The control bits VOD in FIG. 5 (corresponding to the output signals of CRAM bits 210 in FIG. 3 for current sources 20 and 30) can be programmed during configuration of the field-programmable gate array (“FPGA”; another term for PLD), or in user mode for a specific VOD setting. (FIG. 8 shows how any CRAM control can be alternatively made more dynamic, user-mode control. The output signal of any CRAM described earlier in this specification (e.g., a CRAM 210) is applied to one selectable input terminal of mux 712. A possibly more dynamic, user-mode signal is applied to the other selectable input terminal of mux 712. Mux 712 is controlled by the output signal of programmable CRAM cell 710 to select either of its primary input signals to be its output signals. Accordingly, if programmable control from a CRAM like 210 is desired, mux 712 is programmably controlled to pass the output signal of that CRAM. If user-mode control is desired, mux 712 is programmably controlled to pass the possibly more dynamic, user-mode signal. Thus any control described earlier in this specification as programmable can be alternatively made more dynamic using the principle illustrated by FIG. 8. Similarly, any control described earlier as dynamic can be alternatively made programmable using the FIG. 8 principle.

With regard to pre-emphasis, as the transmission system degrades at high frequency, the signal is not only attenuated but also gets distorted in shape, resulting in a setback to a quality signal arriving at its destination. To overcome these obstacles, the present transmitter is equipped with pre-emphasis resources from one pre-tap and two post-taps with different amplitudes. In an illustrative embodiment, the transmitter is targeted to drive up to 40 inches of FR4 at 6.375 Gbps. To be more flexible, the pre-tap and second post-tap polarities can be inverted. Each tap has several settings for different amounts or levels of the pre-emphasis. In FIG. 5 the control bits pre-tap control (corresponding to the output signals of CRAM bits 210 in FIG. 3 for current sources 22 and 32), 1st post-tap control (corresponding to the output signals of CRAM bits 210 in FIG. 3 for current sources 24 and 34), and 2nd post-tap control (corresponding to the output signals of CRAM bits 210 in FIG. 3 for current sources 26 and 36) are used to set the pre-emphasis level(s). The more control bits provided, the more fine-grained the pre-emphasis levels that can be selected. However, the cost over performance and layout may be considered for optimization.

With regard to signal inversion on pre-emphasis taps, different back-planes may have different characteristics. The ability to selectively invert certain taps provides flexibility to compensate for the distortion at the far end. The control bits in FIG. 5 labeled PRE-TAP_INV and SECOND-TAP_INV (corresponding, respectively, to the outputs of CRAM cells 124 and 134 in FIG. 2) provide this option.

With regard to slew rate control, fast edge rates introduce high frequency components in the transmitted signal. This can result in inter-symbol interference (“ISI”) and jitter. In a back-plane where traces are highly susceptible to noise, fast edge rate can also cause functional failure. Therefore, in applications where the data rates do not require fast switching (e.g., below about 3 Gbps), the slew rate control is used to slow down the edge rates. The slew rate control signal(s) in FIG. 5 (see also FIGS. 1 and 4) is (are) used to adjust the rise/fall time at the output pins TX_P and TX_N. (See, for example, commonly assigned, co-pending Asaduzzaman et al. U.S. patent application Ser. No. 11/183,288, filed Jul. 14, 2005.)

With regard to the common mode driver, this component (60) provides a low impedance termination path to common mode voltage. The control bits 420 in FIG. 5 can be programmable to select different common mode voltages to support different standards. This circuitry is also used to support electrical idle mode by itself or together with receiver detect circuit 510 (FIG. 6) to support PCI-Express.

The transmitter circuitry also has a calibration feature with on-chip termination (variable resistors 50). This can be used to absorb any reflection that bounces back from the interconnect medium, since there can be several discontinuities from the driver to the receiver (e.g., a connector). The calibration unit provides offset to the termination due to process variation. Some specifications might ask for termination different than 100 ohm differential. In FIG. 5, control bits 410 (TERM_CONTROL) allow 120 ohm and 150 ohm termination.

Further with regard to electrical idle, the signal Tx_ELEC_IDLE in FIG. 5 is asserted to get the transmitter driver into idle mode in PCI-Express. See also the above discussion of common mode driver 60.

As has been noted, receiver detect is a requirement to support PCI-Express. This circuitry is used in conjunction with the TX driver. It needs both pins in the TX driver to feed back the signals sensed from the link to see if there is a presence of the receiver at the other end. In addition, the signal TX_DETECT_RX (FIG. 6) is asserted to start receiver detect circuit block 510. The result can be observed in the two signals VALID and RX_FOUND in FIG. 6.

In sum, transmitter design is encountering more challenges as a result of the complex nature of the requirements. The transmitter of this invention, with the described features and programmable controls, provides the solution to a wide range of applications within one product.

It will be understood that the foregoing is only illustrative of the principles of the invention, and that various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention. For example, not all of the features shown and described herein need to be included in all embodiments of the invention.

Claims

1. Serial data transmitter circuitry on a PLD comprising: a main data signal circuit for applying a data signal to an output of the transmitter circuitry;a pre-tap signal circuit for applying an advance replica of the data signal to the output;a post-tap signal circuit for applying a delayed replica of the data signal to the output;signal strength circuitry for controlling drive strength of at least one of the main data signal circuit, the pre-tap signal circuit, and the post-tap signal circuit;slew rate control circuitry for controlling slew rate of at least one of the main data signal circuit, the pre-tap signal circuit, and the post-tap signal circuit;programmable selectable inversion circuitry for programmably selectively inverting at least one of the advance replica and the delayed replica prior to use of said at least one replica by the one of the pre-tap signal circuit and the post-tap signal circuit that applies that replica to the output;common mode voltage circuitry for controlling common mode voltage of the output; andtermination circuitry for providing controllable termination resistance to the output.

2. The circuitry defined in claim 1 wherein the advance replica precedes the data signal by one unit interval of the data signal.

3. The circuitry defined in claim 1 wherein the delayed replica trails the data signal by one unit interval of the data signal.

4. The circuitry defined in claim 1 further comprising: a second post-tap signal circuit for applying a further delayed replica of the data signal to the output.

5. The circuitry defined in claim 4 wherein the further delayed replica trails the delayed replica by one unit interval of the data signal.

6. The circuitry defined in claim 1 further comprising: circuitry for selectively placing the main data signal circuit, the pre-tap signal circuit, and the post-tap signal circuit in an electrical idle mode.

7. The circuitry defined in claim 1 wherein the main data signal circuit comprises: a main pre-driver circuit; anda main driver circuit connected between the main pre-driver circuit and the output.

8. The circuitry defined in claim 7 wherein the main driver circuit comprises current source circuitry of variable strength.

9. The circuitry defined in claim 8 wherein the current source circuitry is separate from power supply circuitry of the main pre-driver circuit.

10. The circuitry defined in claim 8 wherein the signal strength circuitry controls the strength of the current source circuitry.

11. The circuitry defined in claim 1 wherein the signal strength circuitry comprises at least one programmable CRAM cell for influencing operation of the signal strength circuitry.

12. The circuitry defined in claim 1 wherein the slew rate control circuitry comprises at least one programmable CRAM cell for influencing operation of the slew rate control circuitry.

13. The circuitry defined in claim 1 wherein the selectable inversion circuitry comprises at least one programmable CRAM cell for influencing operation of the selectable inversion circuitry.

14. The circuitry defined in claim 1 wherein the common mode voltage circuitry comprises at least one programmable CRAM cell for influencing operation of the common mode voltage circuitry.

15. The circuitry defined in claim 1 wherein the termination circuitry comprises at least one programmable CRAM cell for influencing operation of the termination circuitry.

16. A PLD including serial data transmitter circuitry comprising: a main data signal circuit for applying a data signal to an output of the transmitter circuitry with controllable strength;a pre-tap signal circuit for applying a replica of the data signal that is advanced by one UI to the output with controllable strength;a first post-tap signal circuit for applying a replica of the data signal that is delayed by one UI to the output with controllable strength;a second post-tap signal circuit for applying a replica of the data signal that is delayed by two UIs to the output with controllable strength; andprogrammable selectable inversion circuitry for programmably selectively inverting either or both of the replica that is advanced by one UI or the replica that is delayed by two UIs prior to use of such a replica by the one of the pre-tap signal circuit and the second post-tap signal circuit that applies that replica to the output with controllable strength.

17. The circuitry defined in claim 16 further comprising: slew rate control circuitry for controlling slew rate of at least one of the main data signal circuit, the pre-tap signal circuit, the first post-tap signal circuit, and the second post-tap signal circuit.

18. The circuitry defined in claim 16 further comprising: common mode voltage circuitry for controlling common mode voltage of the output.

19. The circuitry defined in claim 16 further comprising: termination circuitry for providing controllable termination resistance to the output.

20. The circuitry defined in claim 16 further comprising: circuitry for selectively placing the main data signal circuit, the pre-tap signal circuit, the first post-tap signal circuit, and the second post-tap signal circuit in an electrical idle mode.

21. Serial data transmitter circuitry on a PLD comprising: a main data signal circuit for applying a data signal to an output of the transmitter circuitry with selectable strength;a pre-tap signal circuit for applying a replica of the data signal that is advanced by one UI to the output with selectable strength and programmably selectable polarity, which can be programmably selected to be the same as or opposite from polarity of the main data signal;a first post-tap signal circuit for applying a replica of the data signal that is delayed by one UI to the output with selectable strength; anda second post-tap signal circuit for applying a replica of the data signal that is delayed by two UIs to the output with selectable strength and programmably selectable polarity, which can be programmably selected to be the same as or opposite from polarity of the main data signal.

22. The circuitry defined in claim 21 further comprising: slew rate control circuitry for controlling slew rate of at least one of the main data signal circuit, the pre-tap signal circuit, the first post-tap signal circuit, and the second post-tap signal circuit.

23. The circuitry defined in claim 21 further comprising: common mode voltage circuitry for controlling common mode voltage of the output.

24. The circuitry defined in claim 21 further comprising: termination circuitry for providing controllable termination resistance to the output.

25. The circuitry defined in claim 21 further comprising: circuitry for selectively placing the main data signal circuit, the pre-tap signal circuit, the first post-tap signal circuit, and the second post-tap signal circuit in an electrical idle mode.