Patent Application
20080233800
This relates generally to high speed signal backplane interfaces.
High speed signal backplane interfaces may be used as part of a modular chassis-based system including a high speed backplane and multiple line cards. Backplane interface solutions are also known as high speed serial links and they provide full duplex communication across the high speed backplane. Data may be transmitted across a high speed differential signal that is routed across the line card, through the connector and backplane, and across another set of high density connectors.
Backplanes may be used to connect boards, including telecom switches, multi-service provisioning platforms, add/drop multiplexers, digital cross connects, storage switches, routers, embedded platforms, multiprocessor systems, and blade servers. Modularity may be possible through the addition of line cards, switch cards, and services blades, all coupled to a single high speed backplane. Operating rates of greater than one gigabit per second are typically used.
At high data rates, the connector in the interface becomes critical to the interface performance. The connector connects the backplanes to the line cards. Electrical field distortion and radiation loss of standard interface connectors may degrade the interface performance. In fact, the interface connector can cause the interface to fail even after applying advanced signaling techniques, such as de-emphasis in the transmitter buffer and equalization in the receiver buffer.
Referring to
The high speed interface connector 16 includes a gradual arc bending L-shaped grounding structure with a pin insert that reduces the return loss spikes and insertion loss dips due to the resonance, around 8 GHz in the frequency domain. The connector 16 may support differential signaling of 40 Gigabytes per second and higher with an equalization technique.
In some embodiments, the system 10 provides better performance on the high speed interface connection and, thus, improves signal quality. For some shorter backplanes, this technique may be used independently to eliminate the need for complex equalization. For longer, complex backplanes, the system 10 may be coupled with simpler equalization techniques to improve the signaling performance at lower cost in some embodiments.
The backplane or motherboard 18 includes the two backplane connectors 16, linking two line cards 20. It also includes the two chips 12, one of which may be a transmitter chip and the other may be a receiver chip.
Paired signal pins 36 and L-shaped grounding metal 34 may form the striplines included within the connector 16, as shown in
Each of the individual connectors 32 within the connector 16 may include paired signal pins 36 and L-shaped grounding metal 34. The L-shaped grounding metal 34 receives the signal pins 36. In some embodiments, the system 10 may be compatible with the Advanced Telecom Computing Architecture (ATCA) 3.0 (18 Mar. 2005) chassis developed by the PCI Industrial Computer Manufacturers Group (PICMG).
With reference to
References throughout this specification to “one embodiment” or “an embodiment” mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation encompassed within the present invention. Thus, appearances of the phrase “one embodiment” or “in an embodiment” are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be instituted in other suitable forms other than the particular embodiment illustrated and all such forms may be encompassed within the claims of the present application.
While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.
