High speed turbo codes decoder for 3G using pipelined SISO Log-Map decoders architecture

Abstract

The invention encompasses several improved Turbo Codes Decoder method and apparatus to provide a more suitable, practical and simpler method for implementation a Turbo Codes Decoder in ASIC or DSP codes. (1) Two pipelined Log-MAP decoders are used for iterative decoding of received data. (2) A Sliding Window of Block N data are used on the input Memory for pipeline operations. (3) The output block N data from the first decoder A are stored in the RAM memory A, and the second decoder B stores output data in the RAM memory B, such that in pipeline mode Decoder A decodes block N data from the RAM memory B while the Decoder B decodes block N data from the RAM memory A at the same clock cycle. (4) Log-MAP decoders are simpler to implement in ASIC and DSP codes with, only Adder circuits, and are low-power consumption. (5) Pipelined Log-MAP decoders architecture provides high speed data throughput, one output per clock cycle.

Description

BACKGROUND OF INVENTION

[0002] 1. Field of the Invention

[0003] This invention relates to Wireless Baseband Processor and Forward Error-Correction (FEC) Codes for 3G Wireless Mobile Communications; and more particularly, to a very high speed Turbo Codes Decoder using pipelined Log-MAP decoders architecture for 3G CDMA2000 and 3G WCDMA.

[0004] 2. Description of Prior Art

[0005] Turbo Codes is based upon the classic forward error correction concepts that include the use of recursive systematic constituent Encoders (RSC) and Interleaver to reduce Eb/N0 for power-limited wireless applications such as digital 3G Wireless Mobile Communications.

[0006] A Turbo Codes Decoder is an important baseband processor of the digital wireless communication Receiver, which was used to reconstruct the corrupted and noisy received data and to improve BER (10−6) throughput. The FIG. 1. shows an example of a 3G Receiver with a Turbo Codes Decoder 13 which decodes data from the Demodulator 11 and De-mapping 12 modules, and sends decoded data to the MAC layer 14.

[0007] A most widely used FEC is the Viterbi Algorithm Decoder in both wired and wireless application. The drawback is that it would requires a long waiting for decisions until the whole sequence has been received. A delay of six time the memory of the received data is required for decoding. One of the more effective FEC, with higher complexity, a MAP algorithm used to decode received message has comprised the steps of very computational complex, requiring many multiplications and additions per bit to compute the posteriori probability. The major difficulty with the use of MAP algorithm has been the implementation in semiconductor ASIC devices, the complexity the multiplications and additions which will slow down the decoding process and reducing the throughput data rates. Furthermore, even under the best conditions, each multiplication will be used in the MAP algorithm, that would create a large circuits in the ASIC. The result is costly, and low performance in bit rates throughput.

[0008] Recently introduced by the 3GPP organization a new class of error correction codes using parallel concatenated codes (PCCC) that include the use of the classic recursive systematic constituent Encoders (RSC) and Interleaver as shown in FIG. 3. offers great improvement. An example of the 3GPP Turbo Codes PCCC with 8-states and rate ⅓ is shown in FIG. 3., data enters the two systematic encoders 3133 separated by an interleaver 32. An output codeword consists of the source data bit followed by the output bits of the two encoders.

[0009] Other prior work of error correction codes was done by Berrou et al. describing a parallel concatenated codes which is much complex encoding structure which is not suitable for portable wireless device. Another patent U.S. Pat. No. 6,023,783 by Divsalar and Pollara et al. describes a more improved encoding method than Berrou and mathematical concepts of parallel concatenated codes. However, patents by Berrou et al., Divsalar et al., and others only described the concept of parallel concatenated codes using mathematical equations which are good for research in deep space communications and other government projects but are not feasible, economical, and suitable for consumers' portable wireless device. The encoding of data is simple and can be easily implemented with a few xor and flip-flop logic gates. But the decoding the Turbo Codes is much more difficult to implement in ASIC or software. The prior arts describe briefly the implementation of the Turbo Codes Decoder which are mostly for deep space communications and requires much more hardware, powers and costs.

[0010] Another prior art example of a 16-states Superorthogonal Turbo Codes (SOTC) is shown in FIG. 2. It is identical to the previous 3GPP Turbo Codes PCCC except a Walsh Code Generator substitutes for the XOR binary adder. Data enters the two systematic encoders 2123 separated by an interleaver 22. An output codeword consists of the two Walsh Codes output of the two encoders.

[0011] All the prior arts of Turbo Codes fail to provide a simpler and suitable method and architecture for a Turbo Codes Decoder as it is required and desired for 3G cellular phones and 3G personal communication devices including high speed data throughput, low power consumption, lower costs, limited bandwidth, and limited power transmitter in noisy environment.

SUMMARY OF INVENTION

[0012] The present invention concentrates only on the Turbo Codes Decoder to implement a more efficient, practical and suitable architecture and method to achieve the requirements for 3G cellular phones and 3G personal communication devices including higher speed data throughput, lower power consumptions, lower costs, and suitable for implementation in ASIC or DSP codes. The present invention encompasses improved and simplified Turbo Codes Decoder method and apparatus to deliver higher speed and lower power especially for 3G applications. As shown in FIG. 5., and FIG. 4., our invention Turbo Codes Decoder utilizes two pipelined and serially concatenated SISO Log-MAP Decoders. The two decoders function in a pipelined scheme; while the first decoder is decoding data in the second-decoder-Memory, the second decoder performs decoding data in the first-decoder-Memory, which produces a decoded output every clock cycle in results. As shown in FIG. 6., our invention Turbo Codes Decoder utilizes a Sliding Window of Block N on the input buffer memory to decode per block N data for improvement processing efficiency. Accordingly, several objects and advantages of our Turbo Codes Decoder are:

[0013] To deliver higher speed throughput and lower power consumption

[0014] To utilize SISO Log-MAP decoder for faster decoding and simplified implementation in ASIC and DSP codes with the use of binary adders for computation.

[0015] To perform re-iterative decoding of data back-and-forth between the two Log-MAP decoders in a pipelined scheme until a decision is made. In such pipelined scheme, a decoded output data is produced each clock cycle.

[0016] To utilize a Sliding Window of Block N on the input buffer memory to decode per block N data for improvement pipeline processing efficiency

[0017] To improve higher performance in term of symbol error probability and low BER (10−6)for 3G applications such as 3G W-CDMA, and 3G CDMA2000 operating at very high bit-rate up to 100 Mbps in a low power noisy environment.

[0018] To utilize an simplified and improved architecture of SISO Log-MAP decoder including branch-metric (BM) calculations module, recursive state-metric (SM) forward/backward calculations module, Add-Compare-Select (ACS) circuit, Log-MAP posteriori probability calculations module, and output decision module.

[0019] To reduce complexity of multiplier circuits in MAP algorithm by perform the entire MAP algorithm in Log Max approximation with the uses of binary adder circuits which are more suitable for ASIC and DSP codes implementation while still maintain a high level of performance output.

[0020] To design an improve Log-MAP Decoder using high level design language (HDL) such as Verilog, system-C and VHDL which can be synthesized into custom ASIC and FPGA devices.

[0021] To implement an improve Log-MAP Decoder in DSP (digital signal processor) using optimized high level language C, C++, or assembly language.

[0022] Still further objects and advantages will become apparent to one skill in the art from a consideration of the ensuing descriptions and accompanying drawings.

BRIEF DESCRIPTION OF DRAWINGS

[0023] FIG. 1. is a typical 3G Receiver Functional Block Diagram which use Turbo Codes Decoder for error-correction. (Prior Art).

[0024] FIG. 2. is an example of an 16-states Superorthogonal Turbo Code (SOTC) Encoder with Walsh code generator. (Prior Art).

[0025] FIG. 3. is a block diagram of the 8-states 3GPP Parallel Concatenated Convolutional Codes. (Prior Art).

[0026] FIG. 4. is the Turbo Codes Decoder System Block Diagram showing Log-MAP Decoders, Interleavers, Memory Buffers, and control logics.

[0027] FIG. 5. is a Turbo Codes Decoder State Diagram.

[0028] FIG. 6. is the Block N Sliding Window Diagram.

[0029] FIG. 7. is a block diagram of the SISO Log-MAP Decoder showing Branch Metric module, State Metric module, Log-MAP module, am State and Branch Memory modules.

[0030] FIG. 8 a. is the 8-States Trellis Diagram of a SISO Log-MAP Decoder using for the 3GPP 8-state PCCC Turbo codes.

[0031] FIG. 8 b. is the 16-States Trellis Diagram of a SISO Log-MAP Decoder using for the superorthogonal Turbo codes (SOTC).

[0032] FIG. 9. is a block diagram of the BRANCH METRIC COMPUTING module.

[0033] FIG. 10 a. is a block diagram of the Log-MAP computing for u=0.

[0034] FIG. 10 b. is a block diagram of the Log-MAP computing for u=1.

[0035] FIG. 11. is a block diagram of the Log-MAP Compare & Select I maximum logic for each state.

[0036] FIG. 12. is a block diagram of the Soft Decode module.

[0037] FIG. 13. is a block diagram of the Computation of Forward Recursion of State Metric module (FACS).

[0038] FIG. 14. is a block diagram of the Computation of Backward Recursion of State Metric module (BACS).

[0039] FIG. 15. showing State Metric Forward computing of Trellis state transitions.

[0040] FIG. 16. showing State Metric Backward computing of Trellis state transitions.

[0041] FIG. 17. is a block diagram of the State Machine operations of Log-MAP Decoder.

[0042] FIG. 18. is a block diagram of the BM dual-port Memory Module.

[0043] FIG. 19. is a block diagram of the SM dual-port Memory Module.

[0044] FIG. 20. is a block diagram of the De-Interleaver dual-port RAM Memory Memory Module for interleaved input R2.

[0045] FIG. 21. is a block diagram of the dual RAM Memory Module for input R0,R1.

[0046] FIG. 24. is a block diagram of the intrinsic feedback Adder of the Turbo Codes Decoder.

[0047] FIG. 23. is a block diagram of the Iterative decoding feedback control.

DETAILED DESCRIPTION

[0048] Turbo Codes Decoder

[0049] An exhibition of a 3GPP 8-state Parallel Concatenated Convolutional Code (PCCC), with coding rate ⅓, constraint length K=4, using SISO Log-MAP Decoders is provided for simplicity in descriptions of the invention. As shown in FIG. 4, a Turbo Codes Decoder has two concatenated Log-MAP SISO Decoders A 42 and B 44 connected in a feedback loop with dual-port Memory 43 and dual-port Memory 45 in between. An input interleaver Memory 41, shown in details FIG. 20, has one interleaver 201, and dual-port RAM memory 202. Input Memory blocks 4849, shown in details FIG. 21, have dual-port RAM memory 202. A control logic module (CLSM) 47, consists of various state-machines, which control all the operations of the Turbo Codes Decoder. The hard-decoder module 46 outputs the final decoded data. Signals R2, R1, R0 are the received soft decision data from the system receiver. Signal XO1, and XO2 are the output soft decision of the Log-MAP Decoders A 42 and B 44 respectively, which are stored in the buffer Memory 43 and Memory 45 module. Signal Z2 and Z1 are the output of the buffer Memory 43 and Memory 45 where the Z2 is feed into Log-MAP decoder B 44, and Z1 is feedback into an Adder 231 then into Log-MAP decoder A 42 for iterative decoding.

[0050] More particularly, the R0 is the data bit corresponding to the the transmit data bit u, R1 is the first parity bit corresponding to the output bit of the first RSC encoder, and R2 is interleaved second parity bit corresponding to the output bit of the second RSC encoder as reference to FIG. 3.

[0051] In accordance with the invention, the R0 data is added to the feedback Z1 data then feed into the decoder A, and R1 is also fed into decoder A for decoding the first stage of decoding output X01. The Z2 and R2 are fed into decoder B for decoding the second stage of decoding output X02.

[0052] In accordance with the invention, as shown in FIG. 6., the Turbo Codes Decoder utilizes a Sliding Window of Block N 61 on the input buffers 62 to decode one block N data at a time, the next block N of data is decoded after the previous block N is done in a circular wrap-around scheme for pipeline operations.

[0053] In accordance with the invention, the Turbo Codes Decoder decodes an 8-state Parallel Concatenated Convolutional Code (PCCC), and also decodes a 16-states Superorthogonal Turbo Codes SOTC with different code rates.

[0054] As shown in FIG. 4. the Turbo Codes Decoder functions effectively as follows:

[0055] Received soft decision data (RXData[2:0]) are stored in three input buffers Memory 484941 to produce R0, R1, and R2 output data words. Each output data word R0, R1, R2 contains a number of binary bits.

[0056] A Sliding Window of Block N is imposed onto each input memory to produce R0, R1, and R2 output data words.

[0057] When a block of N input data is ready, the Turbo Decoder starts the Log-MAP Decoder A to decode the N input data based on the soft-values of R0, Z1 and R1, then stores the outputs in the buffer Memory A.

[0058] The Turbo Decoder also starts the Log-MAP Decoder B at the same time to decode the N input data based on the soft-values of R2 and Z2, then store the outputs in the De-Interleaver Memory.

[0059] The Turbo Decoder will do the iterative decoding for L number of times (L=1,2, . . . M). The Log-MAP Decoder A uses the sum of Z1 and R1 and R0 as inputs. The Log-MAP Decoder B uses the data Z2 and R2 as inputs.

[0060] When the iterative decoding sequences are done, the Turbo Decoder starts the hard-decision operations to compute and produce soft-decision outputs.

[0061] SISO Log-MAP Decoder

[0062] As shown in FIG. 7., an SISO Log-MAP Decoder4244 comprises of a Branch Metric (BM) computation module 71, a State Metric (SM) computation module 72, a Log-MAP computation module 73, a BM Memory module 74, a SM Memory module 75, and a Control Logic State Machine module 76. Soft-values inputs enter the Branch Metric (BM) computation module 71, where Euclidean distance is calculated for each branch, the output branch metrics are stored in the BM Memory module 74. The State Metric (SM) computation module 72 reads branch metrics from the BM Memory 74 and compute the state metric for each state, the output state-metrics are stored in the SM Memory module 75. The Log-MAP computation module 73 reads both branch-metrics and state-metrics from BM memory 74 and SM memory 75 modules to compute the Log Maximum a Posteriori probability and produce soft-decision output. The Control Logic State-machine module 76 provides the overall operations of the decoding process.

[0063] As shown in FIG. 7. and primary example of 3GPP Turbo Codes, the Log-MAP Decoder 4244 functions effectively as follows:

[0064] The Log-MAP Decoder 4244 reads each soft-values (SD) data pair input, then computes branch-metric (BM) values for all paths in the Turbo Codes Trellis 80 as shown in FIG. 8a. (and Trellis 85 in 8b.), then stores all BM data into BM Memory 74. It repeats computing BM values for each input data until all N samples are calculated and stored in BM Memory 74.

[0065] The Log-MAP Decoder 4244 reads BM values from BM Memory 74 and SM values from SM Memory 75, and computes the forward state-metric (SM) for all states in the Trellis 80 as shown in FIG. 8a. (and Trellis 85 in 8b.), then store all forward SM data into SM Memory 75. It repeats computing forward SM values for each input data until all N samples are calculated and stored in SM Memory 75.

[0066] The Log-MAP Decoder 4244 reads BM values from BM Memory 74 and SM values from SM Memory 75, and computes the backward state-metric (SM) for all states in the Trellis 80 as shown in FIG. 8a. (and Trellis 85 in 8b.), then store all backward SM data into the SM Memory 75. It repeats computing backward SM values for each input data until all N samples are calculated and stored in SM Memory 75.

[0067] The Log-MAP Decoder 4244 then computed Log-MAP posteriori probability for u=0 and u=1 using BM values and SM values from BM Memory 74 and SM Memory 75. It repeats computing Log-MAP posteriori probability for each input data until all N samples are calculated. The Log-MAP Decoder then decodes data by making soft decision based on the posteriori probability for each stage and produce soft-decision output, until all N inputs are decoded.

[0068] Branch Metric Computation module

[0069] The Branch Metric (BM) computation module 71 computes the Euclidean distance for each branch in the 8-states Trellis 80 as shown in the FIG. 8a. based on the following equations:

Local Euclidean distances values=SD0*G0+SD1*G1

[0070] The SD0 and SD1 are soft-values input data, G0 and G1 are the expected input for each path in the Trellis 80. G0 and G1 are coded as signed antipodal values, meaning that 0 corresponds to +1 and 1 corresponds to −1. Therefore, the local Euclidean distances for each path in the Trellis 80 are computed by the following equations:

M 1 =SD0+SD1

M 2 =−M1

M3=M2

M4=M1

M 5 =−SD0+SD1

M 6 =−M5

M7=M6

M8=M5

M9=M6

M10=M5

M11=M5

M12=M6

M13=M2

M14=M1

M15=M1

M16=M2

[0071] As shown in FIG. 9., the Branch Metric Computing module comprise of one L-bit Adder 91, one L-bit Subtracter 92, and a 2′complemeter 93. It computes the Euclidean distances for path M1 and M5. Path M2 is 2′complement of path M1. Path M6 is 2′complement of M5. Path M3 is the same path M2, path M4 is the same as path M1, path M7 is the same as path M6, path M8 is the same as path M5, path M9 is the same as path M6, path M10 is the same as path M5, path M11 is the same as path M5, path M12 is the same as path M6, path M13 is the same as path M2, path M14 is the same as path M1, path M15 is the same as path M1, and path M16 is the same as path M2.

[0072] State Metric Computing Module

[0073] The State Metric Computing module 72 calculates the probability A(k) of each state transition in forward recursion and the probability B(k) in backward recursion. FIG. 13. shows the implementation of state-metric in forward recursion with Add-Compare-Select (ACS) logic, and FIG. 14. shows the implementation of state-metric in backward recursion with Add-Compare-Select (ACS) logic. The calculations are performed at each node in the Turbo Codes Trellis 80 (FIG. 8a.) in both forward and backward recursion. The FIG. 15. shows the forward state transitions in the Turbo Codes Trellis 80 (FIG. 8a.), and FIG. 16. show the backward state transitions in the Turbo Codes Trellis 80 (FIG. 8a.). Each node in the Trellis 80 as shown in FIG. 8a. has two entering paths: one-path 84 and zero-path 83 from the two nodes in the previous stage.

[0074] The ACS logic comprises of an Adder 132, an Adder 134, a Comparator 131, and a Multiplexer 133. In the forward recursion, the Adder 132 computes the sum of the branch metric and state metric in the one-path 84 from the state s(k−1) of previous stage (k−1). The Adder 134 computes the sum of the branch metric and state metric in the zero-path 83 from the state (k−1) of previous stage (k−1). The Comparator 131 compares the two sums and the Multiplexer 133 selects the larger sum for the state s (k) of current stage (k). In the backward recursion, the Adder 142 computes the sum of the branch metric and state metric in the one-path 84 from the state s(j+1) of previous stage (J+1). The Adder 144 computes the sum of the branch metric and state metric in the zero-path 83 from the state s(j+1) of previous stage (J+1). The Comparator 141 compares the two sums and the Multiplexer 143 selects the larger sum for the state s(j) of current stage (j).

[0075] The Equations for the ACS are shown below:

A (k)=MAX [(bm0+sm0(k−1)), (bm1+sm1(k−1)]

B (j)=MAX [(bm0+sm0(j+1)), (bm1+sm1(j+1)]

[0076] Time (k−1) is the previous stage of (k) in forward recursion as shown in FIG. 15., and time (j+1) is the previous stage of (j) in backward recursion as shown in FIG. 16.

[0077] Log-MAP Computing Module

[0078] The Log-MAP computing module calculates the posteriori probability for u=0 and u=1, for each path entering each state in the Turbo Codes Trellis 80 corresponding to u=0 and u=1 or referred as zero-path 83 and one-path 84. The accumulated probabilities are compared and selected the u with larger probability. The soft-decision are made based on the final probability selected for each bit. FIG. 10a. shows the implementation for calculating the posteriori probability for u=0. FIG. 10b. shows the implementation for calculate the posteriori probability for u=1. FIG. 11. shows the implementation of compare-and-select the u with larger probability. FIG. 12. shows the implementation of the soft-decode compare logic to produce output bits based on the posteriori probability of u=0 and u=1. The equations for calculation the accumulated probabilities for each state and compare-and-select are shown below:

sum—s00=sm0i+bm1+sm0j

sum—s01=sm3i+bm7+sm1j

sum—s02=sm4i+bm9+sm2j

sum—s03=sm7i+bm15+sm3j

sum—s04=sm1i+bm4+sm4j

sum—s05=sm2i+bm6+sm5j

sum—s06=sm5i+bm12+sm6j

sum—s07=sm6i+bm14+sm7j

sum—s10=sm1i+bm3+sm0j

sum—s11=sm2i+bm5+sm1j

sum—s12=sm5i+bm11+sm2j

sum—s13=sm6i+bm13+sm3j

sum—s14=sm0i+bm2+sm4j

sum—s15=sm3i+bm8+sm5j

sum—s16=sm4i+bm10+sm6j

sum—s17=sm7i+bm16+sm7j

s 00 sum=MAX[sum—s00, 0]

s 01 sum=MAX[sum—s01, s00sum]

s 02 sum=MAX[sum—s02, s01sum]

s 03 sum=MAX[sum—s03, s02sum]

s 04 sum=MAX[sum—s04, s03sum]

s 05 sum=MAX[sum—s05, s04sum]

s 06 sum=MAX[sum—s06, s05sum]

s 07 sum=MAX[sum—s07, s06sum]

s 10 sum=MAX[sum—s10, 0]

s 11 sum=MAX[sum—s11, s10sum]

s 12 sum=MAX[sum—s12, s11sum]

s 13 sum=MAX[sum—s13, s12sum]

s 14 sum=MAX[sum—s14, s13sum]

s 15 sum=MAX[sum—s15, s14sum]

s 16 sum=MAX[sum—s16, s15sum]

s 17 sum=MAX[sum—s17, s16sum]

[0079] Control Logics—State Machine (CLSM) Module

[0080] As shown in FIG. 7. the Control Logics module controls the overall operations of the Log-MAP Decoder. The control logic state machine 171, referred as CLSM, is shown in FIG. 17. The CLSM module 171 (FIG. 17.) operates effectively as the followings. Initially, it stays in IDLE state 172. When the decoder is enable, the CLSM transitions to CALC-BM state 173, it then starts the Branch Metric (BM) module operations and monitor for completion. When Branch Metric calculations are done, referred as bm-done the CLSM transitions to CALC-FWD-SM state 174, it then tarts the State Metric module (SM) in forward recursion operation. When the forward SM state metric calculations are done, referred as fwd-sm, the CLSM transitions to CALC-BWD-SM state 175, it then starts the State Metric module (SM) in backward recursion operations. When backward SM state metric calculations are done, referred as bwd-sm-done the CLSM transitions to CALC-Log-MAP state 176, it then starts the Log-MAP computation module to calculate the maximum a posteriori probability to produce soft decode output. When Log-MAP calculations are done, referred as log-map-done, it transitions back to IDLE state 172.

[0081] BM Memory and SM Memory

[0082] The Branch-Metric Memory 74 and the State-Metric Memory 75 are shown in FIG. 7. as the data storage components for BM module 71 and SM module 72. The Branch Metric Memory module is a dual-port RAM contains M-bit of N memory locations as shown in FIG. 18. The State Metric Memory module is a dual-port RAM contains K-bit of N memory locations as shown in FIG. 19. Data can be written into one port while reading at the other port.

[0083] Buffer Memory

[0084] As shown in FIG. 4., the buffer Memory A 43 stores data for the first decoder A 42, and buffer Memory B 45 stores data for the second decoder B 44. In an iterative pipelined decoding, the decoder A 42 reads data from buffer memory B 45 and writes results data into buffer memory B 43, the decoder B 44 reads data from buffer memory A 43 and write results into buffer memory B 45.

[0085] As shown in FIG. 20., the De-Interleaver memory 41 comprises of an De-Interleaver module 201 and a dual-port RAM 202 contains M-bit of N memory locations. The Interleaver is a Turbo code internal interleaver as defined by 3GPP standard ETSI TS 125 222 V3.2.1 (2000-05), or other source. The Interleaver permutes the address input port A for all write operations into dual-port RAM module. Reading data from output port B are done with normal address input.

[0086] As shown in FIG. 21., the buffer memory 4345 comprises of a dual-port RAM 212 contains M-bit of N memory locations.

[0087] Turbo Codes Decoder Control Logics—State Machine (TDCLSM)

[0088] As shown in FIG. 4. the Turbo Decoder Control Logics module 47, referred as TDCLSM, controls the overall operations of the Turbo Codes Decoder. Log-MAP A 42 starts the operations of data in Memory B 45. At the same time, Log-MAP B starts the operations in Memory A 43. When Log-MAP A 42 and Log-MAP B 44 are done for a block N data, the TDCLSM 47 starts the iterative decoding for L number of times. When the iterative decoding sequences are done, the TDCLSM 47 transitions to HARD-DEC to generate the hard-decode outputs. Then the TDCLSM 47 transitions to start decoding another block of data.

[0089] Iterative Decoding

[0090] Turbo Codes decoder performs iterative decoding L times by feeding back the output Z1 of the second Log-MAP decoder B into the first Log-MAP decoder A, before making decision for hard-decoding output. As shown in FIG. 23., the Counter 233 count the preset number L times.

Claims

1. An apparatus of turbo codes decoder used as a baseband processor subsystem for iterative decoding a plurality of sequences of received data Rn representative of coded data Xn generated by a turbo codes encoder from a source of original data un into decoded data Yn comprising of: (a) two pipelined SISO Log-MAP Decoders each decoding input data from the other output data in an iterative mode. (b) the first SISO Log-MAP Decoder A having three inputs: R0, R1 connecting from the two Input Memory modules 4849, and Z1 feeding-back from the buffer Memory B module 45 output; the output of the Adder 231 of two input values R0 and Z1 is connected to Decoder A 42; and the first Decoder output is connected to a buffer Memory A module 43. (c) the second SISO Log-MAP Decoder B having two inputs: R2 connecting from the Input Memory module 41, and Z2 connecting from the buffer Memory A module output; and the second Decoder output is connected to a buffer Memory B module 45. (d) a buffer Memory A module 43 storing decoded data from the first Log-MAP Decoder A 42, feeding data to the second Log-MAP Decoder B 44. (e) a buffer Memory B module 45 storing decoded data from the second Log-MAP Decoder B 44, feeding-back data to the first Log-MAP Decoder A 42. (f) an Adder 231 to produce a sum values of the two inputs R0 and Z1 output for the first Log-MAP Decoder A 42. (g) Three Input Buffer Memory modules 484941 storing input soft decision received data, and feeding data to the two Log-MAP Decoders. (h) a Control logic state machine 47 controlling the overall operations of the Turbo Codes Decoder. (i) a hard-decoder logic 46 producing a final decision of either logic zero 0 or logic one 1 at the end of the iterations.

2. The Decoder system of claim 1, wherein each Log-MAP decoder uses the logarithm maximum a posteriori probability algorithm. The Decoder system of claim 1, wherein each Log-MAP decoder uses the soft-input and soft-output (SISO) method maximum a posteriori probability algorithm. The Decoder system of claim 1, wherein each Log-MAP decoder uses the Log Max approximation algorithm.

3. The Decoder system of claim 1, wherein the two serially connected SISO Log-MAP Decoders each decoding input data from the other output data in pipeline mode to produce soft decoded data each clock cycle.

4. The Decoder system of claim 1, wherein the Memory modules use dual-port memory RAM. The Decoder system of claim 1, wherein the input buffer Interleaver Memory module uses an interleaver to generate the write-address sequences of the Memory core in write-mode. In read-mode, the memory core read-address are normal sequences.

5. The Decoder system of claim 1, wherein a Sliding Window of Block N is used on the input buffer Memory so that each block N data is decoded at a time one block after another in a pipeline scheme. The Decoder system of claim 1, wherein the a Sliding Window of Block N is used on the input buffer Memory in a continuous circular wrap-around scheme for pipeline operations.

6. A method for iterative decoding a plurality of sequences of received data Rn representative of coded data Xn generated by a Turbo Codes Encoder from a source of original data un into decoded data Yn comprising the steps of: (a) coupling two pipelined Log-MAP decoders serially connected, having buffer Memory A and buffer Memory B for storing decoded output and providing feedback input for the decoders. (b) applying feedback signal from the output of the buffer Memory B to the first decoder A, by adding the intrinsic values Z1 with the received signal R0 input, to generate a first decoded output XO1. (c) applying the first decoded output to the buffer Memory A, and feeding the data with the received signal R2 input into the second decoder B to generate a second decoded output XO2. (d) applying the second decoded output XO2 to the buffer Memory B and feeding back the data to the first decoder A. (e) executing operations in both Log-MAP Decoders at the same time such that each decoder use the other's output as an input in iterative decoding. (f) applying a Sliding Window of Block N on the input buffer Memory so that each block N data is decoded at a time one block after another in a pipeline scheme. (g) applying an iterative decoding on each input data for L times until a desire soft decision is achieved and a hard decode output is generated.

7. An apparatus of SISO Log-MAP Decoder for decoding a plurality of sequences of soft-input data SD0 and SD1 generated by a receiver to produce decoded soft-output data Y comprising of: (a) a Branch Metric module computing the two soft-input data SD0 and SD1 into branch metric values for each branch in the trellis. (b) a Branch Metric Memory module storing the branch metric values for each stage k=0 . . . N. (c) a State Metric module computing state metric values for each state in the trellis using branch metric values. A State Metric Computing module calculates the probability A(k) of each state transition in forward recursion and the probability B(k) in backward recursion. (d) an Add-Compare-Select (ACS) circuit to compute state metric values at each node in the Trellis. (e) a State Metric Memory module storing state metric values for each stage k=0 . . . N. (f) a Log-MAP module computing the soft decision output based on the branch metric values and state metric values using log maximum a posteriori probability algorithm. (g) a Control Logic state machine module controlling the overall operations of the Log-MAP decoder.

8. The Decoder system of claim 7, wherein the decoder uses the logarithm maximum a posteriori probability algorithm. The Decoder system of claim 7, wherein each Log-MAP decoder uses the Log Max approximation algorithm. The Decoder system of claim 7, wherein the decoder uses the soft-input and soft-output (SISO) method Log maximum a posteriori probability algorithm.

9. The Decoder system of claim 7, wherein the decoder implements state-metric in forward recursion with Add-Compare-Select (ACS). The Decoder system of claim 7, wherein the decoder implements state-metric in backward recursion with Add-Compare-Select (ACS).

10. The Decoder system of claim 7, wherein the decoder uses an 8-states Trellis state transition diagram for 3GPP PCCC Turbo Codes. The Decoder system of claim 7, wherein the decoder uses an 16-states Trellis state transition diagram for Superorthogonal Turbo Codes SOTC. The Decoder system of claim 7, wherein the decoder uses an N-states trellis state transition diagram for higher order Superorthogonal Turbo Codes SOTC.

11. The Decoder system of claim 7, wherein the the branch metric module uses a binary adder, a binary Subtracter, and two binary two-complementers logic. The Decoder system of claim 7, wherein the the state metric module uses a binary adder, a comparator, a Mux selector logic. The Decoder system of claim 7, wherein the the log-map module uses binary adders, binary maximum selectors logic. The Decoder system of claim 7, wherein the the branch metric memory module uses dual-port memory RAM. The Decoder system of claim 7, wherein the soft decoder module uses soft decision algorithm.

12. A method for Log-Map decoding a plurality of sequences of received data SD0 and SD1 generated by a receiver to produce decoded soft-output data Y comprising the steps of: (a) computing the branch metric for each input data in a block N data for the branches entering each state in the Trellis, then storing the results into the BM Memory. (b) computing the forward recursion state metric with ACS for each data in BM Memory, for a block N data, for the each state in the Trellis, then storing the results into the SM Memory. (c) computing the backward recursion state metric with ACS for each data in BM Memory, for a block N data, for the each state in the Trellis, then storing the accumulated results into the SM Memory. (d) computing the Log-Map values from each data in BM Memory and SM Memory, for a block N data, for the each state in the Trellis. (e) applying soft decision algorithm for each state and generate soft decoded outputs.

13. An apparatus of an ACS (add-compare-select) for computing a plurality of sequences of sm0, bm0, sm1, bm1 data to select max output data A comprising of: (a) an Adder0 to compute the sum of state metric sm0 and branch metric bm0 data, (b) an Adder1 to compute the sum of state metric sm1 and branch metric bm1 data, (c) a Comparator to compares the two sums, (d) and a Multiplexer selects the larger sum for the state s(k).

14. An apparatus of Super Orthogonal Turbo Codes (SOTC) Decoder used as a baseband processor subsystem for iterative decoding a plurality of sequences of received Walsh code data RWi and RW−i representative of Walsh coded data Wi and W−j generated by a Super Orthogonal Turbo Codes (SOTC) Encoder from a source of original data un into decoded data Yn comprising of: (a) two pipelined SISO Log-MAP Decoders each decoding input data from the other output data in an iterative mode. (d) a buffer Memory A module storing decoded data from the first Log-MAP Decoder A, feeding data to the second Log-MAP Decoder B. (e) a buffer Memory B module storing decoded data from the second Log-MAP Decoder B, feeding-back data to the first Log-MAP Decoder A. (f) an Adder to produce a sum values of the two inputs RWi and Z1 output for the first Log-MAP Decoder A. (g) The Input Buffer Memory modules storing input soft decision received data, and feeding data to the two Log-MAP Decoders. (h) a Control logic state machine controlling the overall operations of the Turbo Codes Decoder. (i) a hard-decoder logic producing a final decision of either logic zero 0 or logic one 1 at the end of the iterations.