Patent Application
20090323235
Embodiments related generally to semiconductor manufacturing, and to semiconductor devices and methods of fabricating a semiconductor device.
In semiconductor manufacturing bulk substrate technology, it is important to prevent in-fab plasma process charging damage on high antenna ratio nodes. This may be accomplished by adding diodes and/or gate-diode transistors. However, the present inventors have identified that it would be beneficial to provide adequate fab in process charging protection while being high-voltage compliant in order to meet reliability voltage requirements of the technology.
The inventions will be understood more fully from the detailed description given below and from the accompanying drawings of some embodiments of the inventions which, however, should not be taken to limit the inventions to the specific embodiments described, but are for explanation and understanding only.
Some embodiments of the inventions relate to a high voltage compliant apparatus for semiconductor fabrication process charging protection.
In some embodiments, semiconductor fabrication process charging protection is provided by coupling a first diode protection device to a high voltage node and coupling a second diode protection device to the first diode protection device at a second node.
In some embodiments a diode protection device is coupled to a high voltage node used in a semiconductor fabrication process, a voltage drop across the diode protection device is reduced, and semiconductor fabrication process charging protection is performed using the diode protection device.
In some embodiments, the drain of transistor 104 is coupled to the high voltage node 102. In some embodiments the gate of transistor 104 and/or source of transistor 104 is/are coupled to the lower voltage node 108. In some embodiments,
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In some embodiments, diode protection devices, gated diode protection devices and/or junction diode protection devices (for example, transistors and/or diodes) are used to provide protection of a high antenna ratio node for semiconductor fabrication induced process charging damage. NMOS diffusion may be used in conjunction with a substrate tap to assist current paths for plasma charge and to provide protection on active circuitry on a node with high antenna ratios. In some embodiments, the transistor has, for example, a gate tied to source and/or substrate taps.
In some embodiments, a transistor connected to a high voltage sees a high voltage drop between a gate and a drain of the transistor, causing reliability risk over the lifetime of the transistor. The reliability risk is gate oxide breakdown, and as a result, a high risk for circuit shorts. Therefore, in some embodiments, a circuit is implemented in which a diode protection device (for example, a gated diode protection device, a junction diode protection device, a high voltage compliant transistor, an NMOS transistor, etc.) provides process charging protection while maintaining compliancy with high voltage requirements of the process. In this manner, the risk of potential reliability concerns is dramatically reduced and/or eliminated.
In some embodiments, a drain of transistor 204 is coupled to the high voltage node 202. In some embodiments a gate of transistor 204 and/or a source of transistor 204 is/are coupled to a voltage node Vx. In some embodiments, a drain of transistor 206 is coupled to the voltage node Vx and/or to the gate and/or source of transistor 204. In some embodiments, a gate of transistor 206 and/or a source of transistor 206 is/are coupled to the lower voltage node 208. In some embodiments,
In some embodiments,
Although
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In some embodiments, stacked transistors (for example, stacked NMOS transistors) are used to avoid a large potential drop across any one transistor, thereby satisfying gate reliability requirements while providing process charging protection. In some embodiments, a stacked structure allows a voltage drop that is one half of the high voltage node in order to avoid violating gate oxide reliability limitations.
In some embodiments, a stacked structure is used so that a total current at a high voltage node is much smaller than that in a single non-high voltage compliant transistor implementation. In the single transistor implementation, a high drain-to-gate voltage drop Vdg causes reliability concerns related to the much larger value of Vdg than the technology specified and/or allowed maximum voltage value Vmax.
In some embodiments, a single oxide process is used. In some embodiments, a high voltage compliant transistor (and/or transistors) provides process charging protection, and is compliant with high voltage requirements of the process. In some embodiments, adequate fabrication in process charging protection is provided while maintaining high voltage compliancy in order to meet reliability requirements of the technology. In some embodiments, there is no sacrifice in discharge capability while still having the capability of use with a high voltage power supply (and/or high voltage ratio antenna nodes).
As discussed above, single transistor implementations suffer from gate reliability and large leakage current, resulting in more power consumption by the product. In some embodiments, a stacked arrangement is used in which diode protection devices are stacked, resulting in safer and better reliability as well as lower leakage current.
Although some embodiments have been described herein as using transistors and/or NMOS transistors, according to some embodiments these particular implementations may not be required, and any type of diode protection device may be used. For example, a diode protection device such as a gated diode protection device (and/or Gated Node Area Charging device or GNAC), a junction diode protection device (and/or a Node Area Charging device or NAC), a transistor, and/or an NMOS transistor may be used in some embodiments. In some embodiments using a junction diode protection device, for example, transistor diffusion may be used as the diode (since it's essentially an N+ to P diode). In some embodiments using a junction diode protection device simple use of an N+ to P diffusion diode may be implemented. In some embodiments using a gated diode protection device, both junction leakage Vdb (drain-to-bulk) as well as off-state leakage Vds (drain-to-source) contribute to the total leakage current from the high voltage node (or nodes). In some embodiments using a junction diode protection device only junction leakage plays a role. In some embodiments, a gated diode protection device may be used. In some embodiments, a junction diode protection device may be used (for example, in some embodiments, where the source of a last stack transistor is not at low potential).
Although some embodiments have been described in reference to particular implementations, other implementations are possible according to some embodiments. Additionally, the arrangement and/or order of circuit elements or other features illustrated in the drawings and/or described herein need not be arranged in the particular way illustrated and described. Many other arrangements are possible according to some embodiments.
In each system shown in a figure, the elements in some cases may each have a same reference number or a different reference number to suggest that the elements represented could be different and/or similar. However, an element may be flexible enough to have different implementations and work with some or all of the systems shown or described herein. The various elements shown in the figures may be the same or different. Which one is referred to as a first element and which is called a second element is arbitrary.
In the description and claims, the terms “coupled” and “connected,” along with their derivatives, may be used. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, “connected” may be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.
An algorithm is here, and generally, considered to be a self-consistent sequence of acts or operations leading to a desired result. These include physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers or the like. It should be understood, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities.
Some embodiments may be implemented in one or a combination of hardware, firmware, and software. Some embodiments may also be implemented as instructions stored on a machine-readable medium, which may be read and executed by a computing platform to perform the operations described herein. A machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium may include read only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustical or other form of propagated signals (e.g., carrier waves, infrared signals, digital signals, the interfaces that transmit and/or receive signals, etc.), and others.
An embodiment is an implementation or example of the inventions. Reference in the specification to “an embodiment,” “one embodiment,” “some embodiments,” or “other embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments, of the inventions. The various appearances “an embodiment,” “one embodiment,” or “some embodiments” are not necessarily all referring to the same embodiments.
Not all components, features, structures, characteristics, etc. described and illustrated herein need be included in a particular embodiment or embodiments. If the specification states a component, feature, structure, or characteristic “may”, “might”, “can” or “could” be included, for example, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to “a” or “an” element, that does not mean there is only one of the element. If the specification or claims refer to “an additional” element, that does not preclude there being more than one of the additional element.
Although flow diagrams and/or state diagrams may have been used herein to describe embodiments, the inventions are not limited to those diagrams or to corresponding descriptions herein. For example, flow need not move through each illustrated box or state or in exactly the same order as illustrated and described herein.
The inventions are not restricted to the particular details listed herein. Indeed, those skilled in the art having the benefit of this disclosure will appreciate that many other variations from the foregoing description and drawings may be made within the scope of the present inventions. Accordingly, it is the following claims including any amendments thereto that define the scope of the inventions.
