Patent Application
20250240000
The present disclosure relates Schmitt triggers and, more particularly, to embodiments of a Schmitt trigger with configurable hysteresis.
In fully depleted semiconductor-on-insulator processing technology platforms (e.g., fully depleted silicon-on-insulator (FDSOI) processing technology platforms) Schmitt triggers may include relatively small laterally diffused metal oxide semiconductor field effect transistors (LDMOSFETs) for reduced area consumption. However, these LDMOSFETs have a relatively low safe operating area (SOA) (e.g., a relatively low maximum gate-to-source voltage (VGSmax) limitation of, for example, 2.0V or less), making them impractical for use in high voltage input buffers of receivers (e.g., General Purpose Input Output (GPIO) receivers). Typically, modifying a Schmitt trigger so that it can accommodate high input voltages (e.g., up to 5.0V or beyond) requires additional circuitry, increasing circuit complexity and circuit area.
Disclosed herein are embodiments of circuit and, particularly, an inverting Schmitt trigger. The inverting Schmitt trigger can include a first p-channel field effect transistor (PFET) and a second PFET connected in series to a positive voltage rail. The inverting Schmitt trigger can further include a first n-channel field effect transistor (NFET) and a second NFET connected in series between a ground rail and the second PFET. In this inverting Schmitt trigger, the gates of the first PFET and the first NFET can be connected to an input node and the gates of the second PFET and the second NFET can be connected to receive different reference voltages.
In some disclosed embodiments, the inverting Schmitt trigger can include a first p-channel field effect transistor (PFET) and a second PFET connected in series to a positive voltage rail. The inverting Schmitt trigger can further include a first n-channel field effect transistor (NFET) and a second NFET connected in series between a ground rail and the second PFET. In these embodiments, the gates of the first PFET and the first NFET can be connected to an input node and the gates of the second PFET and the second NFET can be connected to receive different reference voltages that are specifically variable.
In some disclosed embodiments, the inverting Schmitt trigger can include a first p-channel field effect transistor (PFET) and a second PFET connected in series to a positive voltage rail. The inverting Schmitt trigger can further include a first n-channel field effect transistor (NFET) and a second NFET connected in series between a ground rail and the second PFET. In these embodiments, the first PFET and the first NFET can be buried oxide field effect transistors (BOXFETs) and the second PFET and the second NFET can be laterally diffused metal oxide semiconductor field effect transistors (LDMOSFETs). Furthermore, in these embodiments the gates of the first PFET and the first NFET can be connected to an input node and the gates of the second PFET and the second NFET can be connected to receive different reference voltages that are specifically variable.
It should be noted that all aspects, examples, and features of disclosed embodiments mentioned in the summary above can be combined in any technically possible way. That is, two or more aspects of any of the disclosed embodiments, including those described in this summary section, may be combined to form implementations not specifically described herein. The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features, objects and advantages will be apparent from the description and drawings, and from the claims.
The present disclosure will be better understood from the following detailed description with reference to the drawings, which are not necessarily drawn to scale and in which:
As mentioned above, in fully depleted semiconductor-on-insulator processing technology platforms (e.g., FDSOI processing technology platforms), Schmitt triggers may include relatively LDMOSFETs for reduced area consumption. However, LDMOSFETs have a relatively low safe operating area (SOA), making them impractical for use in high voltage input buffers of receivers (e.g., of GPIO receivers). Typically, modifying a Schmitt trigger so that it can accommodate high input voltages (e.g., up to 5.0V or beyond) requires additional circuitry, increasing circuit complexity and circuit area. Furthermore, hysteresis trigger voltage levels of such Schmitt triggers may vary with process-voltage-temperature (PVT) variations (also known as “corners”), negatively affecting performance (e.g., resulting in the output voltage switching earlier or later than desired).
In view of the foregoing, disclosed herein are embodiments of a compact, high-voltage, inverting Schmitt trigger (herein after referred to simply as the Schmitt trigger) where hysteresis is optionally configurable (i.e., selectively adjustable or tunable) to, for example, account for PVT variation. More particularly, in the disclosed embodiments, the Schmitt trigger can include input and output stages. The input stage can include at least four series-connected transistors: a first p-channel field effect transistor (PFET) and a second PFET connected in series to a positive voltage rail and a first n-channel field effect transistor (NFET) and a second NFET connected in series between a ground rail and the second PFET. The output stage can include additional p-channel and n-channel FETs to provide hysteresis. The first PFET and first NFET of the input stage can have a higher voltage rating than all other transistors due to different structural configurations. For example, the first PFET and first NFET can be buried oxide field effect transistors (BOXFETs) and all the other transistors in the Schmitt trigger can be LDMOSFETs. In the input stage, only the gates of the first PFET and the first NFET are connected to an input node for receiving input voltage (Vin), which can, for example, swing between ground and a high voltage (e.g., 5.0V). Gates of the second PFET and second NFET are instead connected to receive different reference voltages. These reference voltages can be preselected to: (1) avoid SOA violations in the second PFET and second NFET; and (2) to set the trigger voltages levels at which the output voltage (Vout) on an output node switches from low to high and high to low in response to changes in Vin at the input node. Optionally, these reference voltages can be variable and, particularly, selectively adjustable to control and, particularly, to fine tune the trigger voltage levels to account for PVT variations. Such a Schmitt trigger can be incorporated into a receiver (e.g., a GPIO receiver) as an inverting input buffer to facilitate down shifting of received data input signals at a data input pad to logic core voltage levels.
Input stage S1 can include an input node 191, which is electrically connected to receive a voltage input signal (Vin). Vin can, for example, be a data input signal received on a data input pad of a receiver (e.g., a GPIO receiver) and can, for example, swing between a low Vin (e.g., at ground (VSS)) indicating a low data value and a high Vin (e.g., at a positive supply voltage (VDD) in, for example, the range of 3.0 volts (V) to 5.5V, such as at 5.0V or even higher) to indicate a high data value.
Input stage (S1) can further include multiple series-connected field effect transistors. These input-stage field effect transistors can include, for example, a first p-channel field effect transistor (PFET) 110 and a second PFET 120 connected in series to a positive voltage rail 199. Specifically, a source region of a first PFET 110 can be electrically connected to a positive voltage rail 199 and a drain region of first PFET 110 can be electrically connected to a source region of a second PFET 120. Additionally, a first n-channel field effect transistor (NFET) 160 and a second NFET 150 can be connected in series between a ground rail 198 and second PFET 120. Specifically, a drain region of second NFET 150 can be electrically connected to a drain region of the second PFET 120 at a first intermediate node 11 and a source region of second NFET 150 can be electrically connected to a drain region of first NFET 160. A source region of first NFET 160 can further be electrically connected directly to ground rail 198 (as illustrated). Alternatively, the source region of first NFET 160 could be connectable to ground rail 198 via an optional footer device (not shown), which controls the on/off state of the Schmitt trigger 100.
In this input stage (S1), first PFET 110 and first NFET 160 can be a first type of FET and second PFET 120 and second NFET 150 can be a second type of FET that is different from the first type. Specifically, the first type can have a first voltage rating (e.g., a first maximum gate-to-source voltage (VGSmax) limitation) and the second type can have a second voltage rating (e.g., a second VGSmax limitation) that is lower than the first voltage rating. For example, in some embodiments, first PFET 110 and first NFET 160 can have a first VGSmax limitation that is at or higher than VDD (e.g., at or above 5.0V) and second PFET 120 and second NFET 150 can have a second VGSmax limitation that is significantly less than VDD, such as less than one-half VDD (e.g., 1.98V). Those skilled in the art will recognize that such a high voltage FET will typically be larger in size (i.e., consume more chip area) than a low voltage FET as well.
For example, in some embodiments, Schmitt trigger 100 can be implemented in an advanced semiconductor-on-insulator processing technology platform (e.g., in a fully depleted silicon-on-insulator (FDSOI) processing technology platform) with first PFET 110 and first NFET 160 being buried oxide field effect transistors (BOXFETs) with a high voltage rating (e.g., of 5.0V or higher) and with second PFET 120 and second NFET 150 being LDMOSFETs with a low voltage rating (e.g., 1.98V). See
In any case, in this input stage (S1), first PFET 110 and first NFET 160 only (i.e., not second PFET 120 or second NFET 150) can be electrically connected to input node 191 for receiving Vin. Specifically, gate 115 of first PFET 110 and gate 165 of first NFET 160 can each be electrically connected to input node 191. If the first VGSmax limitation of first PFET 110 and first NFET 160 is 5.0V and VDD is 5.0V, then even when Vin swings downward to 0.0V, these transistors will continue to operate within the SOA. Additionally, in this input stage (S1), second PFET 120 and second NFET 150 can be electrically connected to receive discrete reference voltages (Vrp1 and Vrn1) (instead of being electrically connected to input node 191). Specifically, gate 125 of second PFET 120 can be electrically connected to receive reference voltage (Vrp1) and gate 155 of second NFET 150 can be connected to receive a different reference voltage (Vrn1).
Vrp1 and Vrn1 received by input stage (S1) can be set at voltage levels preselected to avoid SOA violations in the second PFET 120 and second NFET 150. For example, in embodiments of Schmitt trigger 100 as described above, where VDD is 5.0V, where the first VGSmax limitation of first PFET 110 and first NFET 160 is 5.0V, and where the second VGSmax limitation of second PFET 120 and second NFET 150 is 1.98V, Vrp1 can be 3.2V to 4.0V and Vrn1 can be 0.9V to 1.8V to avoid SOA violations in these transistors. Furthermore, Vrp1 and Vrn1 can optionally be variable and selectively adjustable to different levels within the established SOA ranges (e.g., 3.2V to 4.0V for Vrp1 and 0.9V to 1.8V for Vrpn1) to fine tune (i.e., control) hysteresis (e.g., in order to account for PVT variations). Vrp1 and Vrn1 can be received by input stage (S1) from a reference voltage generator (not shown). Reference voltage generators capable of generating multiple variable reference voltages are well known in the art and, thus, are not shown and the details thereof are not described herein in order to allow the reader to focus on the salient aspects of the disclosed embodiments.
Output stage (S2) can include an output node 192 and at least four additional transistors. Specifically, output node 192 can be electrically connected to the first intermediate node 11 in input stage (S1) at the connection between the drain regions of second PFET 120 and second NFET 150. A third PFET 130 can be electrically connected between ground rail 198 and a second intermediate node 12 at the connection between first PFET 110 and second PFET 120. A fourth PFET 140 can be electrically connected between the gate 135 of third PFET 130 and output node 192. Similarly, a third NFET 170 can be electrically connected between positive voltage rail 199 and a third intermediate node 13 at the connection between first NFET 160 and the second NFET 150. A fourth NFET 180 can be electrically connected between the gate 175 of third NFET 170 and output node 192. Optionally, output stage (S2) could include an additional PFET (e.g., a pull-up device, not shown) connected between output node 192 and positive voltage rail 199 in order to control the on/off state of the Schmitt trigger 100.
In this output stage (S2), all of the transistors (e.g., third PFET 130, fourth PFET 140, third NFET 170 and fourth NFET 180) can be configured essentially the same as the second PFET 120 and second NFET 150 of input stage (S1). That is, these transistors can be the second type with the second voltage rating. For example, they can be LDSMOSFETs with the second VGSmax limitation of, for example, 1.98V.
Additionally, fourth PFET 140 and fourth NFET 180 can be controlled by additional reference voltages (Vrp2 and Vrn2, respectively) and can function as voltage protection devices to avoid SOA violations. Specifically, gate 145 of fourth PFET 140 can be electrically connected to receive additional reference voltage (Vrp2) and gate 185 of fourth NFET 180 can be electrically connected to receive additional reference voltage (Vrn2). Vrp2 and Vrn2 received by output stage (S2) can specifically be preselected to limit the gate voltages on third PFET 130 and third NFET 170, respectively, to prevent VGSmax violations in those transistors. Vrp2 and Vrn2 can, in turn, limit the source voltages of the third PFET 130 and third NFET 170 and, thereby the voltage level at second intermediate node 12 (between the first and second PFETs 110 and 120) and the voltage level at third intermediate node 13 (between the first NFET 160 and second NFET 150), when necessary, to assist with the prevention of VGSmax violations in the input stage S1. As with Vrp1 and Vrn1 applied to the input stage S1, Vrp2 and Vrp2 applied to output stage S2 can be received from a reference voltage generator (not shown).
As mentioned above, in input stage (S1), in addition to being preselected to avoid SOA violations, Vrp1 and Vrn1 can be preselected to control hysteresis. That is, Vrp1 and Vrn1 can also be preselected to establish the trigger voltage levels at which Vout at output node 192 switches from low to high and high to low in responses to changes in Vin at input node 191. Since the disclosed Schmitt trigger 100 is an inverting Schmitt trigger, the high trigger voltage level (VIH) refers to that point at which Vout at output node 192 switches from a high voltage level (e.g., at VDD) to a low voltage level (e.g., at ground) as Vin increases, whereas the low trigger voltage level (VIL) refers to that point at which Vout switches from the low voltage level the high voltage level as Vin decreases. Having a VIH and a VIL as opposed to one trigger voltage level (e.g., as in a conventional inverter), ensures a stable Vout in the presence of noise fluctuation at Vin. Optionally, Vrp1 and Vrn1 can also be variable and selectively adjustable to control and, particularly, fine tune the hysteresis level (e.g., to account for PVT variations).
For example,
Voltage level shifters and output stages for receivers (e.g., for GPIO receivers) are well known in the art and, thus, the details thereof have been omitted from this specification in order to allow the reader to focus on the salient aspects of the disclosed embodiments.
It should be noted that Schmitt trigger 100 of
Referring to
The chip can include, on semiconductor substrate 901, both semiconductor-on-insulator regions (e.g., silicon-on-insulator (SOI) regions) and bulk regions.
A semiconductor-on-insulator region refers to a region of the chip that includes an insulator layer 908 above and immediately adjacent to the top surface of the semiconductor substrate 901 and a monocrystalline semiconductor layer 909 above and immediately adjacent to the top surface of the insulator layer 908. Insulator layer 908 can be, for example, a silicon diode layer (also referred to herein as a buried oxide (BOX) layer). Insulator layer 908 can be relatively thick (e.g., at least 0.015 μm, >0.020 μm, etc.). Monocrystalline semiconductor layer 909 can be a monocrystalline silicon layer or a monocrystalline layer of any other suitable semiconductor material (e.g., silicon germanium, etc.). A bulk region refers to a region of the chip that is devoid of both insulator layer 908 and semiconductor layer 909 thereon.
Those skilled in the art will recognize that one advantage of such technology processing platforms is that a fully depleted semiconductor-on-insulator field effect transistor 990 (e.g., FDSOI FET) can be formed within a semiconductor-on-insulator region. Specifically, as illustrated in
In any case, the active device region can be aligned above a well region 998 within semiconductor substrate 901. For purposes of this disclosure, a well region refers to a portion of a semiconductor substrate doped so as to have either P-type conductivity (referred to as a Pwell) or N-type conductivity (referred to as an Nwell) at some desired conductivity level. The well region 998 can be either a Pwell or an Nwell, as discussed below. The threshold voltage (VT) of FDSOI FET 990 can vary depending on whether it is a PFET or an NFET and whether it is aligned above an Nwell or a Pwell. For example, for super low threshold voltage (SLVT) or low threshold voltage (LVT) FETs, NFETs can be formed above Nwells and PFETs can be formed above Pwells. For regular threshold voltage (RVT) or high threshold voltage (HVT) FETs, NFETs can be formed above Pwells and PFETs can be formed above Nwells. Typically, a circuit block (e.g., a logic core) will include all SLVT (or LVT) FETs with NFETs above Nwells and PFETs above Pwells or all RVT (or HVT) FETs with NFETs above Pwells and PFETs above Nwells. Whether the FETs are SLVT or LVT FETs or whether they are RVT or HVT FETs will depend upon the design (e.g., device size, etc.) and process specifications (e.g., dopant concentrations, etc.). Another advantage of such technology processing platforms is that back biasing (also referred to herein as back gate biasing) can be employed to fine tune the VTs (regardless of whether the FETs are SLVT/LVT or RVT/HVT FETs. This is achieved by applying different back gate bias voltages to the well region 998 aligned below the FDSOI FET 990 (e.g., via a well tap 999). As mentioned above, FDSOI FETs can be included in the logic core or other sections of a chip
Generally, in bulk regions, the chip can include well taps (also referred to herein as well contact regions) that facilitate contacting of the well regions (e.g., in the semiconductor-on-insulator areas and/or in the bulk regions). A well tap can include, for example, an epitaxially grown monocrystalline semiconductor layer (e.g., an epitaxially grown silicon layer or an epitaxially grown layer of any other suitable semiconductor material) on the top surface of semiconductor substrate 901 immediately adjacent to a well region (e.g., see well tap 999 immediately adjacent to well region 998 in
Additionally, in bulk regions, the chip can include semiconductor devices, such as LDMOSFETs.
As illustrated in
As illustrated in
As mentioned above, LDMOSFETs, such as those described above and illustrated in
As illustrated in
As illustrated in
As illustrated in
BOXFETs are advantageous because the thick gate dielectric layer allows the VGSmax limitation to be increased (e.g., to 5.0V). By using BOXFETs for the first PFET 110 and first NFET 160 in the input stage (S1) of Schmitt trigger 100 and LDMOSFETs for the other transistors within the input stage (S1) and in the output stage (S2), no additional circuitry is required within the Schmitt trigger to prevent SOA violations. Even though the BOXFETs are relatively large as compared to LDMOSFETs, no additional circuitry is required within the device to prevent SOA violations because the chip area consumed is reduced over Schmitt triggers that incorporate only LDMOSFETs or only BOXFETs.
It should be understood that in the structures and methods described above, a semiconductor material refers to a material whose conducting properties can be altered by doping with an impurity. Exemplary semiconductor materials include, for example, silicon-based semiconductor materials (e.g., silicon, silicon germanium, silicon germanium carbide, silicon carbide, etc.) and III-V compound semiconductors (i.e., compounds obtained by combining group III elements, such as aluminum (Al), gallium (Ga), or indium (In), with group V elements, such as nitrogen (N), phosphorous (P), arsenic (As) or antimony (Sb)) (e.g., GaN, InP, GaAs, or GaP). A pure semiconductor material and, more particularly, a semiconductor material that is not doped with an impurity for the purposes of increasing conductivity (i.e., an undoped semiconductor material) is referred to in the art as an intrinsic semiconductor. A semiconductor material that is doped with an impurity for the purposes of increasing conductivity (i.e., a doped semiconductor material) is referred to in the art as an extrinsic semiconductor and will be more conductive than an intrinsic semiconductor made of the same base material. That is, extrinsic silicon will be more conductive than intrinsic silicon; extrinsic silicon germanium will be more conductive than intrinsic silicon germanium; and so on. Furthermore, it should be understood that different impurities (i.e., different dopants) can be used to achieve different conductivity types (e.g., P-type conductivity and N-type conductivity) and that the dopants may vary depending upon the different semiconductor materials used. For example, a silicon-based semiconductor material (e.g., silicon, silicon germanium, etc.) is typically doped with a Group III dopant, such as boron (B) or indium (In), to achieve P-type conductivity, whereas a silicon-based semiconductor material is typically doped a Group V dopant, such as arsenic (As), phosphorous (P) or antimony (Sb), to achieve N-type conductivity. A gallium nitride (GaN)-based semiconductor material is typically doped with magnesium (Mg) to achieve P-type conductivity and with silicon (Si) or oxygen to achieve N-type conductivity. Those skilled in the art will also recognize that different conductivity levels will depend upon the relative concentration levels of the dopant(s) in a given semiconductor region.
It should be understood that the terminology used herein is for the purpose of describing the disclosed structures and methods and is not intended to be limiting. For example, as used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Additionally, as used herein, the terms “comprises,” “comprising,” “includes,” and/or “including” specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Furthermore, as used herein, terms such as “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” “upper,” “lower,” “under,” “below,” “underlying,” “over,” “overlying,” “parallel,” “perpendicular,” etc., are intended to describe relative locations as they are oriented and illustrated in the drawings (unless otherwise indicated) and terms such as “touching,” “in direct contact,” “abutting,” “directly adjacent to,” “immediately adjacent to,” etc., are intended to indicate that at least one element physically contacts another element (without other elements separating the described elements). The term “laterally” is used herein to describe the relative locations of elements and, more particularly, to indicate that an element is positioned to the side of another element as opposed to above or below the other element, as those elements are oriented and illustrated in the drawings. For example, an element that is positioned laterally adjacent to another element will be beside the other element, an element that is positioned laterally immediately adjacent to another element will be directly beside the other element, and an element that laterally surrounds another element will be adjacent to and border the outer sidewalls of the other element. The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed.
The descriptions of the various disclosed embodiments have been presented for purposes of illustration but are not intended to be exhaustive or limiting. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosed embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
