High voltage steering network for EEPROM/FLASH memory

Abstract

A circuit comprising a positive switch and a steering network. The positive switch may be configured to present a first and a second switch signal in response to a first select signal. The steering network may be configured to present a high voltage output that may transition between a very high positive and a very low negative voltage, where the transition may respond to a high positive voltage input, a low negative voltage input, a first and second switch signal, and a second select signal.

Description

FIELD OF THE INVENTION

The present invention relates to high voltage steering networks generally and, more particularly, to a high voltage steering network for use in a EEPROM/FLASH memory.

BACKGROUND OF THE INVENTION

Non-volatile memories such as EEPROM and FLASH memories generally require a variety of voltages that may be above the positive supply voltage or below the negative supply voltage. To generate the programming voltages, pump circuits may be used in a circuit where both high positive voltages and high negative voltages are required, conventional approaches often implement separate charge pumps to generate each of the separate voltages. Once generated, said separate voltages are transferred independently from each other to the different blocks of the circuit. This implies that the receiving blocks must handle both a high positive voltage signal and a high negative voltage on separate inputs. In order to do so, each receiving block may need additional local circuitry implemented on the die. Where a number of different blocks require the high positive voltage and the high negative voltage, as is the case in EEPROM/FLASH memories, additional circuitry, such as local charge pumps, may have to be duplicated on each wordline as was implemented in U.S. Pat. No. 5,311,480. The more places the high positive voltage and the low negative voltage are required, the more circuit area may be required. Were it feasible to combine said separate high positive voltage and separate high negative voltage into a single input, then the receiving blocks would only need to handle high voltage from a simple input instead of from two inputs which would significantly reduce the die area. This invention proposes a method and a circuit to combine said separate high positive voltage and separate high negative voltage onto a single output.

SUMMARY OF THE INVENTION

The present invention concerns a circuit comprising a high voltage positive switch and a steering network. The high voltage positive switch may be configured to present first and second switch signals in response to a first select signal. The steering network may be configured to present a high voltage output that may transition between a very high positive and a very low negative voltage, where the transition may respond to a high voltage positive input, a low voltage negative input, a first and second switch signal, and a second select signal.

The objects, features and advantages of the present invention include providing a circuit capable of alternately steering a very high positive voltage (e.g., VPP) or a very low negative voltage (e.g., VNN) to a single output using a very small, area-efficient steering network.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which:

FIG. 1 is a block diagram of a preferred embodiment of the present invention;

FIG. 2 is a circuit diagram of a preferred embodiment of the present invention;

FIG. 3 is a more detailed diagram of the HV positive switch of FIG. 2 ;

FIG. 4 is a timing diagram of the circuit of FIG. 1. ;

FIG. 5 is a circuit diagram of a four-phase positive pump; and

FIG. 6 is a circuit diagram of a four-phase negative pump.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIG. 1 , a block diagram of a circuit 10 illustrating a preferred embodiment of the present invention is shown. The circuit 10 generally comprises a high voltage (HV) positive switch 11 , a positive charge pump 12 , a negative charge pump 13 , and a steering network block (or circuit) 14 . The HV positive switch 11 may have an input 15 that may receive a signal (e.g., HP), an input 16 that may receive a signal (e.g., ER_S), and an input 18 that may receive a control signal (e.g., CTR). The HV positive switch 11 may have an output 20 and an output 22 that may present signals to an input 24 and an input 26 respectively of the steering network 14 . The HV positive switch 11 will be described in more detail in connection with FIG. 3 .

The steering network 14 has an input 28 that may receive the signal ER_S, an input 30 that may receive the high voltage positive signal (e.g., HP) from the positive charge pump 12 , and an input 32 that may receive a high voltage negative signal (e.g., HN) from the negative charge pump 13 and inputs 24 and 26 that may receive control signals 20 and 22 respectively from the HV positive switch. The steering network 14 may have an output 34 that may present an output signal (e.g., GLHV).

Referring to FIG. 2 , a more detailed diagram of the circuit 14 is shown. The steering network 14 is shown comprising a transistor M 1 , a transistor M 2 , a transistor M 3 , a transistor M 4 , a transistor M 5 , a transistor M 6 , a transistor Mb 5 , a transistor Mb 2 , a transistor Mb 1 , and a capacitor C 1 . The capacitor C 2 may represent the external load capacitance at the output 34 .

A high positive output may occur on the signal GLHV when the control signal CTR is at Vcc, the signal ER_S is at an intermediate high voltage between Vcc and Vpp (for example 5V) and the positive charge pump 12 delivers a high voltage Vpp at the node HP. A node Vc 1 (i.e., input 24 ) may then be at Vss and a node Vc 2 (i.e., input 26 ) may be raised to Vpp by the HV positive switch 11 in response to control signal CTR being at Vcc. Hence, the transistors M 1 and M 2 are on, which may pass a high voltage Vpp to output signal GLHV. Under such conditions, the transistors M 5 and MSb may both be on and a node DN (i.e., a node connecting the sources of the transistors Mb 5 and M 6 with the gates of the transistors M 3 and M 4 ) may be at Vpp, which generally turns off the transistors M 3 and M 4 . The transistor M 6 , may also be off, since the gate (which is connected to the node Vc 2 ) is at Vpp.

In terms of junction-breakdown issues, the transistors M 3 and M 4 may be the most vulnerable since they may be connected to the signal GLHV (which may be as high as Vpp) at one terminal (e.g., the drain), and the high voltage negative signal HN at the other terminal (e.g., the source). The voltage level of the high voltage negative signal HN may depend on how the negative charge pump 13 is implemented and how the negative charge pump 13 operates in conjunction with the positive charge pump 12 . In one example, the high voltage negative signal HN may be at −5V while the high voltage positive signal HP may be at 15.5V. With such an implementation, the overall voltage difference across the transistors M 3 and M 4 may be 20.5V which, if uncompensated, may lead to junction breakdown conditions. To overcome junction breakdowns, the transistor Mb 2 may be positioned between a node Vc 1 (i.e., a node connected to the input 24 ) and the input 28 (i.e., the signal ER_S). Since the node Vc 1 is generally at Vss under these conditions (i.e., signal CTR at Vcc), the transistor Mb 2 may be on which forces a node PB (i.e., a node between the terminals of the transistors M 3 and M 4 and the source of the transistor Mb 2 ) to a voltage level of 5V (e.g., the voltage of the signal ER_S). This may split the 20.5V difference across the junctions of the transistors M 3 and M 4 and may avoid breakdown.

A high negative voltage at the output node GLHV may occur when the control signal CTR and the signal ER_S are set at Vss before the negative pump 13 moves the node HN from Vss down to Vnn. In one example, when the node HN transitions from Vss to Vnn, the node HP may transition to roughly 8V (which may vary according to the technology process and supply voltages implemented), which may move the node Vc 1 to roughly 8V as well. This generally turns the transistors M 1 , M 2 , Mb 2 and M 5 off. Now the node Vc 2 may be at Vss which is not generally low enough to turn the transistor M 6 on, since the signal ER S is at Vss. However, the transistor M 6 may prevent the node DN from going too positive when the transistor M 5 is switched off. More specifically, as the transistor MS is turned off by the control signal CTR, the node DN is no longer anchored to the node HP and can float. The transistor M 6 may allow the node DN to float in the negative direction, but not at a voltage level higher than Vss plus a threshold voltage. Therefore, as the node HN begins to ramp down to Vnn, the node DN follows the node HN due to the coupling of the capacitance C 1 . The ramping of the node HN turns on transistors M 3 and M 4 that may transfer the negative voltage to the signal GLHV.

Symmetrically to the previous case, the junctions of the transistors M 1 and M 2 may be exposed to a very high voltage difference (e.g., HP- (-HN), or 18V). Thus, the transistor Mb 1 may be used to force the node NB (i.e., a node between the source of the transistor M 1 , the drain of the transistor M 2 and the source of the transistor Mb 1 ) to a voltage level close to Vss. This generally ensures that the voltage across M 1 and M 2 is not higher than 11V. An additional potential breakdown condition may occur when the node DN reaches Vnn (e.g., −10V) and the node HP is at 8V. In the absence of the transistor Mb 5 , this may have led to 18V across transistor MS.

The arrangements introduced in the circuit 10 are generally designed to prevent junction-breakdown problems in a circuit implemented in a technology where the breakdown voltage for high voltage transistors is limited (e.g., 12V). In different technologies or in applications where the output voltage is not so extreme, the transistors Mb 1 , Mb 2 , Mb 5 , M 3 and M 2 may be removed, making the circuit 10 much simpler and easy to layout. For example, all of the PMOS devices may be located within the same n-well.

Referring to FIG. 3 , a more detailed diagram of the HV positive switch 11 is shown generally comprising a transistor 50 , a transistor 52 , a transistor 54 , a transistor 56 , a transistor 58 , a transistor 60 , a transistor 62 , and a transistor 64 . The output 20 and the output 22 are generally complementary signals. In general, as the signal at the input 18 transitions between a zero and Vcc, the signal at the output 20 transitions between zero and Vpp. A signal ER may typically stay at a zero volts and may be taken to an intermediate high voltage when Vpp is at a very high voltage (e.g., 15V) or when junction breakdown may occur in the P transistors (e.g., the transistors 50 and 52 ).

Referring to FIG. 4 , a transient simulation is shown where the signal CTR is taken low twice in a row. As a result, the signal GLHV follows to a negative voltage of −7.7V for a Vnn of −10V. A voltage drop of 2.3V from the node HN to the signal GLHV is observed mainly due to the fact that the node DN does not generally transition more negative than the node HN plus a PMOS threshold voltage (i.e., −9.4V). Thus, the transistor M 4 cannot pass the node HN fully with −9.4V at its gate, which results in the node PB being at −8.8V. An additional 1V may be dropped through the transistor M 3 . When CTR goes high, the signal GLHV follows the node HP up to Vpp.

Referring to FIG. 5 , a circuit diagram of one example of a four-phase positive pump 102 is shown. The pump 102 comprises a capacitor C 1 , capacitor C 2 , capacitor C 3 , capacitor C 4 , capacitor C 5 , capacitor C 6 , a transistor M 1 , a transistor M 2 , a transistor M 3 , a transistor M 4 , a transistor M 5 , a transistor M 6 , a transistor M 7 , a transistor M 8 , and a transistor M 9 . The transistor M 1 has a source that may be coupled to ground. The gate of the transistor M 1 is generally coupled to the drain of the transistor M 2 , the source of the transistor M 3 and a first side of the capacitor C 2 . A second side of the capacitor C 2 is generally coupled to the input 108 b . The drain of the transistor M 1 is generally coupled to the gate of the transistor M 2 as well as to a first side of the capacitor C 1 . A second side of the capacitor C 1 is generally coupled to the input 108 c . The input 108 c is also coupled to a first side of the capacitor C 5 . The input 108 n is generally coupled to a first side of the capacitor C 3 . The input 108 b is generally coupled to a second side of the capacitor C 2 and the capacitor C 6 . The transistors M 3 , M 4 , M 5 and M 6 are generally configured in a similar fashion to the transistors M 1 and M 2 . The transistors M 7 , M 8 and M 9 generally provide output isolation.

Referring to FIG. 6 , a more detailed diagram of an example of a four-phase negative pump 104 is shown. The pump 104 generally comprises a capacitor C 13 , a capacitor C 14 , a capacitor C 15 , a capacitor C 16 , a capacitor C 17 , a capacitor C 18 , a capacitor C 19 , and a capacitor C 20 , a transistor M 15 , a transistor M 16 , a transistor M 17 , a transistor M 18 , a transistor M 19 , a transistor M 20 , a transistor M 21 , a transistor M 22 , a transistor M 23 , and a transistor M 24 . The transistors M 14 -M 22 are coupled in a similar fashion as the transistors M 1 -M 16 shown in FIG. 3 . However, the transistors M 15 -M 22 are generally P-channel transistors. Additionally, the sources of the transistors M 15 and M 16 are generally coupled to ground. The positive pump 102 and the negative pump 1904 are merely examples of pumps that may be used with the present invention. Other pumps may be implemented to meet particular design criteria.

While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.

Claims

1. A circuit comprising:a steering network configured to dynamically generate a high voltage output in response to (i) a high positive voltage input, and (ii) a low negative voltage input, wherein said high voltage output comprises either a high positive voltage level or a low negative voltage level, said steering network comprises a first breakdown transistor coupled to one of one or more first control signals through two of a plurality of transistors having respective sources and drains cascaded together between said low negative voltage input and said high positive voltage input.

2. The circuit according to claim 1, wherein said high positive voltage level is less positive than said high positive voltage input and said low negative voltage level is less negative than said low negative voltage input.

3. The circuit according to claim 1, further comprising:a high voltage positive charge pump configured to generate said high positive voltage input; and a high voltage negative charge pump configured to generate said low negative voltage input.

4. The circuit according to claim 1, wherein said steering network is further configured in response to said one or more first control signals.

5. The circuit according to claim 4, further comprising a switch configured to generate said one or more first control signals in response to a second signal.

6. The circuit according to claim 5, wherein said switch is further configured to receive said high positive voltage input.

7. The circuit according to claim 5, wherein said switch comprises a high voltage positive switch and said second signal comprises a switch control signal.

8. The circuit according to claim 1, wherein said steering network further comprises a second breakdown transistor coupled to another one of said one or more first control signals through another of said plurality of transistors.

9. A method for programming a memory, comprising the steps of:(A) initiating an operation in said memory; (B) generating a programming voltage comprising a high positive voltage or a low negative voltage in response to step (A), wherein said programming voltage is generated using a first breakdown transistor coupled to one of one or more first control signals through two of a plurality of transistors having respective sources and drains cascaded together between a low negative voltage input and a high positive voltage input; and (C) providing said programming voltage to a wordline of said memory.

10. The method according to claim 9, wherein said programming voltage is presented to a plurality of wordlines of said memory.

11. The method according to claim 31, wherein said high positive voltage level is less positive than said high positive voltage input and said low negative voltage level is less negative than said low negative voltage input.

12. The method according to claim 9, further comprising steps:(C) generating said high positive voltage input using a high voltage positive charge pump; and (D) generating said low negative voltage input using a high voltage negative charge pump.

13. A circuit comprising:a first charge pump configured to generate a high positive voltage input; a second charge pump configured to generate a low negative voltage input; a switch configured to generate first and second control signals in response to a second signal; and a steering network configured to present a high voltage output in response to (i) said high positive voltage input, (ii) said low negative voltage input, and (iii) said first and second control signals, wherein said high voltage output comprises either a high positive voltage level or a low negative voltage level, said steering network comprises a first breakdown transistor coupled to one of said one or more first control signals through two of a plurality of transistors having respective sources and drains cascaded together between said low negative voltage input and said high Positive voltage input.

14. The circuit according to claim 13, wherein said high positive voltage level is less positive than said high positive voltage input and said low negative voltage level is less negative than said low negative voltage input.

15. The method according to claim 9, wherein said step (B) further comprises:(B-2) generating said programming voltage using a second breakdown transistor coupled to another one of said one or more first control signals through another of said plurality of transistors.

16. The circuit according to claim 13, wherein said steering network further comprises a second breakdown transistor coupled to another one of said one or more first control signals through another of said plurality of transistors.