Claims
- 1. A high voltage bipolar transistor comprising:a body of silicon of a first conductivity type, having an upper surface; a base region of silicon of a second type, extending a first depth from said upper surface into the body of the first type; first and second heavily doped collector contact regions of the first type, flanking said base region and separated therefrom by shallow isolation trenches, extending a second depth from said upper surface into the silicon body; a heavily doped base contact region of the second type, wholly within the base region, and extending a third depth from said upper surface; a heavily doped emitter region of the first type, wholly within the base region, extending a fourth depth from said upper surface; shallow isolation trenches between the base and first collector contact and between the emitter and second collector contact region; and a heavily doped buried layer of the second type, having a thickness between about 2.5 and 3.5 microns and an upper interface with said body of the first type that is located between about 2.5 and 3 microns below said upper surface, and overlapping the base layer by between about 1.5 and 2.5 microns.
- 2. A process for manufacturing a high voltage bipolar transistor, comprising:providing a silicon wafer of a first conductivity type, having an upper surface; through a mask, ion implanting first ions to form a heavily doped layer of a second type extending downward from said upper surface and then heating the wafer in order to perform a drive-in diffusion; depositing, by means of epitaxial growth, a layer of silicon of the first type having a thickness between about 4 and 5 microns; forming shallow isolation trenches on said epitaxial layer which delineate the area of said high voltage transistor and provide a single base opening and two collector contact openings that underlap said buried layer of the second type; selectively implanting ions through said base opening followed by a rapid thermal anneal thereby forming a base region of the second type; by introduction of ions, forming heavily doped regions of the first type in the collector openings and, through a mask forming an emitter region within said base region; and through a mask, ion implanting ions to form a heavily doped base contact region of the second type.
Parent Case Info
This is a Continuation Application of Ser. No. 09/846,538, filing date May 2, 2001, High Voltage Transistor Using P+ Buried Layer, now U.S. Pat. No. 6,423,590 B2 which is a Divisional Application of application Ser. No. 09/405,060 filed Sep. 27, 1999 assigned to the same assignee as the present invention and now U.S. Pat. No. 6,245,609.
US Referenced Citations (15)
Foreign Referenced Citations (3)
Number |
Date |
Country |
60-109278 |
Jun 1985 |
JP |
1-196849 |
Aug 1989 |
JP |
6-349942 |
Dec 1994 |
JP |
Continuations (1)
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Number |
Date |
Country |
Parent |
09/846538 |
May 2001 |
US |
Child |
10/091990 |
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US |