High Voltage Transmit/Receive Switch With Standard BCD Process

Abstract

An analog transmit/receive switch and voltage detection circuit that do not require depletion mode devices are provided. The switch may be configured to operate in a receive mode and a protection mode. The voltage detection circuit may be coupled to the switch and may be configured to measure a potential difference between two terminals of the switch. The switch and the voltage detection circuit may not include any depletion mode devices.

Description

TECHNICAL FIELD

The present disclosure generally relates to an analog switch and voltage detection circuit that do not require depletion mode devices.

SUMMARY

According to the related art, a two terminal transmit/receive (T/R) switch may pass small analog signals with a constant low resistance value and quickly turn itself off when the presence of high voltage is detected. The switch may be connected between an ultrasound transducer and the input of a low noise, low voltage, receiver amplifier, and can protect the input against the high voltage transmit signals in ultrasound applications without the aid of any control signal and high-voltage power supplies.

A detailed block diagram of a T/R switch according to the related art is shown in FIG. 1. The basic blocks for the switch are the four-transistor butterfly (symmetrical) switch and the voltage detection circuit.

The two-terminal high voltage T/R protection switch has a constant resistance characteristic when small signals, e.g., amplitudes within approximately ±300mV, are applied. When high voltages, e.g., amplitudes larger than 2V are seen, the voltage detection circuit will pinch off one of the two depletion-mode PMOS transistors, so as to cut off the current path of the symmetrical switch. I-V characteristics of the T/R switch of FIG. 1 are shown in FIG. 2.

The switch according to the related art consists of depletion-mode high-voltage NMOS transistors and depletion-mode PMOS transistors, which are nominally on to pass a small analog signal and detect the presence of high voltage. Accordingly, although some facilities are able to fabricate these related art switches, the switches impose problems to other BCD process foundries which do not provide depletion devices of any type.

In an attempt to implement an analog switch without high voltage supplies, bootstrap and translinear loop techniques are used in the exemplary embodiment of FIG. 3. The translinear loop may regulate VGS of the symmetrical switch and matches its conductance to the transconductance of M5, given M1, M2 and M5 are matched in size.

Accordingly, the T/R switch according to one or more exemplary embodiments of the present disclosure may be able to pass small analog signal and block ±90V without high voltage supplies and without any depletion or thick oxide device, and thus is transferrable to different BCD processes.

According to an aspect of one or more exemplary embodiments, there is provided an apparatus include a switch configured to operate in a receive mode and a protection mode, and voltage detection circuit coupled to the switch that measures a potential difference between two terminals of the switch. The switch and the voltage detection circuit may not include any depletion mode devices.

The switch may be configured to automatically switch between receive and protection modes without control signals. The switch may also include first and second NMOS transistors whose source terminals are coupled together. The switch may not include any PMOS transistors.

The apparatus may also include third and further transistors configured to turn off the switch. The source terminals of the third and fourth transistors may be coupled to the source terminals of the first and second NMOS transistors, and the drain terminals of the third and fourth transistors may be coupled to the gate terminals of the first and second NMOS transistors.

The voltage detection circuit may include first and second rheostats configured to measure the potential difference between the two terminals of the switch. The gate terminal of the third transistor may be coupled to the first rheostat, and a gate terminal of the fourth transistor may be coupled to the second rheostat. The switch may be configured to switch between the receive mode and the protection mode based on a threshold voltage of the third transistor or a threshold voltage of the fourth transistor. The third and fourth transistors may be NMOS transistors. In the receive mode, the resistance of the switch may be substantially constant. In the protection mode, the switch may operate as a constant current source.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 depicts a T/R switch according to the related art.

FIG. 2 depicts the I-V characteristics of the T/R switch shown in FIG. 1.

FIG. 3 depicts an analog switch circuit using a translinear loop according to an exemplary embodiment.

FIG. 4 depicts a T/R switch according to an exemplary embodiment.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Reference will now be made in detail to the following exemplary embodiments, which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. The exemplary embodiments may be embodied in various forms without being limited to the exemplary embodiments set forth herein. Descriptions of well-known parts are omitted for clarity.

Referring to FIG. 4, an exemplary embodiment of the present disclosure is shown, which includes an analog switch and a voltage detection circuit. In general, the analog switch has two modes of operation; 1) receive mode and 2) protection mode. In the receive mode, the analog switch resistance is fairly constant due to the translinear loop technique. Distortion is minimized and only limited by the parasitic capacitances to any AC ground path that would also attenuate the signal and introduce electrical noise. In the protection mode, the combined switch protects the low voltage low noise receiver amplifier against both positive and negative high-voltage pulses, by transforming itself to a high-impedance constant current source. The DC current going through the combined switch is defined by the current mirrors M1B, M2B and M5B. The combined switch automatically switches between receive and protection modes without control signals.

A pair of low-voltage NMOS switches M6 and M7 are added to shut down the symmetrical switch M1A and M2A. Different from the previous design, no series PMOS switch is needed so the symmetrical switch M1A and M2A can be much smaller than M1 and M2 of FIG. 1 and the parasitic capacitances are also much smaller in the exemplary embodiment of FIG. 4. Apart from the way the symmetrical switch is cut off, the voltage detection circuit, which consists of M1B, M2B, R1 and R2 is similar to that of FIG. 1, except M1B and M2B, just like all other transistors in FIG. 4, are enhancement mode devices with a low-voltage gate oxide. The tipping voltage between receive and protection modes is just the threshold voltage of M6 or M7 multiplied by the rheostat ratio of R1 or R2. If the rheostats are tapped at center and the threshold voltages of M6 and M7 are 1V, then the tipping voltage will be about 4V.

The T/R switch according to the exemplary embodiment described above does not require depletion mode devices. Translinear loop and bootstrap operation realize constant on-resistance of the symmetrical switch in receive mode. Therefore, the exemplary embodiment shown in FIG. 4 may eliminate the harmonic distortion due to the signal dependent on-resistance. The voltage detection circuit of the exemplary embodiment of FIG. 4 may measure the potential difference between the two switch terminals with a pair of resistors R1 and R2. A scaled-down voltage at the rheostat tap of R1 and R2 may adjust the tipping voltage between receive and protection mode, which is only a function of the M6 or M7 threshold voltage. With such flexibility of the tipping voltage adjustment and without any depletion mode or thick gate oxide device, the T/R switch of the exemplary embodiment can be easily implemented with all nominal BCD processes.

Although the inventive concepts of the present disclosure have been described and illustrated with respect to exemplary embodiments thereof, it is not limited to the exemplary embodiments disclosed herein and modifications may be made therein without departing from the scope of the inventive concepts.

Claims

1. An apparatus comprising: a switch configured to operate in a receive mode and a protection mode; anda voltage detection circuit coupled to the switch that measures a potential difference between two terminals of the switch;wherein the switch and the voltage detection circuit do not include any depletion mode devices.

2. The apparatus of claim 1, wherein the switch is configured to automatically switch between receive and protection modes without control signals.

3. The apparatus of claim 1, wherein the switch comprises first and second NMOS transistors whose source terminals are coupled together.

4. The apparatus of claim 3, wherein the switch does not include any PMOS transistors.

5. The apparatus of claim 3, further comprising a third transistor and a fourth transistor configured to turn off the switch.

6. The apparatus of claim 5, wherein source terminals of the third and fourth transistors are coupled to the source terminals of the first and second NMOS transistors; and wherein drain terminals of the third and fourth transistors are coupled to gate terminals of the first and second NMOS transistors.

7. The apparatus of claim 6, wherein the voltage detection circuit comprises first and second rheostats configured to measure the potential difference between the two terminals of the switch; and wherein a gate terminal of the third transistor is coupled to the first rheostat, and a gate terminal of the fourth transistor is coupled to the second rheostat.

8. The apparatus of claim 7, wherein the switch is configured to switch between the receive mode and the protection mode based on a threshold voltage of the third transistor or a threshold voltage of the fourth transistor.

9. The apparatus of claim 5, wherein the third and fourth transistors are NMOS transistors.

10. The apparatus of claim 1, wherein in receive mode, the resistance of the switch is substantially constant.

11. The apparatus of claim 1, wherein in the protection mode, the switch operates as a constant current source.