Patent Application
20100301820
(1) Field of the Invention
The present invention relates to high withstand voltage semiconductor devices and current control devices using the same, and in particular to a high withstand voltage semiconductor device which repeatedly opens and closes a main current to be used especially for a switching power source device, and to a current control device using the same.
(2) Description of the Related Art
Recent years have seen strong demands for switching power source devices which achieve low power consumption during standby. Such switching power source devices include, for example, a rectification smoothing circuit, a transformer, and a body circuit including a semiconductor switching element.
In the device configured as mentioned above, power losses occur mainly in the semiconductor switching element. Accordingly, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is used as this semiconductor switching element because the MOSFET produces less switching losses than a bipolar transistor does. However, the MOSFET produces a significant conduction resistance which cannot be ignored. Accordingly, a high current that flows in the MOSFET increases losses in the whole switching power source device.
To prevent this, considering both the switching losses and conduction losses, a high withstand voltage semiconductor device has been proposed (Patent Reference: Japanese Unexamined Patent Application Publication No. 2007-115871) which functions as a MOSFET advantageous in the case of high frequency and low current while a light load is placed, for example, in a wait mode whereas it functions as an IGBT (Insulated Gate Bipolar Transistor) having a small conduction resistance and thus advantageous in the case of low frequency and high current while a heavy load is placed.
This high withstand voltage semiconductor device 500 includes three electrodes that are an emitter/source electrode 521, a gate electrode 522, and a collector/drain electrode 520.
An N-type resurf region 505 is formed on the P−-type substrate 501. In the P−-type substrate 501, a P-type base region 502 is also formed adjacent to the resurf region 505. In the P-type base region 502, an N+-type emitter/source region 504 and P+-type base contact region 503 are formed apart from the resurf region 505. Further, a gate insulation film 507 is formed to cover the P-type base region 502 at a part between the N+-type emitter/source region 504 and the resurf region 505. In the resurf region 505, an N+-type drain region 562 is formed apart from the P-type base region 502. Further in the resurf region 505, a P-type collector region 561 is formed apart from the P-type base region 502. The P-type collector region 561 and the N+-type drain region 562 are each configured with separate parts, and arranged such that the respective parts of the P-type collector region 561 and the respective parts of the N+-type drain region 562 are alternately in contact with each other in a direction vertical to the direction from the P-type collector region 561 to the N+-type emitter/source region 504.
Further, a gate electrode 522 is formed on the gate insulation film 507, and on the P−-type substrate 501, a collector/drain electrode 520 is disposed in electrical contact with both the P-type collector region 561 and the N+-type drain region 562. In addition, on the P−-type substrate 501, an emitter/source electrode 521 is formed connected to both the P+-type base contact region 503 and the N+-type emitter/source region 504. This emitter/source electrode 521 is connected to a metal layer 523 deposited on the back surface of the P−-type substrate 501. In addition, on the resurf region 505, an inter-layer film 512 is formed through a field insulation film 509.
This high withstand voltage semiconductor device 500 applies a positive bias to between the collector/drain electrode 520 and the emitter/source electrode 521, and applies a positive voltage to the gate electrode 522. This causes a current to start flowing from the N+-type drain region 562 to the emitter/source electrode 521 (MOSFET operation). When the current increases to a certain level and the potential of the resurf region 505 around the P-type collector region 561 decreases to a voltage lower than the voltage of the P-type collector region 561 by approximately 0.6 V, holes are injected from the P-type collector region 561 to transit to an IGBT operation.
A method for detecting and controlling a current flowing in the high withstand voltage semiconductor device 500 having the circuit configuration shown in
However, the high withstand voltage semiconductor device having three electrodes and the current control device using the same disclosed in Patent Reference 1 entails a problem of not being able to accurately detect the collector/drain voltage Vch for switching from a MOS operation to an IGBT operation and a corresponding collector/drain current Ich. For example, since Ich is 1 A, the high withstand voltage semiconductor device 500 shown in
Next, a description is given of a problem produced due to the inability of detecting such switch from the MOS operation to the IGBT operation. As clear from
Accordingly, in order to reduce losses throughout the period from the MOS operation to the IGBT operation to an optimum level, it is necessary to reduce drive losses using 6 V as the gate voltage during the MOS operation and reduce losses by the turned-on resistor using 12 V as the gate voltage during the IGBT operation. At this time, in order to reduce losses to an optimum level, it is a must to accurately detect the switch from the MOS operation to the IGBT operation and switch the gate voltage properly.
In view of the above-described problems, the present invention has an object to provide a high withstand voltage semiconductor device capable of accurately detecting a switch from a MOS operation to an IGBT operation, thereby achieving a low-loss drive, and provide a current control device including the high withstand voltage semiconductor device.
In order to achieve the above-described object, the high withstand voltage semiconductor device according to a first aspect of the present invention includes: a second conductive-type resurf region formed on a surface part of a first conductive-type semiconductor substrate; a first conductive-type base region formed adjacent to the resurf region in the semiconductor substrate; a second conductive-type emitter/source region formed in the base region and apart from the resurf region; a gate insulation film formed on the semiconductor substrate to cover the base region at a part between the emitter/source region and the resurf region; a second conductive-type drain region formed in the resurf region and apart from the base region; a first conductive-type collector region formed in the resurf region and apart from the base region; a gate electrode formed on the gate insulation film; a collector/drain electrode formed on the semiconductor substrate and electrically connected to both the collector region and the drain region; a back gate electrode formed on the semiconductor substrate and electrically connected to the base region; and an emitter/source electrode formed on the semiconductor substrate and electrically connected to the emitter/source region, wherein the collector region and the drain region are each configured with separate parts, and arranged such that the respective parts of the collector region and the respective parts of the drain region are alternately in contact with each other in a direction perpendicular to a direction from the collector region to the emitter/source region.
The conventional three-terminal element including a gate electrode, a collector/drain electrode, and an emitter/source electrode has a problem of being not able to separately detect an electron current and a hole current during a turned-on state.
The four-terminal element configured to additionally have a back gate electrode makes it possible to separately detect an electron current and a hole current during a turned-on state. This allows an accurate detection of a switch from a MOS operation to an IGBT operation, thereby enabling a low-loss drive.
In addition, in order to achieve the above-described object, the current control device according to a second aspect of the present invention may include: the high withstand voltage semiconductor device according to the first aspect; and a current control unit configured to control a collector/drain current according to a result of detection of a value of at least one of (i) a first current flowing into the emitter/source electrode in the collector/drain current of the high withstand voltage semiconductor device and (ii) a second current flowing into the back gate electrode in the collector/drain current.
With this, it is possible to detect either the electron current or the hole current that is generated from a corresponding one of the emitter/source electrode and the back gate electrode of the high withstand voltage semiconductor device during a turned-on state. Therefore, it is possible to achieve a current control device capable of accurately detecting a switch from a MOS operation to an IGBT operation and performing a low-loss drive.
In addition, the back gate electrode may be connected to a common electrode having a constant potential at least in the current control unit, and the current control unit may include: a first resistor element which is inserted between the emitter/source electrode and the common electrode, and is configured to detect the first current flowing into the common electrode; a first reference voltage generator circuit which generates a first reference voltage that is a potential with respect to the potential of the common electrode; a first comparator circuit which has a first input terminal connected to the emitter/source electrode and has a second input terminal connected to the first reference voltage generator circuit, and compares (i) a first voltage generated between both terminals of the first resistor element with (ii) the first reference voltage; and a current control circuit which controls the collector/drain current according to a result of the comparison made by the first comparator circuit.
According to this implementation, since the first resistor element for detecting a current is connected to the emitter/source electrode, and the back gate electrode is connected to the common electrode, the emitter/source electrode has a potential greater than the potential of the back gate electrode during a turned-on state in which a current is flowing. As a result, this implementation has an advantageous feature of having a great resistance against a so-called latch-up phenomenon compared to the conventional implementations. The latch-up phenomenon is a phenomenon in which an undesirable current flows from a base region to an emitter/source region when the base region has a potential greater than the potential of the emitter/source region by approximately 0.6 V.
In addition, the current that flows into the first resistor element is only the electron current that flows into the emitter/source electrode. On the other hand, in the case of the conventional current control device shown in
In addition, the emitter/source electrode may be connected to a common electrode having a constant potential at least in the current control unit, and the current control unit may include: a second resistor element which is inserted between the back gate electrode and the common electrode, and is configured to detect the second current flowing into the common electrode; a second reference voltage generator circuit which generates a second reference voltage that is a potential with respect to the potential of the common electrode; a second comparator circuit which has a first input terminal connected to the back gate electrode and a second input terminal connected to the second reference voltage generator circuit, and compares (i) a second voltage generated between the both terminals of the second resistor element with (ii) the second reference voltage; and a current control circuit which controls the collector/drain current according to a result of the comparison made by the second comparator circuit.
According to this implementation, since the second resistor element for detecting a current is connected to the back gate electrode, and the emitter/source electrode is connected to the common electrode, the hole current that starts flowing when the high withstand voltage semiconductor device switches from a MOS operation to an IGBT operation is connected to the back gate electrode, and is detected by the second resistor element. Accordingly, the present invention enables an accurate detection of a switch from a MOS operation to an IGBT operation although the conventional current control device shown in
In addition, the current that flows into the second resistor element is only the hole current that flows into the back gate electrode. On the other hand, in the case of the conventional current control device shown in
In addition, the current control unit may further include a resistor element for preventing a latch-up which is inserted between the emitter/source electrode and the common electrode and is configured to prevent a latch-up.
According to this implementation, since a resistor for preventing a latch-up is connected to the emitter/source electrode, it is possible to increase resistance against the so-called latch-up that is a phenomenon in which an undesirable current flows from the base region to the emitter/source region.
In addition, the current control unit may further include: a third resistor element which is inserted between the emitter/source electrode and the common electrode, and is configured to detect the first current flowing into the common electrode; a third reference voltage generator circuit which generates a third reference voltage that is a potential with respect to the potential of the common electrode; and a third comparator circuit which has a first input terminal connected to the emitter/source electrode and a second input terminal connected to the third reference voltage generator circuit, and compares (i) a third voltage generated between the both terminals of the third resistor element with (ii) the third reference voltage, wherein the current control circuit may control the collector/drain current according to a result of the comparison made by the first and third comparator circuits.
According to this implementation, a resistor for detecting a current and a comparator circuit are provided for each of the emitter/source electrode and the back gate electrode. Therefore, this implementation has an advantageous feature of being able to detect even an electron current during a MOS operation, unlike a current control device in which the second resistor element is connected only to the back gate electrode. In addition, since the third resistor element for detecting a current is connected to the emitter/source electrode, it is possible to increase resistance against the so-called latch-up that is a phenomenon in which an undesirable current flows from the base region to the emitter/source region, unlike the case where the resistor is not connected.
In addition, the current control circuit may include a gate voltage selection circuit which: increases a gate voltage value of the high withstand voltage semiconductor device according to a signal received from the second comparator circuit when the second voltage reaches or exceeds the second reference voltage; and decreases a gate voltage value of the high withstand voltage semiconductor device according to a signal received from the second comparator circuit when the second voltage reaches or falls below the second reference voltage.
According to this implementation with a gate voltage selection circuit which receives a signal from a comparator circuit, it is possible to detect a switch from a MOS operation to an IGBT operation of the high withstand voltage device, and for example, can cause the gate voltage selection circuit to switch the gate voltage of 6 V during an MOS operation to 12 V at the time of transition into an IGBT operation. Thereby, this implementation has an advantageous feature of being able to reduce gate drive losses during the MOS operation, and reduce losses in the turned-on resistor during the IGBT operation.
According to the high withstand voltage semiconductor device and the current control device using the same in the present invention, it is possible to perform an accurate detection of a switch from an MOS operation to an IGBT operation, thereby enabling a low-loss drive.
The disclosure of Japanese Patent Application No. 2009-129547 filed on May 28, 2009 including specification, drawings and claims is incorporated herein by reference in its entirety.
These and other objects, advantages and features of the invention will become apparent from the following description thereof taken in conjunction with the accompanying drawings that illustrate a specific embodiment of the invention. In the Drawings:
A high withstand voltage semiconductor device in this embodiment includes: an N-type resurf region formed on the surface part of a P-type semiconductor substrate; a P-type base region formed adjacent to the resurf region; an N-type emitter/source region formed in said base region and apart from said resurf region; a gate insulation film formed to cover the base region at a part between the emitter/source region and the resurf region; an N-type drain region and an N-type collector region formed in said resurf region and apart from said base region; a gate electrode formed on said gate insulation film; a collector/drain electrode electrically connected to both the collector region and the drain region; a back gate electrode electrically connected to the base region; and an emitter/source electrode electrically connected to the emitter/source region, wherein the collector region and the drain region are each configured with separate parts, and arranged such that the respective parts of the collector region and the respective parts of the drain region are alternately in contact with each other in the direction vertical to the direction from the collector region to the emitter/source region.
Configuring a high withstand voltage semiconductor device as a four-terminal element additionally including a back gate electrode enables the semiconductor device to separately detect an electron current and a hole current during a turned-on state. This allows the semiconductor device to accurately detect a switch from a MOS operation to an IGBT operation, and perform a low-loss drive.
An N-type resurf region 5 is formed on the surface part of a P−-type substrate 1. A P-type base region 10 is formed adjacent to the resurf region 5 in the P−-type substrate 1. In the P-type base region 10, an N+-type emitter/source region 14 and a P+-type base contact region 15 are formed apart from the resurf region 5.
Further, a gate insulation film 7 is formed to cover the P-type base region 10 at a part between the N+-type emitter/source region 14 and the resurf region 5.
In the resurf region 5, an N+-type drain region 32 is formed apart from the P-type base region 10, and P-type collector region 31 is also formed apart from the P-type base region 10. The P-type collector region 31 and the N+-type drain region 32 are each configured with separate parts, and are arranged such that the respective parts of the P-type collector region 31 and the respective parts of the N+-type drain region 32 are alternately in contact with each other in the direction vertical to the direction from the P-type collector region 31 to the N+-type emitter/source region 14.
Further, a gate electrode 90 is formed on the gate insulation film 7.
In addition, on the P−-type substrate 1, a collector/drain electrode 110 is disposed in electrical contact with both the P-type collector region 31 and an N+-type drain region 32.
In addition, on the P−-type substrate 1, an emitter/source electrode 61 is formed in contact with the N+-type emitter/source region 14.
In addition, on the P−-typesubstrate 1, a back gate electrode 62 is formed in contact with the P+-type base contact region 15. This back gate electrode 62 is either electrically connected with a metal layer 70 deposited on the back surface of the P−-type substrate 1, or connected through a later-described sense resistor.
In addition, on the resurf region 5, an inter-layer film 12 is formed through a field insulation film 9.
This high withstand voltage semiconductor device 40 applies a positive bias to between the collector/drain electrode 110 and the emitter/source electrode 61 to apply the positive voltage to the gate electrode 90, which causes a current to start flowing from the N+-type drain region 32 to the emitter/source electrode 61 (MOSFET operation).
When the current increases to a certain level (1 A in the example of
Next, a description is given of a current control device using a high withstand voltage semiconductor device 40 according to this embodiment of the present invention.
Terminal P4 is connected (grounded) to the common electrode 60 having a constant potential at least in the current control device 20, and Terminal P3 is connected (grounded) to the common electrode 60 through the sense resistor 49 which is a resistor used to detect a current.
The reference voltage generator circuit 48 is a first reference voltage generator circuit which generates a first reference voltage with respect to the voltage of the common electrode 60.
The comparator 47 is connected to Terminal P3 having a first input terminal connected to the emitter/source electrode 61 and having a second input terminal connected to the reference voltage generator circuit 48. The comparator 47 compares (i) the first voltage generated between both the terminals of the sense resistor 49 which is the first resistor element with (ii) the first reference voltage generated by the reference voltage generator circuit 48 when an electron current 46 that is the first current flows into the sense resistor 49. Here, the first current is a current that flows into the emitter/source electrode 61 among the collector/drain current of the high withstand voltage semiconductor device 40.
The gate voltage application circuit 54 controls the collector/drain current according to the result of the comparison made by the comparator circuit 47.
As for a current control method, the high withstand voltage semiconductor device 40 configured as the circuit shown in
Next, a description is given of an advantageous effect provided by the current control device 20 shown in
While the high withstand voltage semiconductor device 40 is in a turned-on state, particularly during an IGBT operation, a hole current from the P-type collector region 31 passes through the P-type base region 10 and the P+-type base contact region 15 and then flows into the back gate electrode 62. At this time, resistance components of the P-type base region 10 inevitably cause a so-called latch-up. Here, a latch-up is a phenomenon in which an undesirable current flows from the P-type base region 10 to the N+-type emitter/source region 14 when the potential of the P-type base region 10 becomes greater than the potential of the N+-type emitter/source region 14 by approximately 0.6 V.
However, the current control device 20 configured as a circuit according to this embodiment of the present invention can increase the potential of the emitter/source electrode 61 exceeding the potential of the back gate electrode 62, and thus the voltage generated by the hole current and the base resistor rarely reaches 0.6 V. Accordingly, the current control device 20 has an advantageous effect of being able to increase the resistance against the so-called latch-up exceeding the resistance of the conventional current control device shown in
In addition, a current that flows in the sense resistor 49 is only the electron current 46 that flows in Terminal P3 even when the high withstand voltage semiconductor device 40 is under execution of an IGBT operation. On the other hand, in the case of the conventional current control device shown in
The above descriptions in this embodiment have been given assuming that the high withstand voltage semiconductor device 40 is a horizontally-disposed device in which a current flows in the horizontal direction with respect to the semiconductor substrate, but it is also good to use it as a vertically-disposed device in which a current flows in the vertical direction.
In addition, in the current control device 20 shown in
Terminal P3 is connected (grounded) to the common electrode 60 having a constant potential at least in the current control device 20, and Terminal P4 is connected (grounded) to the common electrode 60 through the sense resistor 50 which is a resistor used to detect a current.
The reference voltage generator circuit 51 is a second reference voltage generator circuit which generates a second reference voltage with respect to the voltage of the common electrode 60.
The comparator circuit 52 is connected to Terminal P4 having a first input terminal connected to the back gate electrode 62 and having a second input terminal connected to the reference voltage generator circuit 51. The comparator 52 compares (i) the second voltage generated between both the terminals of the sense resistor 50 which is the second resistor element with (ii) the second reference voltage generated by the reference voltage generator circuit 51 when a hole current 45 that is the second current flows into the sense resistor 50. Here, the second current is a current that flows into the back gate electrode 62 among the collector/drain current of the high withstand voltage semiconductor device 40.
The gate voltage application circuit 54 controls the collector/drain current according to the result of the comparison made by the comparator circuit 52.
As for a current control method, the high withstand voltage semiconductor device 40 configured as the circuit shown in
Next, a description is given of an advantageous effect provided by the current control device 21 shown in
Since the sense resistor 50 is connected to Terminal P4, and Terminal P3 is connected to the common electrode 60 in the circuit configured as shown in
As an exemplary case, it is assumed that the second reference voltage generated by the reference voltage generator circuit 51 is variable within a range from 0.02 to 0.3 V inclusive, and that the sense resistor 50 has 0.2Ω. In this case, a switch from a MOS operation to an IGBT operation is detected when the second reference voltage is, for example, 0.03 V. This switch from the MOS operation to the IGBT operation is accurately detected when the high withstand voltage semiconductor device 40 causes a transition to the IGBT operation, causing a hole current 45 to start flowing into Terminal P4, and subsequently causing the voltage generated in the sense resistor 50 to reach 0.03 V, that is, causing the hole current 45 to reach 0.15 A. On the other hand, when the voltage generated in the sense resistor 50 is below 0.03 V, it is possible to detect a switch from the IGBT operation to a next MOS operation.
As described above, according to this embodiment, it is possible to accurately detect a switch from a MOS operation to an IGBT operation although such detection cannot be performed by the conventional current control device shown in
In addition, a current that flows in the sense resistor 50 is only the hole current 45 that flows in Terminal P4 even when the high withstand voltage semiconductor device 40 is under execution of an IGBT operation. On the other hand, in the case of the conventional current control device shown in
The current control device 22 according to this embodiment is structurally different from the current control device 21 according to this embodiment in having the gate voltage selection circuit 53 which receives a signal from the comparator circuit 52. Only differences are described below without repeating the same descriptions given of the current control device 21 according to Embodiment 2.
The gate voltage selection circuit 53 receives a signal from the comparator circuit 52, and increases the gate voltage value, of the high withstand voltage semiconductor device 40, which is applied to Terminal P2 when the second voltage generated in the sense resistor 50 becomes equal to or above the second reference voltage generated by the reference voltage generator circuit 51. On the other hand, when the second voltage becomes equal to or below the second reference voltage, the gate voltage selection circuit 53 capable of decreasing the gate voltage value, of the high withstand voltage semiconductor device 40, which is applied to Terminal P2.
For example, upon detection of a switch from an MOS operation to an IGBT operation of the high withstand voltage semiconductor device 40, the gate voltage selection circuit 53 can switch the gate voltages to be applied to Terminal P2 between 6 V for the MOS operation and 12 V for the IGBT operation.
Next, a detailed description is given of a switch of the gate voltages between the MOS operation and the IGBT operation.
Therefore, the use of 6 V as Vg in the MOS operation region reduces drive losses more significantly than in the case of using 12 V as Vg. In contrast, in the IGBT operation region in which Vch is greater than 2 V, the current drive capability is greatly different depending on whether Vg is 6 V or 12 V. The use of 12 V as Vg in this region reduces losses caused by a turned-on resistor more significantly than in the case of using 6 V as Vg.
As described above, in order to reduce losses to an optimum level, it is necessary to accurately detect a switch between a MOS operation and an IGBT operation, reduce drive losses using 6 V as the gate voltage during the MOS operation and reduces losses caused by the turned-on transistor using 12 V as the gate voltage during the IGBT operation.
Here, a detailed description is given below of drive losses during the MOS operation.
A gate drive loss P of the high withstand voltage semiconductor device 40 is expressed by Expression 1, and increases in relation to the squares of the gate voltage Vg.
P=½×C×Vg2×2×fosc (Expression 1)
Thus, assuming that a gate capacitance C of the high withstand voltage semiconductor device 40 is 1000 pF, and a drive frequency fosc is 100 kHz, the gate drive loss P is 14 mW when Vg is 12 V according to Expression 1. On the other hand, when the gate voltage is 6 V, the gate drive loss P is 4 mW with a loss reduction of 10 mW.
As described above, the current control device 22 in the present invention can accurately detect a switch between an MOS operation and an IGBT operation, reduce the drive losses using 6 V as the gate voltage during the MOS operation, and reduce losses caused by the turned-on resistor using 12 V as the gate voltage during the IGBT operation. Therefore, the current control device 22 can reduce losses more significantly than the current control device 21 described in Embodiment 2 does.
The current control device 23 according to this embodiment is structurally different from the current control device 22 according to Embodiment 3 in that Terminal P3 is connected (grounded) to the common electrode through the sense resistor 49 which is a resistor used to prevent a latch-up. Only differences are described below without repeating the same descriptions given of the current control device 22 according to Embodiment 3.
The sense resistor 49 for preventing a latch-up increases the potential of Terminal P3 with respect to the potential of the common electrode 60 during a turned-on state in which a current is flowing. This increases the potential of Terminal P3 during the turned-on state to a certain level exceeding the potential of Terminal P3 of the current control device 22 according to Embodiment 3 shown in
As the result, it is possible to increase a resistance against a so-called latch-up more significantly than in the case of using the current control device 22 shown in
Terminal P3 is connected (grounded) to the common electrode 60 through the sense resistor 49 which is a resistor used to detect a current, and Terminal P4 is connected (grounded) to the common electrode 60 through the sense resistor 50 which is also a resistor used to detect a current.
The reference voltage generator circuit 48 is a third reference voltage generator circuit which generates a third reference voltage with respect to the voltage of the common electrode 60.
The reference voltage generator circuit 51 is a second reference voltage generator circuit which generates a second reference voltage with respect to the voltage of the common electrode 60.
The comparator 47 is a third comparator having a first input terminal connected to Terminal P3 which is connected to the emitter/source electrode 61 and having a second input terminal connected to the reference voltage generator circuit 48. The comparator 47 compares (i) the third voltage generated between both the terminals of the sense resistor 49 which is the third resistor element with (ii) the third reference voltage generated by the reference voltage generator circuit 48 when an electron current 46 that is the first voltage flows into the sense resistor 49. Here, the first current is a current that flows into the emitter/source electrode 61 among the collector/drain current of the high withstand voltage semiconductor device 40.
The comparator circuit 52 is a second comparator having a first input terminal connected to Terminal P4 which is connected to the back gate electrode 62 and having a second input terminal connected to the reference voltage generator circuit 51. The comparator 52 compares (i) the second voltage generated between both the terminals of the sense resistor 50 which is the second resistor element with (ii) the second reference voltage generated by the reference voltage generator circuit 51 when a hole current 45 that is the second voltage flows into the sense resistor 50. Here, the second current is a current that flows into the back gate electrode 62 among the collector/drain current of the high withstand voltage semiconductor device 40.
The gate voltage application circuit 54 controls the collector/drain current according to the result of the comparison made by the comparator circuit 47.
As for a current control method, the high withstand voltage semiconductor device 40 configured as the circuit shown in
Further, the circuit configured as shown in
As a concrete example, it is assumed that the second reference voltage generated by the reference voltage generator circuit 51 is set to be 0.03 V, and that the sense resistor 50 has 0.2Ω.
When the high withstand voltage semiconductor device 40 causes a transition to the IGBT operation, the hole current 45 starts flowing into Terminal P4, and then the voltage generated in the sense resistor 50 reaches 0.03 V, that is, the flowing hole current 45 reaches 0.15 A. At this time, a detection signal 64 is outputted from the comparator circuit 52. The use of this detection signal 64 makes it possible to accurately detect a switch from a MOS operation to an IGBT operation. On the other hand, when the voltage generated in the sense resistor 50 is below 0.03 V, it is possible to detect a switch from the IGBT operation to a next MOS operation.
As described above, unlike the current control device 21 according to Embodiment 2 shown in
In addition, the sense resistor 49 connected to Terminal P3 increases the potential of Terminal P3 with respect to the potential of the common electrode 60 during a turned-on state in which a current is flowing. This increases the potential of Terminal P3 during the turned-on state to the level exceeding the potential of Terminal P3 of the current control device 21 according to Embodiment 2. In other words, in this embodiment, the emitter/source electrode 61 in the high withstand voltage semiconductor device 40 shown in
As the result, it is possible to increase a resistance against a so-called latch-up more significantly than in the case of using the current control device 21 according to Embodiment 2. The latch-up is a phenomenon in which an undesirable current flows from a P-type base region 10 to an N+-type emitter/source region 14.
The current control device 25 according to this embodiment is structurally different from the current control device 24 according to Embodiment 5 in having the gate voltage selection circuit 53 which receives a signal from the comparator circuit 52. Only differences are described below without repeating the same descriptions given of the current control device 24 according to Embodiment 5.
The gate voltage selection circuit 53 receives a signal from the comparator circuit 52, and increases the gate voltage value, of the high withstand voltage semiconductor device 40, which is applied to Terminal P2 when the second voltage generated between both the terminals of the sense resistor 50 is equal to or above the second reference voltage generated by the reference voltage generator circuit 51. On the other hand, when the second voltage is below the second reference voltage, the gate voltage selection circuit 53 is capable of decreasing the gate voltage value, of the high withstand voltage semiconductor device 40, which is applied to Terminal P2.
As described above, the current control device in the present invention can accurately detect a switch between an MOS operation and an IGBT operation, reduce the drive losses using 6 V as the gate voltage during the MOS operation, and reduce losses caused by the turned-on resistor using 12 V as the gate voltage during the IGBT operation. Therefore, the current control device 52 can reduce losses more significantly than the current control device 24 described in Embodiment 2 does.
According to the high pressure resistant semiconductor device and the current control device using the same in the present invention, it is possible to perform an accurate detection of a switch between an MOS operation and an IGBT operation, thereby enabling a low-loss drive.
It is to be noted that the high withstand voltage semiconductor devices and the current control devices using the same according to the present invention are not limited to those in the above-described embodiments. Those skilled in the art will readily appreciate that many modifications and variations of the exemplary embodiments are possible by combining arbitrary structural elements in Embodiments 1 to 6 without materially departing from the novel teachings and advantages of this invention, and that the high withstand voltage semiconductor devices and the current control devices can be installed in various devices. Accordingly, all such modifications and implementations are intended to be included within the scope of the present invention.
A current control device using a high withstand voltage semiconductor device according to the present invention is useful particularly as a component used for a switching power source device which achieves a low power consumption during standby.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2009-129547 | May 2009 | JP | national |
