Patent Application
20080055327
The invention, together with further advantages thereof, may best be understood by reference to the following description taken in conjunction with the accompanying drawings.
An invention is disclosed for improving the efficiency of FIFO buffers. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some or all of these specific details. In other instances, well known process steps have not been described in detail in order not to unnecessarily obscure the present invention.
The timing control signals and data lines between the graphics controller 106 and the display 110 are shown generally as a line 112. These may in fact be several separate address, data and control lines but are shown generally as the line 112, which may be referred to as a bus. It should be recognized that such data pathways may be represented throughout the figures as a single line. The processor 102 performs digital processing operations and communicates with the graphics controller 106 and the memory 108 over the bus 104. However, in other embodiments, the processor 102 communicates over several address, data, and control lines.
In addition to the components mentioned above and illustrated in
The processor 102 performs digital processing operations and communicates with the graphics controller 106. The processor 102 is an integrated circuit capable of executing instructions retrieved from the memory 108. These instructions provide the device 100 with functionality when executed on the processor 102. The processor 102 may also be a digital signal processor (DSP) or other processing device.
The memory 108 may be random-access memory or non-volatile memory. The memory 108 may be non-removable memory such as embedded flash memory or other EEPROM, or magnetic media. Alternatively, the memory 108 may take the form of a removable memory card such as ones widely available and sold under such trade names such as “miniSD”, “SD Card,” “Compact Flash,” and “Memory Stick.” The memory 108 may also be any other type of machine-readable removable or non-removable media. Additionally, the memory 108 may be remote from the device 100. For example, the memory 108 may be connected to the device 100 via a communications port (not shown), where a BLUETOOTH® interface or an IEEE 802.11 interface, commonly referred to as “Wi-Fi,” is included. Such an interface may connect the device 100 with a host (not shown) for transmitting data to and from the host. If the device 100 is a communications device such as a cell phone, the device 100 may include a wireless communications link to a carrier, which may then store data on machine-readable media as a service to customers, or transmit data to another cell phone or email address. Furthermore, the memory 108 may be a combination of memories. For example, it may include both a removable memory for storing media files such as music, video or image data, and a non-removable memory for storing data such as software executed by the processor 102.
The display 110 can be any form of display capable of displaying a digital image. In one embodiment, the display 110 is a liquid crystal display (LCD). In another embodiment the display 110 is a matrix of organic light-emitting diodes (OLED). Other types of displays are available or may become available that are capable of displaying an image that may be used in conjunction with the device 100.
The host I/F 202 is used to communicate between the graphics controller 106 and the other components connected to the bus 104. One of the many function of the host I/F 202 is to ensure that input and output data at different clock frequencies are properly synchronized.
The memory controller 204 responds to requests from the display pipes and retrieves pixel values stored in the memory 214. The memory controller 204 has direct access to the memory 214 which, in this embodiment, is memory dedicated to the graphics processor. The memory 214 can be of various forms of machine-readable/writeable media such DRAM, SRAM, or magnetic media. Other types of memory are available or may become available that are capable of temporarily storing data and may be used in conjunction with the graphics controller 106. In another embodiment the memory accessed by the memory controller 204 may be shared with the device 100, such as the memory 108 shown in
The main display pipe 206, the overlay display pipe 208 and the sprite display pipe 210 temporarily store pixel data for the images to be sent to the display interface 212. The display interface 212 receives pixel values from the various display pipes and outputs the resulting data to the display 110. The various display pipes work on a first-in-first-out (FIFO) basis and contain buffers so the display 110 can be refreshed with the appropriate images. The main display pipe 206 provides a buffer to store pixel data for the main display. The overlay display pipe 208 provides a buffer to store pixel data for a graphical overlay such as a wallpaper or background image. The sprite display pipe 210 provides a buffer to store pixel data for sprite images or animations. Those skilled in the art will recognize that additional or fewer display pipes can be used and the types of display pipes listed above are not meant to be inclusive. Rather, the examples used are simply representative of the type of graphics capable of benefiting from the use of display pipes. Display pipes given different names are still within the scope of this disclosure if the display pipes provide the same level of functionality.
The logic 302 sends a request for a pixel value to the memory controller 204 of
The display interface 212 communicates with the logic 302 and indicates when the display needs to be refreshed in order to extract the proper pixels from the pixel value registry 308. The logic 302 also communicates with the counter 304. The counter 304 is used to keep track of the number of times a pixel is output from the pixel value registry 308. After receiving a request to refresh the display from the display interface 212 the pixel value is retrieved and the corresponding repeater value is read. If the repeater value is greater than zero, the logic 302 pauses the fetching of the next pixel value from the memory 214 and outputs the pixel value the required number of times. The counter 304, in conjunction with the logic 302, decrements the corresponding repeater value as the pixel value is repetitively sent to the display interface 212. After decrementing the repeater value until the pixel value no longer needs to be sent, i.e. the repeater value is zero, the fetching of the next pixel value resumes. Further information of the operation of the display pipe will be disclosed in the discussion of
For example, if an image has two consecutive pixels with identical pixel values, the repeater value for the first of the consecutive identical pixels is incremented from zero to one after the second pixel value is compared to the first pixel value. Similarly, if there are three consecutive pixels of the same value, the repeater value for the first of the three consecutive pixels will be incremented to two. After finishing operation 510, the procedure returns to operation 504 and repeats as described above.
If the new pixel value is not the same as the preceding pixel value in operation 508, the procedure continues to operation 512 where the pixel data, containing the new pixel value and a corresponding repeater value, is recorded in the open register. Completion of operation 514 is followed by operation 516 where the new pixel data is designated as the preceding pixel data and then the procedure returns to operation 504 and repeats as described above.
If the repeater value indicates that the pixel value is repeated, the procedure advances to operation 608 where the logic pauses the fetching of the next pixel data. Operation 610 uses this pause to output the retrieved pixel value as many times as indicated by the corresponding stored repeater value. The counter is used to decrement the repeater value each time the pixel value is output. Alternatively, the counter could increment a temporary value until the temporary value is equal to the number of consecutive pixels represented by the repeater value. Thus, if a pixel data has a repeater value of one, the pixel will be output a total of two times and the fetching of the next pixel data will be paused once. Similarly, if the pixel data has a repeater value of two, the pixel will be output a total of three times and the fetching of the next pixel data will be paused twice to accommodate the repeater value.
After operation 610 is performed, operation 614 designates the register storing the retrieved pixel data as empty, followed by operation 616 that resumes the fetching of a next pixel data. After completing operation 616 the procedure returns to operation 602 and repeats as described above. If the repeater value indicates that the pixel value is not repeated, the procedure performs operation 612 and the pixel value is output. Next, operation 614 is performed and the registers storing the retrieved pixel data are designated as empty. Operation 614 is followed by operation 616 where the next pixel data is fetched and then the procedure returns to operation 602.
One of the many advantages of using the claimed display FIFO is the ability to efficiently use FIFO memory. The use of a repeater value requires a minimal increase in the memory allocation for each registry location. However, the minimal increase in memory is offset by the increased efficiency of the FIFO. For example, four bits of additional memory would be needed to include a repeater value that can be incremented to 16. Because 24 bits are required to store the pixel value, a total of 28 bits would be required to store the pixel value and repeater value for up to 17 identical consecutive pixels. A FIFO buffer not using repeater values would require 408 bits (24 bits/pixel value A 17 pixel values) to store the data for the same 17 identical consecutive pixels. Thus, a display FIFO using repeater values saves 380 bits as compared to a display FIFO that does not use repeater values. Therefore, despite the minimal increase in memory allocation to record the repeater value, the improved efficiency of the claimed invention may allow less total memory to be allotted to FIFO buffers of the graphics controller 106 without degrading the ability of the graphics controller 106 to process images. Alternatively, using the claimed FIFO buffer may enable a graphics controller to handle more complex images than a regular display FIFO when each type of graphics controller has the same allocation of memory.
Although the foregoing invention has been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims.
