Highly energy-efficient processor employing dynamic voltage scaling

Abstract

Provided is a highly energy-efficient processor architecture. The architecture employs 2-stage dynamic voltage scaling (DVS) and a sleep mode for high energy efficiency, dynamically controls the power supply voltage and activation of an embedded processor with instructions, and thus can prevent performance deterioration while reducing power consumption.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present invention will become more apparent to those of ordinary skill in the art by describing in detail preferred exemplary embodiments thereof with reference to the attached drawings in which:

FIG. 1 is a block diagram of a conventional single instruction multiple data (SIMD) structure of an embedded processor using a single power supply voltage;

FIG. 2 is a block diagram of a conventional embedded processor using multiple power supply voltages;

FIG. 3 is a block diagram of a highly energy-efficient processor employing 2-stage dynamic voltage scaling (DVS) and a sleep mode according to an exemplary embodiment of the present invention;

FIG. 4 is a detailed block diagram showing the internal structure of a function unit block shown in FIG. 3;

FIG. 5 is a detailed block diagram showing the internal structure of a peripheral unit block shown in FIG. 3;

FIG. 6 is a block diagram showing a parallel processing structure of N×M number of unit processors employing the 2-stage DVS and sleep mode according to an exemplary embodiment of the present invention;

FIG. 7 is a block diagram showing a structure of each unit processor for parallel processing configuring the parallel processing structure shown in FIG. 6; and

FIG. 8 is a block diagram showing a structure of an N×M parallel processor employing 2-stage DVS and a sleep mode according to another exemplary embodiment of the present invention.

Claims

1. A processor comprising: a function unit block for performing an operation according to instructions input from outside;at least one peripheral unit block for performing data communication with an external device;an instruction decoder for interpreting the input instructions and determining operation modes of the function unit block and the peripheral unit block required for executing the interpreted instructions;a function unit block driver for applying a different power supply voltage according to the operation mode of the function unit block to the function unit block; anda peripheral unit block driver for applying a different power supply voltage according to the operation mode of the peripheral unit block to the peripheral unit block.

2. The processor of claim 1, wherein the function unit block comprises at least two function units.

3. The processor of claim 2, wherein the function unit block further comprises at least two function unit drivers each for applying a different power supply voltage according to control of the instruction interpreter to each function unit.

4. The processor of claim 1, wherein the peripheral unit block comprises at least two peripheral units.

5. The processor of claim 4, wherein the peripheral unit block further comprises at least two peripheral unit drivers each for applying a different power supply voltage according to control of the instruction interpreter to each peripheral unit.

6. A processor comprising: a processing element including an instruction interpreter for receiving and interpreting instructions input from outside; andan element driver for supplying the processing element with a power supply voltage,wherein a level of the power supply voltage output from the element driver is determined according to the interpretation result of the instruction interpreter with respect to the received instructions.

7. The processor of claim 6, wherein the instruction interpreter determines an operation mode of the processing element to be a sleep mode according to the received instructions.

8. The processor of claim 6, wherein the processing element further comprises one of: a function unit for being supplied with the power supply voltage from the element driver and performing an operation according to the instructions; andat least one peripheral unit for being supplied with the power supply voltage from the element driver and performing data communication with an external device.

9. A parallel processor comprising: at least two unit processors each including a processing element performing an operation or data transfer according to instructions input from outside, and an element driver for supplying the processing element with a power supply voltage; anda processing element selector interpreting the instructions and determining a unit processor required for processing the instructions,wherein the element driver supplies a different power supply voltage according to the determination of the processing element selector.

10. The parallel processor of claim 9, wherein the processing element further comprises one of: a function unit for being supplied with the power supply voltage from the element driver and performing the operation according to the instructions; andat least one peripheral unit for being supplied with the power supply voltage from the element driver and performing data communication with an external device.