NSF Award
9260320
This proposal will explore a novel approach to achieving high performance analog to digital conversion through the use of very efficient low speed ADCs (Analog-to-Digital Converters) operating in parallel. On chip circuitry can accommodate turnable prefiltering to band limit the signal to be digitized. Preamplification and/or demultiplexing make the proposed device ideal for low-level multichannel signal acquisition from grid array sensors in the field of biology and optical sensing. The approach relies on combining hundreds of channels of single- slope ADCs in a single IC. Numerous ICs are stacked in a 3-D configuration described in the proposal. The number of ICs per stack is a variable, dependent on the application and conversion bandwidth desired. Simple stacks can contain greater than 1000 ADC channels operating in parallel. Even greater parallelism can be obtained by assembling the stacks on a substrate so that greater than 10,000 single-slope ADCs can be made to operate in parallel in a package approximately 2 cubic inches. The proposed Phase I program will focus on specification generation, architecture development, and preliminary packaging design in order to determine feasibility of producing a prototype in Phase II.
