The present disclosure relates to a highly parallel processing system and method. In particular, the present disclosure relates to a highly parallel processing system and method to perform heavy computational intensive graphics and modeling processes in real-time.
Computer vision has become an important part of today's society. For example, computer vision supports crucial applications in medical, manufacturing, military intelligence, surveillance as well as other domains. Computer vision tasks can be divided into fundamental steps, such as image acquisition, pre-processing, feature extraction, detection or segmentation and high-level processing. Various computer vision tasks, such as classification, objection detection, 3D computer graphics and modeling tasks, require computationally intensive algorithms or processes.
However, the processing of heavy intensive computational computer vision tasks by conventional processing systems is ineffective. For example, it is difficult for conventional processing systems to perform classification, objection detection, 3D computer graphics and modeling processes in real-time. This hinders the performance or effectiveness of computer vision applications.
From the foregoing discussion, it is desirable to provide a high-performance processing system for computer vision or graphics applications.
Embodiments of the present disclosure generally relate to high parallel processing systems and methods. In particular, embodiments relate to highly parallel processing systems and methods to perform heavy computational intensive graphics and modeling processes in real-time.
In one embodiment, a highly parallel processing system is disclosed. The processing system includes a central processing unit which is configured to run an application. The processing system includes a highly parallel processing unit which includes an array of at least hundreds of parallel processing cores and libraries of graphics codes written in a low-level programming language. The central processing unit calls the highly parallel processing unit to execute highly computational intensive tasks of the application in parallel.
In another embodiment, a method for highly parallel processing of a software application is disclosed. The method includes running the software application by a central processing unit. The central processing unit calls a highly parallel processing unit having an array of at least hundreds of parallel processing cores and libraries of graphics codes written in a low-level programming language for executing the highly intensive computational tasks of the software application in parallel by the numerous processing cores using the graphics codes. The highly parallel processing unit returns the results of the highly intensive computational tasks to the central processing unit.
These and other objects, along with advantages and features of the present embodiments herein disclosed, will become apparent through reference to the following description and the accompanying drawings. Furthermore, it is to be understood that the features of the various embodiments described herein are not mutually exclusive and can exist in various combinations and permutations.
In the drawings, like reference characters generally refer to the same parts throughout the different views. Also, the drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various embodiments of the present disclosure are described with reference to the following drawings, in which:
Embodiments described herein generally relate to highly parallel processing systems. For example, embodiments relate to high-speed processing architectures. Highly parallel processing systems are particularly useful for processing computer vision and 3D graphics applications which include graphics, including 3D graphics.
In one embodiment, the highly parallel processing system includes a highly parallel processing unit (HPPU) 120. The HPPU, in one embodiment, is a graphics processing unit (GPU). Other types of HPPUs may also be useful. The HPPU, for example, may be an application specific integrated circuit (ASIC) or field programmable gate array (FPGA) based processing unit. HPPUs may also include, for example, Tensor Processing Units (TPUs), Neural Processing Units (NPUs) as well as other types of massively parallel processing units in the form of software and chipsets.
In one embodiment, the GPU includes an array 130 of hundreds to thousands of processing cores 135, such as Compute Unified Device Architecture (CUDA) cores 135. Graphics codes or routines 140 are provided within the framework of the GPU. For example, the GPU framework includes libraries of graphics codes. The graphics codes are employed for various heavy intensive computational computer vision tasks, including classification, objection detection, 3D computer graphics and modeling tasks. In one embodiment, the graphics codes are written in a low-level programming language. For example, the low-level graphics routines are written using native APIs, such as Vulkan. Other low-level programming languages may also be employed, depending on, for example, the type of HPPU. The codes are processed across thousands of parallel cores.
The CPU, when it encounters heavy computational tasks while running the high-level App, invokes the GPU. For example, the CPU makes calls to the GPU, invoking the codes for parallel processing of the tasks across the thousands of cores. When the tasks are completed, the GPU returns the results to the CPU.
As described, the HPPU enables massively parallel applications to be created. For example, utilizing high-performance codes written in a low-level programming language, the tasks are accelerated by thousands of parallel threads running on cores. As such, execution of computation—and bandwidth-hungry graphics applications is accelerated with the present highly parallel processing system. The highly parallel processing system with the libraries and frameworks of codes underpin the ongoing revolution in artificial intelligence known as Deep Learning.
The inventive concept of the present disclosure may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The foregoing embodiments, therefore, are to be considered in all respects illustrative rather than limiting the invention described herein.
The present disclosure claims the benefit of US Provisional Applications with serial numbers 63/111,094, 63/111,095, 63/111,097, 63/111,098, 63/111,096, 63/111,102, and 63/111,101, which are all filed on Nov. 09, 2020. All disclosures are herein incorporated by reference in their entireties for all purposes.
Number | Date | Country | |
---|---|---|---|
63111094 | Nov 2020 | US | |
63111095 | Nov 2020 | US | |
63111097 | Nov 2020 | US | |
63111098 | Nov 2020 | US | |
63111096 | Nov 2020 | US | |
63111102 | Nov 2020 | US | |
63111101 | Nov 2020 | US |