Patent Application
20130051101
The present invention relates to the field of electronic technologies, and in particular, to a hold-up time circuit, a hold-up time method and a power supply system.
With the continuing development of a power supply service, a requirement of a product for continuous stability of the power supply becomes higher and higher. In particular, when an input grid voltage is decreased abnormally, a system needs to rapidly report and store a system running state and an abnormal case of the grid voltage and to be switched to a backup power supply power supply manner, within hold-up time. Therefore, in order to achieve a hold-up time purpose, it is required to set a hold-up time circuit in a power supply system, and required to prolong the hold-up time as much as possible.
In the prior art, the hold-up time is prolonged usually by using a boost topology. When an input voltage V1 is normal, the input voltage charges an energy storage capacitor C through a current limiting resistor to store energy. When the input voltage is power-off, the energy storage capacitor implements hold-up time in dependence on its own discharging. When the energy storage voltage is close to an under-voltage point V2 of an output load after the discharging, a step-up circuit starts to work, boosts the voltage of the energy storage capacitor, and then supplies power to the load. When the energy storage voltage is lowered to a minimum voltage V3 that can be adjusted by the step-up circuit, the hold-up time circuit stops working. It can be known that, the hold-up time T that can be achieved by the solution of the prior art is:
P0 is the power of the output load, and η is the efficiency of the output load.
In the implementation of the present invention, the inventors find that the prior art has at least the following problems. A capacitor itself has a derating limitation for a capacitor voltage-resistant value, so when an input voltage has a wide range, a high voltage-resistant value and a limited layout space have become a bottleneck for selecting a capacitor having a large capacity. Therefore, a difficulty occurs, in the selection of a type of a capacitor. Moreover, when a low voltage is input, a long power-off protecting time cannot be achieved.
Embodiments of the present invention provide a hold-up time circuit, a hold-up time method, and a power supply, system, so as to achieve a long power-off protecting time when a low voltage is input.
An embodiment of the present invention provides a hold-up time circuit, which includes an energy storage capacitor, a step-down circuit and a step-up circuit.
A first input end and a second input end of the step-down circuit are separately connected to two electrodes of an input power supply. A first output end and a second output end of the step-down circuit are respectively connected to two electrodes of the energy storage capacitor. When the input power supply is normal, the step-down circuit is configured to perform reduction processing on an input voltage of the input power supply, and an output of the step-down circuit charges the energy storage capacitor.
A first input end and a second input end of the step-up circuit are separately connected to the two electrodes of the energy storage capacitor. When the input power supply is power-off, the step-up circuit is configured to perform boost processing on an energy storage voltage of the energy storage capacitor.
The energy storage capacitor is configured to: when the input power supply is normal, finish a charging process through an input voltage that has undergone reduction processing, and when the input power supply is power-off, supply power to an output load through the energy storage voltage that has undergone boost processing.
An embodiment of the present invention provides a hold-up time method, which includes:
when an input power supply is normal, charging an energy storage voltage of an energy storage capacitor through an input voltage has undergone reduction processing; and
when the input power supply is power-off, supplying power to an output load through an energy storage voltage that has undergone boost processing.
An embodiment of the present invention provides a power supply system, which includes an input power supply, a load circuit and the aforementioned hold-up time circuit.
It can be seen that, in the hold-up time circuit, the hold-up time method and the power supply system in the embodiments of the present invention, when the input power supply is normal, the energy storage capacitor is charged through an input voltage has undergone reduction processing, and when the input power supply is power-off, hold-up time processing is performed on an output load through an energy storage voltage of an energy storage capacitor, where the energy storage voltage has undergone boost processing. In other words, in the embodiments of the present invention, a manufacturing characteristic of a capacitor is used, and under a requirement for the same volume, the capacity of a capacitor having a low voltage-resistant value is far higher than the capacity of a capacitor having a high voltage-resistant value. The embodiments of the present invention implement the selection of a low-voltage capacitor by performing reduction processing on an input voltage, so as to assure that the selection of a capacitor having a large capacity is implemented in a low voltage. Thereby, the maximum energy storage in a low voltage is implemented. During the power-off, the energy stored in the capacitor having a large capacity performs a boost action on the energy storage capacitor through a step-up circuit, so as to achieve long hold-up time. However, in the prior art, if a high voltage is input, the selection range of a capacitor is narrow (which is limited by a high voltage-resistant value and a limited layout space). That is, a capacitor having a large volume and a large capacity cannot be used. Therefore, the long hold-up time cannot be achieved. On the contrary, if a low voltage is input, the selection range of a capacitor is wide, and may include a capacitor having a large volume and a large capacity. However, the input voltage is close to an under-voltage point of a load, so the long hold-up time cannot be achieved either. It can be seen that, compared with the prior art, the method provided in this embodiment avoids the problem in the prior art that it is difficult to select a capacitor for an input voltage having a wide range. In the embodiments of the present invention, the selection of a capacitor having a low voltage-resistant value and a large capacity is implemented by performing reduction processing on an input voltage. Then the step-up circuit boosts the capacitor, which achieves a long power-off protecting time when a low voltage is input in a condition that the input voltage has a wide range.
In order to more clearly describe technical solutions according to the embodiments of the present invention and in the prior art, accompanying drawings which may be used in the description of the embodiments of the present invention or the prior art have been briefly introduced in the following. Apparently, the accompanying drawings described in the following are merely some embodiments of the present invention, and persons of ordinary skill in the art may obtain other accompanying drawings according to the accompanying drawings without any creative effort.
In order to make the objectives, technical solutions, and advantages of embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings. Apparently, the embodiments in the following description are merely a part rather than all of the embodiments of the present invention. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.
A first input end and a second input end of the step-down circuit 103 are separately connected to two electrodes of an input power supply 101. Moreover, a first output end and a second output end of the step-down circuit 103 are separately connected to two electrodes of the energy storage capacitor 102. The step-down circuit 103 is configured to perform reduction processing on an input voltage of the input power supply 101 when the input power supply 101 is normal. An output of the step-down circuit 103 is used to charge the energy storage capacitor 102.
A first input end and a second input end of the step-up circuit 104 are separately connected to the two electrodes of the energy storage capacitor 102. The step-up circuit 104 is configured to perform boost processing on an energy storage voltage of the energy storage capacitor 102 when the input power supply 101 is power-off.
The energy storage capacitor 102 is configured to: when the input power supply 101 is normal, finish a charging process through an input voltage that has undergone reduction processing, and when the input power supply 101 is power-off, supply power to an output load 105 through the energy storage voltage that has under gone boost processing.
It can be seen that, this embodiment provides a hold-up time circuit, which includes an energy storage capacitor, a step-down circuit and a step-up circuit. When an input power supply is normal, the step-down circuit performs reduction processing on an input voltage. The input voltage that has undergone reduction processing charges the energy storage capacitor. When the input power supply is power-off, the step-up circuit performs boost processing on an energy storage voltage of the energy storage capacitor, and the energy storage voltage that has under gone boost processing supplies power to an output load. In other words, the embodiment of the present invention, a manufacturing characteristic of a capacitor is used: under a requirement for the same volume, the capacity of a capacitor having a low voltage-resistant value is far higher than the capacity of a capacitor having a high voltage-resistant value. In the embodiment of the present invention, the selection of a low-voltage capacitor is implemented by performing reduction processing on an input voltage, so as to assure that the selection of a capacitor having a large capacity is implemented in a low voltage. Thereby, the maximum energy storage in a low voltage is implemented. During the power-off, the energy stored in the capacitor having a large capacity performs a boost action on the energy storage capacitor through the step-up circuit, so as to achieve long hold-up time. However, in the prior art, if a high voltage is input, the selection range of a capacitor is narrow. That is, a capacitor having a large volume and a large capacity cannot be used. Therefore, the long hold-up time cannot be achieved. On the contrary, if a low voltage is input, the selection range of a capacitor is wide, and may include a capacitor having a large volume and a large capacity. However, the input voltage is close to an under-voltage point of a load, so the long hold-up time cannot be achieved either. It can be seen that, compared with the prior art, the method provided in this embodiment avoids the problem in the prior art that it is difficult to select a capacitor for an input voltage having a wide range. In the embodiment of the present invention, the selection of a capacitor having a low voltage-resistant value and a large capacity is implemented by performing reduction processing on an input voltage. Then the step-up circuit boosts the capacitor, which assures a long hold-up time function when a low voltage is input. Thereby, it is assured that a long power-off protecting time can still be achieved when the low voltage is input in a condition that the input voltage has a wide range.
Referring to
In this embodiment, the step-down circuit may specifically be a linear voltage stabilizing circuit, a buck converter (Buck Converter), a buck-boost converter (Buck-Boost Converter), or a Cuk converter (Cuk Converter). The step-up circuit may specifically be a boost converter (Boost Converter), a single-ended primary inductance converter (Single-Ended Primary Inductance Converter; SEPIC for short below), or a flyback converter (Flyback Converter).
Moreover, the hold-up time circuit of this embodiment may further include a reverse-proof diode D6. A positive electrode of the reverse-proof diode D6 is connected to one end of the input power supply, and a negative electrode thereof is connected to the first input end of the step-down circuit, that is, the collector of the first electronic triode Q1, so as to prevent the energy of the input power supply or the energy storage capacitor from being reversed when the power supply is power-off.
Specifically, in
P0 is the power of the output load, and η is the efficiency of the output load. Compared with the aforementioned formula (1), in a condition of a low voltage input, V1 and V4 are basically equal to each other. However, with the layout space being the same, the capacitance value C1 of the energy storage capacitor in this embodiment is far larger than the capacitance value C of an energy storage capacitor in the prior art. It can be known that, in comparison with the prior art, the hold-up time may be prolonged by using the method provided in this embodiment. For example, experiments prove that, under a condition of the same volume, the capacitance value of a capacitor having a voltage-resistant value of 42 V is 212.8% of the capacitance value of a capacitor having a voltage-resistant value of 80V. Therefore, the hold-up time that may be achieved in this embodiment is up to more than twice that of the prior art.
It can be seen that, this embodiment provides a hold-up time circuit, which includes an energy storage capacitor, a step-down circuit and a step-up circuit. When an input power supply is normal, the step-down circuit performs reduction processing on an input voltage. The input voltage that has undergone reduction processing charges the energy storage capacitor. When the input power supply is power-off, the step-up circuit performs boost processing on an energy storage voltage of the energy storage capacitor, and the energy storage voltage that has undergone boost processing supplies power to an output load. In other words, in the embodiment of the present invention, the manufacturing characteristic of a capacitor is used: under a requirement for the same volume, the capacity of a capacitor having a low voltage-resistant value is far higher than the capacity of a capacitor having a high voltage-resistant value. In the embodiment of the present invention, the selection of a low-voltage capacitor is implemented by performing reduction processing on an input voltage, so as to assure that the selection of a capacitor having a large capacity is implemented in a low voltage. Thereby, the maximum energy storage in a low voltage is achieved. During the power-off, the energy stored in the capacitor having a large capacity performs a boost action on the energy storage capacitor through the step-up circuit, so as to achieve a long hold-up time. However, in the prior art, if a high voltage is input, the selection range of a capacitor is narrow. That is, a capacitor having a large volume and a large capacity cannot be used. Therefore, the long hold-up time cannot be achieved. On the contrary, if a low voltage is input, the selection range of a capacitor is wide, and may include a capacitor having a large volume and a large capacity. However, the input voltage is close to an under-voltage point of a load, so the long hold-up time cannot be achieved either. It can be seen that, compared with the prior art, the method provided in this embodiment avoids the problem in the prior art that it is difficult to select a capacitor for an input voltage having a wide range. In the embodiment of the present invention, the selection of a capacitor having a low voltage-resistant value and a large capacity is implemented by performing reduction processing on an input voltage. Then the step-up circuit boosts the capacitor, which assures that the selection of a capacitor having a large capacity is implemented in a low voltage and achieves a long power-off protecting time when a low voltage is input in a condition that the input voltage has a wide range.
An embodiment of the present invention further provides a power supply system. The power supply system includes an input power supply, a load circuit and the hold-up time circuit shown in
Step 301: When an input power supply is normal, charge an energy storage voltage of an energy storage capacitor through an input voltage that has undergone reduction processing.
Step 302: When the input power supply is power-off, supply power to an output load through an energy storage voltage that has undergone boost processing.
It can be seen that, this embodiment provides a hold-up time method. When the input power supply is normal, the energy storage capacitor is charged through the input voltage that has undergone reduction processing. When the input power supply is power-off, the energy storage voltage of the energy storage capacitor supplies power to the output load, where the energy storage voltage has undergone boost processing. In other words, in the embodiment of the present invention, a manufacturing characteristic of a capacitor is used: under a requirement for the same volume, the capacity of a capacitor having a low voltage-resistant value is far higher than the capacity of a capacitor having a high voltage-resistant value. In the embodiment of the present invention, the selection of a low-voltage capacitor is implemented by performing reduction processing on an input voltage, so as to assure that the selection of a capacitor having a large capacity is implemented in a low voltage. Thereby, the maximum energy storage in a low voltage is achieved. During the power-off, the energy stored in the capacitor having a large capacity performs a boost action on the energy storage capacitor through the step-up circuit, so as to achieve long hold-up time. However, in the prior art, if a high voltage is input, the selection range of a capacitor is narrow. That is, a capacitor having a large volume and a large capacity cannot be used. Therefore, the long hold-up time cannot be achieved. On the contrary, if a low voltage is input, the selection range of a capacitor is wide, and may include a capacitor having a large volume and a large capacity. However, the input voltage is close to an under-voltage point of a load, so the long hold-up time cannot be achieved either. It can be seen that, compared with the prior art, the method provided in this embodiment avoids the problem in the prior art that it is difficult to select a capacitor for an input voltage having a wide range. In the embodiment of the present invention, the selection of a capacitor having a low voltage-resistant value and a large capacity is implemented by performing that has undergone reduction processing on an input voltage. Then the step-up circuit boosts the capacitor, which assures the implementation of a long hold-up time function when a low voltage is input, and achieves a long power-off protecting time when the low voltage is input in a condition that the input voltage has a wide range.
Step 401: When an input power supply is normal, switch on a step-down circuit, switch off a step-up circuit, and the step-down circuit performs reduction processing on an input voltage.
In this embodiment, the step-down circuit and the step-up circuit are set in the circuit. The step-down circuit may specifically be a linear power supply, a linear converting circuit, or a buck converter (Buck Converter). The step-up circuit may specifically be a Boost Converter, a Sepic Converter, or a Flyback Converter. When the input power supply works normally, the step-down circuit is switched on and the step-up circuit is switched off. Specifically, by controlling a feedback benchmark of a converter or a power-supply voltage (VCC) of a PWM chip, the PWM of the step-up circuit is switched off when the input power supply works normally, so that disturbance to the main loop is avoided. When the input power supply works normally, the input voltage of the input power supply first enters the step-down circuit. The step-down circuit performs reduction processing on the input voltage.
Step 402: Charge the energy storage capacitor through the input voltage that has undergone reduction processing.
In this embodiment, when the input power supply works normally, reduction processing is performed by the step-down circuit on the input voltage. The input voltage that has undergone reduction processing charges the energy storage capacitor. The energy storage capacitor in this embodiment may be one capacitor, or may be formed by several capacitors connected in parallel. According to a manufacturing characteristic of a capacitor, under a condition of the same volume, the capacity of a capacitor having a low voltage-resistant value is higher than the capacity of a capacitor having a high voltage-resistant value. Therefore, in this embodiment, by performing reduction processing on an input voltage and then charging an energy storage capacitor by the input voltage that has undergone reduction processing, a low voltage-resistant value of the capacitor may be assured, so that a capacitor having a large capacity may be selected. The defect in the prior art that it is difficult to select a capacitor in a condition of a voltage input of a wide range is overcome. The selection of a capacitor having a large capacity is assured when a low voltage is input, so that the energy storage capacitor may store the maximum energy in a low voltage.
Step 403: When the input power supply is power-off, switch off the step-down circuit, switch on the step-up circuit, and the step-up circuit performs boost processing on the energy storage voltage of the energy storage capacitor.
When the input power supply is power-off, the step-down circuit is switched off, and the step-up circuit is switched on. The step-up circuit starts to work. The step-up circuit performs boost processing on the energy storage voltage of the energy storage capacitor.
Step 404: Perform hold-up time processing on an output load through the energy storage voltage of the energy storage capacitor, where the energy storage voltage has undergone boost processing.
When the input power supply is power-off, the step-up circuit starts to work. When the step-up circuit perform boost on the energy storage voltage, hold-up time is performed on the output load through the energy storage voltage of the energy storage capacitor at the same time, where the energy storage voltage has undergone boost processing. That is, the energy stored in the energy storage capacitor continues to provide energy for the load, so as to implement the hold-up time function.
It can be seen that, this embodiment provides a hold-up time method. When the input power supply is normal, the step-down circuit performs reduction processing on the input voltage. The input voltage that has undergone reduction processing charges the energy storage capacitor. When the input power supply is power-off, the step-up circuit performs boost processing on the energy storage voltage of the energy storage capacitor. Moreover, the energy storage voltage that has undergone boost processing performs hold-up time processing on the output load. In other words, in the embodiment of the present invention, the manufacturing characteristic of the capacitor is used: under a requirement for the same volume, the capacity of a capacitor having a low voltage-resistant value is far higher than the capacity of a capacitor having a high voltage-resistant value. In the embodiment of the present invention, the selection of a low-voltage capacitor is implemented by performing reduction processing on an input voltage, so as to assure that the selection of a capacitor having a large capacity is implemented in a low voltage. Thereby, the maximum energy storage in a low voltage is achieved. During the power-off, the energy stored in the capacitor having a large capacity performs a boost action on the energy storage capacitor through the step-up circuit, so as to achieve a long hold-up time. However, in the prior art, if a high voltage is input, the selection range of a capacitor is narrow. That is, a capacitor having a large volume and a large capacity cannot be used. Therefore, the long hold-up time cannot be achieved. On the contrary, if a low voltage is input, the selection range of a capacitor is wide, and may include a capacitor having a large volume and a large capacity. However, the input voltage is close to an under-voltage point of a load, so the long hold-up time cannot be achieved either. It can be seen that, compared with the prior art, the method provided in this embodiment avoids the problem in the prior art that it is difficult to select a capacitor for an input voltage having a wide range. In the embodiment of the present invention, the selection of a capacitor having a low voltage-resistant value and a large capacity is implemented by performing reduction processing on an input voltage. Then the step-up circuit boosts the capacitor, which assures the implementation of a long hold-up time function when a low voltage is input, assures the selection of a capacitor having a large capacity in a low voltage, and achieves a long power-off protecting time when the low voltage is input in a condition that the input voltage has a wide range.
Persons of ordinary skill in the art can understand that all or a part of the steps of the method according to the embodiments of the present invention may be implemented by a program instructing relevant hardware. The program may be stored in a computer readable storage medium. When the program runs, the steps of the method according to the embodiments of the present invention are performed. The storage medium may be any medium that is capable of storing program codes, such as an ROM, an RAM, a magnetic disk, or a compact disk.
Finally, it should be noted that the above embodiments are merely provided for describing the technical solutions of the present invention, but not intended to limit the present invention. It should be understood by persons of ordinary skill in the art that although the present invention has been described in detail with reference to the embodiments, modifications can be made to the technical solutions described in the embodiments, or equivalent replacements can be made to some technical features in the technical solutions, and such modifications or replacements do not make the corresponding technical solutions depart from the spirit and scope of the present invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201010158598.9 | Apr 2010 | CN | national |
This application is a continuation of International Application No. PCT/CN2010/077904, filed on Oct. 20, 2010, which claims priority to Chinese Patent Application No. 201010158598.9, filed on Apr. 27, 2010, both of which are hereby incorporated by reference in their entireties.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/CN2010/077904 | Oct 2010 | US |
| Child | 13661749 | US |
