Claims
- 1. A data transfer controller comprising:a data transfer hub connected to dispatch data transfer requests specifying a data source, a data destination and a data quantity to be transferred; a plurality of ports each connected to said data transfer hub and including an hub interface unit connected to said data transfer hub, said hub interface unit for each port being identically configured, and an application unit interface connected to said corresponding hub interface unit and configured for an external memory/device expected to be connected to said port, said hub interface unit and said application unit interface operatively connected for data transfer therebetween by a predetermined set of interface signal lines identical for all ports; and said data transfer hub controlling data transfer from a source port corresponding to said data source to a destination port corresponding to said data destination in a quantity corresponding to said data quantity to be transferred of a currently executing data transfer request.
- 2. The data transfer controller of claim 1, wherein:said data transfer hub is clocked at first frequency; said application unit interface of each of said plurality of ports is clocked at second frequency corresponding to the external memory/device expected to be connected to said port; and said hub interface unit of each of said plurality ports includes a first clock domain clocked at said first frequency, a second clock domain clocked at said second frequency of said corresponding application unit interface, and a synchronizer connected to said first clock domain and said second clock domain operative to synchronize signals passing between said first clock domain and said second clock domain.
- 3. The data transfer controller of claim 2, wherein:said hub interface unit further includes a write request queue disposed in said first clock domain, said write request queue storing write requests directed to the external memory/device expected to be connected to said port, said write request queue transmitting write requests to the external memory/device expected to be connected to said port via said application unit interface following acknowledgement of receipt of a last previous command.
- 4. The data transfer controller of claim 2, wherein:said hub interface unit further includes a read request queue disposed in said first clock domain, said read request queue storing read requests directed to the external memory/device expected to be connected to said port, said read request queue transmitting read requests to the external memory/device expected to be connected to said port via said application unit interface following acknowledgement of receipt of a last previous command.
- 5. The data transfer controller of claim 1, wherein:said predetermined set of interface signal lines includes a command valid signal line driven by said hub interface unit indicating that a valid command is being transmitted, at least one command signal line driven by said bus interface unit indicating at least one command, a command acknowledge signal line driven by said application unit interface indicating receipt of a command on said at least one command signal line.
- 6. The data transfer controller of claim 5, wherein:said at least one command signal line includes a read command signal line indicating a read request for reading data from the external memory/device expected to be connected to said corresponding application unit interface.
- 7. The data transfer controller of claim 5, wherein:said at least one command signal line includes a write command signal line indicating a write request for writing data to the external memory/device expected to be connected to said corresponding application unit interface.
- 8. The data transfer controller of claim 1, wherein:said predetermined set of interface signal line s includes at least one application unit data size line driven by said application unit interface.indicating the maximum size of data words accepted by the external memory/device expected to be connected to said port; and wherein said data transfer hub transmits data to and from said corresponding port in data words having a length not greater than said indication of said at least one application unit data size line.
- 9. The data transfer controller of claim 8, wherein:said predetermined set of interface signal lines further includes a plurality of data lines divided into a plurality of data line groups, at least one data strobe signal line equal in number to a number of data line groups of said plurality of data lines, each data strobe indicating whether a corresponding data line group is employed in a current data transfer.
- 10. The data transfer controller of claim 9, wherein:said plurality of data lines includes a plurality of read data lines driven by said application unit interface upon transfer of data from the external memory/device expected to be connected to said corresponding application unit interface; and said at least one data strobe signal line includes a plurality of read strobe lines driven by said hub interface unit.
- 11. The data transfer controller of claim 10, wherein:said plurality of read data lines consists of 32 data lines divided into four groups of 8 data lines each; and said plurality of read strobe lines consists of four read data strobe lines.
- 12. The data transfer controller of claim 9, wherein:said plurality of data lines includes a plurality of write data lines driven by said hub interface unit upon transfer of data to the external memory/device expected to be connected to said corresponding application unit interface; and said at least one data strobe signal line includes a plurality of write strobe lines driven by said hub interface unit.
- 13. The data transfer controller of claim 12, wherein:said plurality of write data lines consists of 32 data lines divided into four groups of 8 data lines each; and said plurality of write strobe lines consists of four read data strobe lines.
- 14. A data processing system comprising:a plurality of data processors, each data processor capable of generating a data transfer request specifying a data source, a data destination and a data quantity to be transferred; a data transfer hub connected to said plurality of data processors to dispatch data transfer requests; a plurality of ports each connected to said data transfer hub and including an hub interface unit connected to said data transfer hub, said hub interface unlit for each port being identically configured, and an application unit interface connected to said corresponding hub interface unit and configured for an external memory/device expected to be connected to said port, said hub interface unit and said application unit interface operatively connected; for data transfer therebetween by a predetermined set of interface signal lines identical for all ports; and said data transfer hub controlling data transfer from a source port corresponding to said data source to a destination port corresponding to said data destination in a quantity corresponding to said data quantity to be transferred of a currently executing data transfer request.
- 15. The data processing system of claim 14, wherein:each of said data processors and said data transfer hub are clocked at first frequency; said application unit interface of each of said plurality of ports is clocked at second frequency corresponding to the external memory/device expected to be connected to said port; and said hub interface unit of each of said plurality ports includes a first clock domain clocked at said first frequency, a second clock domain clocked at said second frequency of said corresponding application unit interface, and a synchronizer connected to said first clock domain and said second clock domain operative to synchronize signals passing between said first clock domain and said second clock domain.
- 16. The data processing system of claim 15, wherein:said hub interface unit further includes a write request queue disposed in said first clock domain, said write request queue storing write requests directed to the external memory/device expected to be connected to said port, said write request queue transmitting write requests to the external memory/device expected to be connected to said port via said application unit interface following acknowledgement of receipt of a last previous command.
- 17. The data processing system of claim 15, wherein:said hub interface unit further includes a read request queue disposed in said first clock domain, said read request queue storing read requests directed to the external memory/device expected to be connected to said port, said read request queue transmitting read requests to the external memory/device expected to be connected, to said port via said application unit interface following acknowledgement of receipt of a last previous command.
- 18. The data processing system of claim 14, wherein:said predetermined set of interface signal lines includes a command valid signal line driven by said hub interface unit indicating that a valid command is being transmitted, at least one command signal line driven by said bus interface unit indicating at least one command, a command acknowledge signal line driven by said application unit interface indicating receipt of a command on said at least one command signal line.
- 19. The data processing system of claim 18, wherein:said at least one command signal line includes a read command signal line indicating a read request for reading data from the external memory/device expected to be connected to said corresponding application unit interface.
- 20. The data processing system of claim 18, wherein:said at least one command signal line includes a write command signal line indicating a write request for writing data to the external memory/device expected to be connected to said corresponding application unit interface.
- 21. The data processing system of claim 14, wherein:said predetermined set of interface signal lines includes at least one application unit-data size line driven by said application unit interface indicating the maximum size of data words accepted by the external memory/device expected to be connected to said port; and wherein said data transfer hub transmits data to and from said corresponding port in data words having a length not greater than said indication of said at least one application unit data size line.
- 22. The data processing system of claim 21, wherein:said predetermined set of interface signal lines further includes a plurality of data lines divided into a plurality of data line groups, at least one data strobe signal line equal in number to a number of data line groups of said plurality of data lines, each data strobe indicating whether a corresponding data line group is employed in a current data transfer.
- 23. The data processing system of claim 22, wherein:said plurality of data lines includes a plurality of read data lines driven by said application unit interface upon transfer of data from the external memory/device expected to be connected to said corresponding application unit interface; and said at least one data strobe signal line includes a plurality of read strobe lines driven by said hub interface unit.
- 24. The data processing system of claim 23, wherein:said plurality of read data lines consists of 32 data lines divided into four groups of 8 data lines each; and said plurality of read strobe lines consists of four read data strobe lines.
- 25. The data processing system of claim 22, wherein:said plurality of data lines includes a plurality of write data lines driven by said hub interface unit upon transfer of data to the external memory/device expected to be connected to said corresponding application unit interface; and said at least one data strobe signal line includes a plurality of write strobe lines driven by said hub interface unit.
- 26. The data processing system of claim 25, wherein:said plurality of write data lines consists of 32 data lines divided into four groups of 8 data lines each; and said plurality of write strobe lines consists of four read data strobe lines.
- 27. The data processing system of claim 14 wherein:said plurality of data processors, said data transfer hub and each of said plurality of ports are disposed on a single integrated circuit.
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims priority under 35 USC §119(e)(1) of Provisional Application No. 60/153,192, filed Sep. 10, 1999.
This application is related to the following patent applications:
U.K. Patent Application No. 09/543,870, filed Apr. 16, 1999, entitled TRANSFER CONTROLLER WITH HUB AND PORTS ARCHITECTURE;
U.S. patent application ser. No. 09/713,609, filed contemporaneously with this application, entitled EXPANDED (Attorney Docket No. TI-28977); and
U.S. patent application Ser. No. 09/638,512, filed contemporaneously with this application, entitled CONFIGURATION BUS RECONFIGURABLE/REPROGRAMMABLE INTERFACE FOR EXPANDED DIRECT MEMORY ACCESS PROCESSOR.
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