Hybrid drives are conventional disk drives augmented with a non-volatile semiconductor memory (NVSM) such as a flash which helps improve certain aspects of the disk drive. For example, the non-volatile semiconductor memory may store boot data in order to expedite the boot operation of a host computer. Another use of a NVSM may be to store frequently accessed data and/or non-sequential data for which the access time is typically much shorter than the disk (which suffers from mechanical latency including seek and rotational latency). Other policies may reduce write amplification of the NVSM in order to maximize its longevity, such as storing frequently written data to the disk (or data having a write/read ratio that exceeds a predetermined threshold).
In the embodiment of
The disk 4 shown in the embodiment of
The NVSM 6 is typically accessed faster than the disk 4, particularly for non-sequential access commands where accessing the disk involves a seek latency of the head and a rotational latency of the disk. Therefore, the NVSM 6 typically improves the performance of a hybrid drive as compared to a conventional disk drive. However, the size of the NVSM 6 is typically limited to reduce cost, thereby limiting the performance benefit. In addition, the reliability of recorded data is a significant concern whether stored on the disk or the NVSM. To increase reliability, data is typically recorded with ECC symbols that enable the detection and correction of errors during read operations. However, the ECC symbols are overhead that decreases the storage capacity of the storage medium, and in the case of the NVSM, reduces the performance benefit.
Accordingly, in an embodiment of the present invention, when data is written to the NVSM a first number of ECC symbols are generated for detecting and correcting a first number of errors during read operations, and a second (greater) number of ECC symbols are generated for detecting and correcting a second (greater) number of errors. This embodiment is understood with reference to the flow diagram of
In one embodiment, the first number of ECC symbols is small enough to increase the user data capacity of the NVSM, but large enough to ensure the correction power is sufficient most of the time to avoid the performance degradation due to accessing the disk to read the second ECC symbols. In one embodiment, the second ECC symbols for a number of the NVSM data sectors may be cached in a volatile semiconductor memory (e.g., RAM) to avoid the latency in accessing the disk. For example, in one embodiment the second ECC symbols for the most frequently read (or most recently read) NVSM data sectors may be read from the disk and cached in a RAM as part of the normal operation of the hybrid drive.
Any suitable ECC algorithm may be employed to generate the first and second ECC symbols. In one embodiment, a suitable polynomial code (e.g., a Reed-Solomon code) may be used to generate both the first and second ECC symbols. This embodiment is understood with reference to
In one embodiment, the number of second ECC symbols generated for an NVSM data sector equals the number of third ECC symbols generated for a disk data sector as illustrated in
In one embodiment, a parity data sector is generated for each block of memory in the NVSM, and the parity sector is flushed to the disk when a current open block is filled with data. A new parity sector is then started for the next block opened. In other embodiments, multiple parity sectors may be generated for each block, and in an embodiment described below with reference to
In one embodiment, the number of times the second ECC symbols are needed to recover an NVSM data sector is used to determine when to retire a block in the NVSM. That is, the occurrence of unrecoverable NVSM data sectors may indicate an NVSM block is failing, and therefore the NVSM block is retired.
Any suitable control circuitry may be employed to implement the flow diagrams in the embodiments of the present invention, such as any suitable integrated circuit or circuits. For example, the control circuitry may be implemented within a read channel integrated circuit, or in a component separate from the read channel, such as a disk controller and/or NVSM controller, or certain steps described above may be performed by a read channel and others by a disk controller and/or NVSM controller. In one embodiment, the read channel and controllers are implemented as separate integrated circuits, and in an alternative embodiment they are fabricated into a single integrated circuit or system on a chip (SOC). In addition, the control circuitry may include a suitable preamp circuit implemented as a separate integrated circuit, integrated into the read channel or disk controller circuit, or integrated into an SOC.
In one embodiment, the control circuitry comprises a microprocessor executing instructions, the instructions being operable to cause the microprocessor to perform the steps of the flow diagrams described herein. The instructions may be stored in any computer-readable medium. In one embodiment, they may be stored on a non-volatile semiconductor memory external to the microprocessor, or integrated with the microprocessor in a SOC. In another embodiment, the instructions are stored on the disk and read into a volatile semiconductor memory when the hybrid drive is powered on. In yet another embodiment, the control circuitry comprises suitable logic circuitry, such as state machine circuitry.
The present application claims priority from co-pending provisional U.S. Patent Application Ser. No. 61/378,869, filed on Aug. 31, 2010, the specification of which is incorporated herein by reference.
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