Patent Application
20250185379
The present non-provisional patent application claims priority to Chinese Patent Application No. 202311645077.X, filed Dec. 4, 2023, and entitled “Hybrid Heterojunction Solar Cell, Cell Component and Preparation Method.” The entirety of the above identified Chinese patent application is hereby incorporated by reference into the present non-provisional patent application.
The present disclosure mainly relates to the field of solar cell technology, and in particular to a hybrid heterojunction solar cell, cell component and preparation method.
Heterojunction (HJT) cells have a series of advantages such as high conversion efficiency, few manufacturing processes, and disclosure of thin silicon wafers, and are considered as the third direction of change in the photovoltaic industry. As more and more companies enter the HJT cell track, it is expected that HJT cell technology will stand out among many cell technologies in the future, and HJT cells will achieve large-scale mass production. Although HJT cells are theoretically more efficient, one of the biggest problems with HJT solar cells is ultraviolet radiation-induced attenuation. Compared with other types of cells, the amorphous silicon/microcrystalline silicon layer of HJT cells is more susceptible to damage by ultraviolet radiation which produces defects on the surface, and compared with other types of cells, the HJT cells decay faster, resulting in a decrease in module efficiency.
Some existing technologies use cut-off film to filter ultraviolet rays, but ultraviolet rays are actually useful energy and the cut-off film causes the initial power to attenuate, or other existing technologies use UV light transfer solutions, but they will encounter the problem of yellowing of the film and cannot completely solve the problem of UV attenuation. In addition, in some cells, a single layer of doped polysilicon layer is grown and then partially etched to form a thin doped polysilicon layer structure in the non-metallic area which reduces the light absorption of the polysilicon layer. Since amorphous silicon has a large number of pinhole-like holes, the etching speed is difficult to control, and the process stability is poor during the mass production stage, making the production process more difficult. Therefore, there are still many deficiencies in the surface design methods of heterojunction cells in this field.
The technical problem to be solved by the present disclosure is to provide a hybrid heterojunction solar cell, cell component and preparation method which can obtain stable passivation effect on the cell surface, reduce light absorption in non-metallic areas of the cell, and achieve better process control.
In order to solve the above technical problems, the present disclosure provides a hybrid heterojunction solar cell, which comprise a semiconductor substrate having a substrate front surface and a substrate back surface opposite to each other, wherein the substrate front surface is close to a light-facing side of the cell and the substrate back surface is close to a backlight side of the cell; at least two composite layers located on side of the substrate front surface, each composite layer includes a multi-layer structure of a tunneling layer and a doped polysilicon layer sequentially arranged in a direction gradually away from the substrate front surface.
Optionally, the semiconductor substrate includes single crystal silicon, a doping type of the semiconductor substrate includes N-type or P-type, and a thickness of the semiconductor substrate is 80 μm-180 μm.
Optionally, the substrate front surface includes a textured surface structure, and the substrate back surface includes a textured surface structure and/or a polished surface structure, wherein the textured surface structure includes a pyramid texture surface and/or a corrosion pit texture surface.
Optionally, the hybrid heterojunction solar cell further comprises an intrinsic amorphous silicon layer, a backside doped layer, a transparent conductive layer and a back metal electrode sequentially arranged on one side of the substrate back surface in a direction gradually away from the substrate back surface, wherein, the backside doped layer includes a single layer or a multi-layer structure composed of amorphous silicon, nanocrystalline silicon and/or microcrystalline silicon.
Optionally, a thickness of the intrinsic amorphous silicon layer is 5 nm-20 nm, and a thickness of the backside doped layer is 5 nm-45 nm.
Optionally, the transparent conductive layer includes a transparent oxide conductive film composed of doped indium oxide, zinc oxide and/or tungsten oxide, and a thickness of the transparent conductive layer is 70 nm-120 nm.
Optionally, the composite layers include a first doped polysilicon layer located in a first composite layer and a second doped polysilicon layer located in a second composite layer, the first composite layer is closer to the substrate front surface than the second composite layer, and a doping concentration of a lower surface of the second doped polysilicon layer close to the substrate front surface is greater than a doping concentration of an upper surface of the first doped polysilicon layer away from the substrate front surface.
Optionally, the first composite layer further includes a first tunneling layer, and the second composite layer further includes a second tunneling layer, wherein, a thickness of the first tunneling layer is 0.8 nm-2 nm, a thickness of the first doped polysilicon layer is 20 nm-40 nm, a thickness of the second tunneling layer is 1 nm-2.5 nm, and a thickness of the second doped polysilicon layer is 50 nm-150 nm.
Optionally, the hybrid heterojunction solar cell further comprises a plurality of spaced and adjacently arranged contact areas and non-contact areas on side of the substrate front surface, and each contact area includes at least two of the composite layers.
Optionally, each non-contact area only includes one composite layer.
Optionally, the hybrid heterojunction solar cell further comprises a dielectric antireflection layer, located in an outermost layer of the contact areas and the non-contact areas away from the substrate front surface.
Optionally, the dielectric antireflection layer includes a single dielectric layer or a stacked dielectric layer composed of one or more dielectric materials among aluminum oxide, silicon oxide, silicon nitride, silicon oxynitride and magnesium fluoride, and a thickness of the dielectric antireflection layer is 60 nm-120 nm.
In order to solve the above technical problems, another aspect of the present disclosure also provides a cell component, which comprises a plurality of hybrid heterojunction solar cells as described above connected in series and/or in parallel.
In order to solve the above technical problems, another aspect of the present disclosure also provides a method of preparing hybrid heterojunction solar cell, which comprises following steps: preparing semiconductor substrate, the semiconductor substrate has a substrate front surface and a substrate back surface opposite to each other, wherein the substrate front surface is close to a light-facing side of the cell and the substrate back surface is close to a backlight side of the cell; preparing at least two composite layers and a positive metal electrode on the substrate front surface sequentially, each composite layer includes a multi-layer structure of a tunneling layer and a doped polysilicon layer sequentially arranged in a direction gradually away from the substrate front surface; and preparing an intrinsic amorphous silicon layer, a single layer, or a multi-layer structure of doped amorphous silicon, nanocrystalline silicon or microcrystalline silicon, a transparent conductive layer, and a back metal electrode on the substrate back surface sequentially.
Optionally, a method for preparing at least two composite layers further includes: sequentially forming a first tunneling layer, a first doped polysilicon layer, a second tunneling layer and a second doped polysilicon layer on the substrate front surface; laser scanning part of the second doped polysilicon layer to grow a silicon oxide film to obtain a first semi-finished cell, the first semi-finished cell has a plurality of spaced and adjacently arranged contact areas and non-contact areas on side of the substrate front surface, wherein, the contact areas are scanned by the laser, and the non-contact areas are not scanned by the laser; etching the first semi-finished cell by using alkaline solution to remove the second doped polysilicon layer of the non-contact areas; removing the silicon oxide film and the second tunneling layer of the non-contact areas, so that each of the contact areas includes two composite layers, and each of the non-contact areas only includes one composite layer.
Optionally, the preparation method further comprises when preparing the semiconductor substrate, etching the semiconductor substrate by using alkali solution to remove contaminants and form an antireflective texture structure.
Optionally, a method of forming the tunneling layer is thermal oxidation, and a method of forming the polysilicon layer is LPCVD method or PECVD method.
Optionally, when forming the doped polysilicon layer, the method further includes forming a microcrystalline silicon layer first, and at a temperature of 800° C.-930° C., doping with a doping source of phosphorus, annealing and crystallizing the microcrystalline silicon layer to form the doped polysilicon layer.
Optionally, the preparation method further comprises using ALD method or PECVD method to prepare a dielectric antireflection layer on the substrate front surface, and the dielectric antireflection layer includes a single dielectric layer or a stacked dielectric layer composed of one or more dielectric materials among aluminum oxide, silicon oxide, silicon nitride, silicon oxynitride and magnesium fluoride.
Optionally, the preparation method further comprises laser scanning part of the dielectric antireflection layers located in the contact areas to expose the second doped polysilicon layer in the contact areas, and preparing the positive metal electrode on exposed second doped polysilicon layer.
Compared with the existing technology, this disclosure adopts a solar cell with a multi-layer structure of a tunneling layer and a doped polysilicon layer, which can achieve a stable passivation effect on the surface of the cell. A dielectric antireflection film is arranged to reduce light absorption while reducing costs. The tunneling oxide layer on the top layer is designed to better prevent etching during the preparation process and achieve better process control.
The drawings are included to provide a further understanding of the present disclosure, and they are included and constitute a part of the present disclosure, the drawings show the embodiments of the present disclosure, and serving to explain the principles of the present disclosure together with the description. In the drawings:
In order to illustrate the technical solutions in the embodiments of the present disclosure more clearly, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and for those skilled in the art, other drawings can also be obtained based on these drawings without creative effort.
As indicated in this disclosure and claims, the terms “a”, “an”, “a kind of” and/or “the” do not specifically refer to the singular and may include the plural unless the context clearly indicates an exception. Generally speaking, the terms “comprising” and “including” only suggest the inclusion of clearly identified steps and elements, and these steps and elements do not constitute an exclusive list, and the method or device may also contain other steps or elements.
The relative arrangements of components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise. At the same time, it should be understood that, for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship. Techniques, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such techniques, methods and devices should be considered part of the authorized specification. In all embodiments shown and discussed herein, any specific values should be construed as illustrative only, and not as limiting. Therefore, other examples of the exemplary embodiment may have different values. It should be noted that like numerals and letters denote like items in the following figures, therefore, once an item is defined in one figure, it does not require further discussion in subsequent drawings.
In the description of the present disclosure, it should be understood that orientation words such as “front, back, up, down, left, right”, “landscape, portrait, vertical, horizontal” and “top, bottom” etc. indicating the orientation or positional relationship is generally based on the orientation or positional relationship shown in the drawings, only for the convenience of describing the disclosure and simplifying the description, in the absence of a contrary statement, these orientation words do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore cannot be construed as limiting the scope of protection of this disclosure; the orientation words “inside and outside” refer to inside and outside relative to the outline of each part itself.
For the convenience of description, spatially relative terms may be used here, such as “on . . . ”, “over . . . ”, “on the upper surface of . . . ”, “above”, etc., to describe the spatial positional relationship between one device or feature and other devices or features. It will be understood that, in addition to the orientation depicted in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. For example, if the device in the drawings is turned over, devices described as “on other devices or configurations” or “above other devices or configurations” would then be oriented “beneath other devices or configurations” or “under other devices or configurations”. Thus, the exemplary term “above” can encompass both an orientation of “above” and “beneath”. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and making a corresponding explanation for the space relative description used here.
In addition, it should be noted that the use of words such as “first” and “second” to define components is only for the convenience of distinguishing corresponding components, unless otherwise stated, the above words have no special meanings, and therefore cannot be construed as limiting the protection scope of the present disclosure. In addition, although the terms used in this disclosure are selected from well-known and commonly used terms, some terms mentioned in the specification of this disclosure may be selected by the applicant according to his or her judgment, and their detailed meanings are listed in this article described in the relevant section of the description. Furthermore, it is required that this disclosure be understood not only by the actual terms used, but also by the meaning implied by each term.
This disclosure proposes a hybrid heterojunction solar cell 10 (hereinafter referred to as “cell 10”) with reference to
Further, the hybrid heterojunction solar cell proposed in any embodiment of the present disclosure further comprises at least two composite layers located on side of the substrate front surface, each composite layer includes a multi-layer structure of a tunneling layer and a doped polysilicon layer sequentially arranged in a direction gradually away from the substrate front surface. Specifically, in the embodiment shown in
Further, the first composite layer 103 and the second composite layer 104 each has a first tunneling layer 1022 and a second tunneling layer 1024. Both the first tunneling layer 1022 and the second tunneling layer 1024 may be SiO2 tunneling layers. The second tunneling layer 1024 serves as a barrier layer in the diffusion process, and since the doping elements have to pass through the barrier layer during the doping process to reach the first doped polysilicon layer 1023 located under the second tunneling layer 1024, it can reduce the doping concentration of the underlying first doped polysilicon layer 1023.
In this embodiment, a thickness of the first tunneling layer 1022 is 0.8 nm-2 nm. A thickness of the first doped polysilicon layer 1023 is 20 nm-40 nm. A thickness of the second tunneling layer 1024 is 1 nm-2.5 nm. A thickness of the second doped polysilicon layer 1025 is 50 nm-150 nm.
The cell 10 further comprises an intrinsic amorphous silicon layer 107, a backside doped layer 108, a transparent conductive layer 109 and a back metal electrode 114 sequentially arranged on side of the substrate back surface 1012 in a direction gradually away from the substrate back surface 1012. Specifically, a thickness of the intrinsic amorphous silicon layer 107 is 5 nm-20 nm; a thickness of the backside doped layer 108 is 5 nm-45 nm, and the backside doped layer 108 includes a single layer or a multi-layer structure composed of amorphous silicon, nanocrystalline silicon and/or microcrystalline silicon, its doping type is the same as or opposite to that of the semiconductor substrate 101, and is opposite to the doping type of the first doped polysilicon layer 1023 and the second doped polysilicon layer 1025 located on the substrate front surface 1011; the transparent conductive layer 109 includes a transparent oxide conductive film composed of doped indium oxide, zinc oxide and/or tungsten oxide, and a thickness of the transparent conductive layer is 70 nm-120 nm.
Referring to
In this embodiment, the doping concentration of the first doped polysilicon layer 1023 and the second doped polysilicon layer 1025 within the respective layers themselves gradually decreases in a direction from the upper surface farther away from the substrate front surface 1011 to the lower surface closer to the substrate front surface 1011, that is, in the first doped polysilicon layer 1023 and the second doped polysilicon layer 1025, the doping concentration of the lower surface is smaller than the doping concentration of the upper surface. In this embodiment, preferably, the doping concentration of a lower surface of the second doped polysilicon layer 1025 close to the substrate front surface 1011 is greater than a doping concentration of an upper surface of the first doped polysilicon layer 1023 away from the substrate front surface 1011. In this way, it can be better controlled that the doping concentration of the first doped polysilicon layer 1023 in the non-metal area (the non-contact area 106 without the positive metal electrode 113) must be smaller than the doping concentration of the second doped polysilicon layer 1025 in the metal area (the contact area 105 with the positive metal electrode 113), which achieves precise and strict control of the doping concentration of the doped polysilicon layer in the non-metallic area, thereby achieving stable surface passivation effect and low light absorption.
According to
Based on the structure of the cell 10 mentioned above, the present disclosure also provides a cell component, which comprises a plurality of hybrid heterojunction solar cells 10 as described above connected in series and/or in parallel.
Another embodiment of the present disclosure also proposes a method 20 of preparing a hybrid heterojunction solar cell (hereinafter referred to as “method 20”) with reference to
Referring to
Illustratively, the method 20 can be used to prepare the cell 10 as shown in
Referring to
For example, when using the LPCVD method to form the above-mentioned doped polysilicon layer, it can form a microcrystalline silicon layer first, and at a temperature of 800° C.-930° C., dope the microcrystalline silicon layer with a doping source of phosphorus and then anneal and crystallize to form the doped polysilicon layer.
Referring to
Referring to
Referring to
Referring to
Referring to
Finally, referring to
The basic concepts have been described above, obviously, for those skilled in the art, the above disclosure of the disclosure is only an example, and does not constitute a limitation to the present disclosure. Although not expressly stated here, various modifications, improvements and amendments to this disclosure may be made by those skilled in the art. Such modifications, improvements, and amendments are suggested in this disclosure, so such modifications, improvements, and amendments still belong to the spirit and scope of the exemplary embodiments of this disclosure.
Meanwhile, the present disclosure uses specific words to describe the embodiments of the present disclosure. For example, “one embodiment”, “an embodiment”, and/or “some embodiments” refer to a certain feature, structure or characteristic related to at least one embodiment of the present disclosure. Therefore, it should be emphasized and noted that two or more references to “one embodiment” or “an embodiment” or “an alternative embodiment” in different places in this specification do not necessarily refer to the same embodiment. In addition, certain features, structures or characteristics of one or more embodiments of the present disclosure may be properly combined.
In the same way, it should be noted that in order to simplify the expression disclosed in the present disclosure and help the understanding of one or more embodiments of the disclosure, in the foregoing description of the embodiments of the present disclosure, sometimes multiple features are combined into one embodiment, drawings or descriptions thereof. However, this method of disclosure does not imply that the subject matter of the disclosure requires more features than are recited in the claims. Indeed, embodiment features are less than all features of a single foregoing disclosed embodiment.
In some embodiments, numbers describing the quantity of components and attributes are used, it should be understood that such numbers used in the description of the embodiments use the modifiers “about”, “approximately” or “substantially” in some examples. Unless otherwise stated, “about”, “approximately” or “substantially” indicates that the stated figure allows for a variation of ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximations that can vary depending upon the desired characteristics of individual embodiments. In some embodiments, numerical parameters should take into account the specified significant digits and adopt the general digit reservation method. Although the numerical ranges and parameters used in some embodiments of the present disclosure to confirm the breadth of the scope are approximate values, in specific embodiments, such numerical values are set as precisely as practicable.
Although the present disclosure has been described with reference to the current specific embodiments, those of ordinary skill in the art should recognize that the above embodiments are only used to illustrate the present disclosure, and various equivalent changes or substitutions can also be made without departing from the spirit of the present disclosure, therefore, as long as the changes and modifications to the above-mentioned embodiments are within the spirit of the present disclosure, they will all fall within the scope of the claims of the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202311645077.X | Dec 2023 | CN | national |
