HYBRID PHASE-LOCKED LOOP

Abstract

A phase-locked loop (PLL) including a digital PFD, a digital loop filter, a decision circuit, a fractional-N PLL, and a frequency divider is provided. The digital PFD generates a first detection signal according to the phase error or frequency difference between an input signal and a feedback signal. The digital loop filter generates a first control signal according to the first detection signal. The decision circuit generates a divisor value according to the first control signal. The fractional-N PLL generates an oscillation signal according to the divisor value and a reference signal. The frequency divider divides the oscillation signal to produce the feedback signal. The fractional-N PLL includes a fractional-N frequency divider for generating a frequency-divided signal for use in tracking the reference signal according to the divisor value by employing phase swallow means.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram of a prior art analog phase-locked loop (PLL).

FIG. 2 is a simplified diagram of a PLL according to an embodiment of the present invention.

FIG. 3 is a diagram of the decision circuit shown in FIG. 2.

DETAILED DESCRIPTION

Please refer to FIG. 2. FIG. 2 is a simplified diagram of a phase-locked loop (PLL) 200 according to an embodiment of the present invention. As shown in FIG. 2, the PLL 200 comprises a digital PFD 210, a digital loop filter 220, a decision circuit 230, a fractional-N PLL 240, a frequency divider 250. The digital PFD 210 is utilized for generating a first detection signal according to a phase error or frequency difference between an input signal SI and a feedback signal S2. The digital loop filter 220 is utilized for generating a first control signal according to the first detection signal. The decision circuit 230 is utilized for generating a divisor value to control the operation of the fractional-N PLL 240 according to the first control signal. The fractional-N PLL 240 is utilized for generating an oscillation signal S_osc according to the divisor value and a reference signal S_ref. The frequency divider 250 is utilized for performing a frequency dividing operation upon the oscillation signal S_osc to generate the feedback signal S2. In practice, the digital loop filter 220 can be implemented by a PI control circuit.

In this embodiment, the fractional-N PLL 240 comprises a PFD 242, a loop filter 244, a controllable oscillator 246, and a fractional-N frequency divider 248. The fractional-N frequency divider 248 performs a frequency dividing operation or a fractional-N frequency dividing operation upon the oscillation signal S_osc outputted from the controllable oscillator 246 for generating a frequency-divided signal S_fd; the frequency-divided signal S_fd to be used in tracking the reference signal S_ref according to the divisor value generated from the decision circuit 230 by employing phase swallow means. The PFD 242 is utilized for generating a second detection signal according to a phase error or frequency difference between the reference signal S_ref and the frequency-divided signal S_fd. The loop filter 244 is utilized for generating a second control signal according to the second detection signal. The controllable oscillator 246 is utilized for controlling the frequency of the oscillation signal S_osc according to the second control signal. In practice, the PFD 242, loop filter 244, and controllable oscillator 246 can all be implemented with analog circuits. For example, the loop filter 244 can be implemented with a charge pump 262 and low-pass filter 264, and the controllable oscillator 246 can be implemented with a voltage-controllable oscillator (VCO).

For solving the problems in circuit design incurred by the prior art analog PLL, the PLL 200 suppresses an effect caused by variations of the input signal SI by digital processing. In addition, a clock signal (e.g. a quartz oscillation signal) having a frequency being much higher than that of the input signal SI is used as the reference signal S_ref, and the loop bandwidth of the fractional-N PLL 240 is designed to be wide enough for suppressing an effect caused by variations of the oscillation signal S_osc.

Additionally, the fractional-N frequency divider 248 comprises a multi-phase clock generator 272 and a phase selector and frequency divider 274. The multi-phase clock generator 272 is utilized for generating a plurality of clock signals having different phases according to the oscillation signal S_osc generated from the controllable oscillator 246. The phase selector and frequency divider 274 is coupled to the decision circuit 230 and the PFD 242, and is utilized for selectively outputting one of the clock signals having different phases to generate a phase swallowed signal according to an integer divisor value or a non-integer divisor value outputted from the decision circuit 230, and for performing a frequency dividing operation upon the phase swallow signal to generate the frequency-divided signal S_fd. However, this is not intended to be a limitation of the present invention. For example, the controllable oscillator 246 can also be implemented by a ring oscillator having multiple outputs. The ring oscillator with multiple outputs is utilized for generating a plurality of clock signals having different phases, where the clock signals comprise the oscillation signal S_osc. The multi-phase clock generator 272 is therefore omitted. This also falls within the scope of the present invention.

Please refer to FIG. 3. FIG. 3 is a diagram of the decision circuit 230 shown in FIG. 2. As shown in FIG. 3, the decision circuit 230 comprises a sigma-delta modulator (SDM) 310 and a calculation unit 320. The SDM 310 is utilized for generating a modulation value according to the first control signal outputted from the digital loop filter 220. The calculation unit 320 is utilized for generating the divisor value according to the modulation value and a predetermined value. The modulation value is meant to be an adjusting amount for calibrating the divisor value, and the predetermined value is meant to be an initial divisor value. Parameters dM, dK are representative of the integer part and fractional part of the adjusting amount, and parameters M0, K0 are representative of the integer part and fractional part of the initial divisor value, respectively. In practice, the initial divisor value can be calculated by firmware. It is assumed that the multi-phase clock generator 272 in the fractional-N frequency divider 248 generates P clock signals having different phases respectively. As mentioned above, the calculation unit 320 can calculate a divisor value according to the following equation:

M1+K1/P=M0+K0/P+(dM+dK/P)   Equation (1)

wherein parameters M1, K1/P represent the integer part and fractional part respectively of the divisor value.

Each time before the frequency dividing operation is performed, the phase selector and frequency divider 274 generates the phase swallowed signal from the plurality of clock signals having different phases according to the divisor value outputted from the calculation unit 320 by employing phase swallow means. The phase selector and frequency divider 274 then performs the frequency dividing operation upon the phase swallowed signal. Therefore, a phase error between the current and preceding frequency-divided signals S_fd outputted from the fractional-N frequency divider 248 is shorter than the length of a period of the oscillation signal S_osc. The ability of the fractional-N PLL 240 for tracking the reference signal S_ref can be improved. Furthermore, the frequency-divided signal S_fd generated by the fractional-N frequency divider 248 can be used as an operating clock signal for driving the digital loop filter 220 and the decision circuit 230 to improve the ability of the PLL 200 for tracking the input signal S1 further.

In practice, the PLL 200 can also be applied in a control circuit in an LCD device. That is, a horizontal synchronous signal Hsync in the LCD device may be the input signal S1, and the oscillation signal S_osc outputted from the fractional-N PLL 240 (or a signal generated by performing a frequency dividing operation upon the oscillation signal S_osc) may be used as a sampling clock signal (or a clock signal having a higher frequency being a multiple of that of the sampling clock signal) for driving an analog-to-digital converter (ADC) in the LCD device. As mentioned above, the PLL 200 can therefore suppress variations of the horizontal synchronous signal Hsync and sampling clock signal to improve an image quality of the LCD device. This also obeys the spirit of the present invention.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims

1. A phase-locked loop (PLL) comprising: a digital phase/frequency detector (PFD), for generating a first detection signal according to a phase error or a frequency difference between an input signal and a feedback signal;a digital loop filter, coupled to the digital phase/frequency detector, for generating a first control signal according to the first detection signal;a decision circuit, coupled to the digital loop filter, for generating a divisor value according to the first control signal;a fractional-N PLL, coupled to the decision circuit, for generating an oscillation signal according to the divisor value and a reference signal; anda frequency divider, coupled to the fractional-N PLL and the digital phase/frequency detector, for performing a frequency dividing operation upon the oscillation signal to generate the feedback signal;wherein the fractional-N PLL comprises a fractional-N frequency divider for generating a frequency-divided signal for use in tracking the reference signal according to the divisor value by employing phase swallow means.

2. The PLL of claim 1, wherein the fractional-N PLL further comprises: a phase/frequency detector, for generating a second detection signal according to a phase error or a frequency difference between the reference signal and the frequency-divided signal;a loop filter, coupled to the phase/frequency detector, for generating a second control signal according to the second detection signal; anda controllable oscillator, coupled to the loop filter and the fractional-N frequency divider, for generating the oscillation signal according to the second control signal.

3. The PLL of claim 2, wherein the controllable oscillator is a ring oscillator for generating a plurality of clock signals having different phases comprising the oscillation signal.

4. The PLL of claim 3, wherein the fractional-N frequency divider comprises: a phase selector and frequency divider, coupled to the decision circuit, the controllable oscillator, and the phase/frequency detector, for selectively outputting the plurality of clock signals to generate a phase swallowed signal according to the divisor value and for performing a frequency dividing operation upon the phase swallowed signal to generate the frequency-divided signal.

5. The PLL of claim 1, wherein a frequency of the reference signal is higher than a frequency of the input signal.

6. The PLL of claim 1, wherein the fractional-N frequency divider comprises: a multi-phase clock generator, for generating a plurality of clock signals having different phases according to the oscillation signal; anda phase selector and frequency divider, coupled to the decision circuit and the multi-phase clock generator, for selectively outputting the plurality of clock signals to generate a phase swallowed signal according to the divisor value and for performing a frequency dividing operation upon the phase swallowed signal to generate the frequency-divided signal.

7. The PLL of claim 1, wherein the input signal is a horizontal synchronous signal (Hsync).

8. The PLL of claim 1, wherein the decision circuit comprises: a sigma-delta modulator (SDM), coupled to the digital loop filter, for generating a modulation value according to the first control signal; anda calculation unit, coupled to the sigma-delta modulator, for generating the divisor value according to the modulation value and a predetermined value.

9. The PLL of claim 1, wherein the digital loop filter is a PI control circuit.

10. A phase-locked loop (PLL) comprising: a digital phase/frequency detector (PFD), for generating a first detection signal according to a phase error or a frequency difference between an input signal and a feedback signal;a digital loop filter, coupled to the digital phase/frequency detector, for generating a first control signal according to the first detection signal;a decision circuit, coupled to the digital loop filter, for generating a divisor value according to the first control signal;a phase/frequency detector, for generating a second detection signal according to a phase error or a frequency difference between a reference signal and a frequency-divided signal;a loop filter, coupled to the phase/frequency detector, for generating a second control signal according to the second detection signal;a controllable oscillator, coupled to the loop filter, for generating at least an oscillation signal according to the second control signal;a fractional-N frequency divider, coupled to the decision circuit, the phase/frequency detector, and the controllable oscillator, for performing a frequency dividing operation upon an output signal of the controllable oscillator to generate the frequency-divided signal according to the divisor value by employing phase swallow means; anda frequency divider, coupled to the controllable oscillator and the digital phase/frequency detector, for performing a frequency dividing operation upon the oscillation signal to generate the feedback signal.

11. The PLL of claim 10, wherein the fractional-N frequency divider comprises: a multi-phase clock generator, coupled to the controllable oscillator, for generating a plurality of clock signals having different phases according to the oscillation signal; anda phase selector and frequency divider, coupled to the decision circuit, the multi-phase clock generator, and the phase/frequency detector, for selectively outputting the plurality of clock signals to generate a phase swallowed signal according to the divisor value and for performing a frequency dividing operation upon the phase swallowed signal to generate the frequency-divided signal.

12. The PLL of claim 10, wherein the controllable oscillator is a ring oscillator for generating a plurality of clock signals having different phases including the oscillation signal.

13. The PLL of claim 12, wherein the fractional-N frequency divider comprises: a phase selector and frequency divider, coupled to the decision circuit, the controllable oscillator, and the phase/frequency detector, for selectively outputting the plurality of clock signals to generate a phase swallowed signal according to the divisor value and for performing a frequency dividing operation upon the phase swallowed signal to generate the frequency-divided signal.

14. The PLL of claim 10, wherein the input signal is a horizontal synchronous signal (Hsync).

15. The PLL of claim 10, wherein the decision circuit comprises: a sigma-delta modulator, coupled to the digital loop filter, for generating a modulation value according to the first control signal; anda calculation unit, coupled to the sigma-delta modulator, for determining the divisor value according to the modulation value and a predetermined value.

16. The PLL of claim 10, wherein the loop filter comprises a charge pump and a low-pass filter.

17. The PLL of claim 10, wherein a frequency of the reference signal is higher than a frequency of the input signal.

18. The PLL of claim 10, wherein the digital loop filter is a PI control circuit.