Patent Application
20240111095
Embodiments described herein generally relate to semiconductor and photonic devices. Selected examples include devices with photonic integrated circuits and optical waveguides.
Communication between semiconductor devices is challenging as devices become smaller, and as the amount of information communicated is ever increasing. One method of communication utilizes optical data, however, optical waveguides have challenges that make scaling below a certain dimension scale difficult. The examples described by the following disclosure address these concerns, and other technical challenges.
The following description and the drawings sufficiently illustrate specific embodiments to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. Portions and features of some embodiments may be included in, or substituted for, those of other embodiments. Embodiments set forth in the claims encompass all available equivalents of those claims.
A dielectric waveguide with a high index of refraction can utilize total internal reflection to guide light a long distance with a low loss, but the light confinement is limited by diffraction limit. The diffraction limit can prevent the localization of electromagnetic waves into a nanoscale regime. A surface plasmon is confined near a metal surface and is not limited by diffraction but the metal may cause significant propagation loss.
The first dielectric material layer 102 can include a dielectric material with a low index of refraction. In one example, the first dielectric material layer includes at least one of bismuth, nitrogen, indium, and phosphorus. One example of a dielectric material with a low index of refraction can include a bismuth and oxygen compound such as bismuth oxide. One example of a dielectric material with a low index of refraction can include a silicon and oxygen compound such as silica. One example of a dielectric material with a low index of refraction can include a silicon and nitrogen compound such as silicon nitride. One example of a dielectric material with a low index of refraction can include an indium and phosphorous compound such as indium phosphide. In one example, the first dielectric material layer 102 includes material with an index of refraction between about 0.02 and about 3.5.
The second dielectric material layer 103 can include a dielectric material with a high index of refraction. In one example, the first dielectric material layer includes at least one of silicon, aluminum, gallium, and arsenic. One example of a dielectric material with a high index of refraction can include silicon. One example of a dielectric material with a high index of refraction can include an aluminum and gallium and arsenic compound such as aluminum gallium arsenide. One example of a dielectric material with a high index of refraction can include an indium and gallium and arsenic compound such as indium gallium arsenide. In one example, the second dielectric material layer 103 includes material with an index of refraction between about 3.5 and about 15.
One or ordinary skill in the art, having the benefit of the present disclosure, will recognize that the terms “high” and “low” index of refraction are relative to one another. In one example, a material chosen for the second dielectric material layer 103 need only have a higher index of refraction than a material chosen for the first dielectric material layer 102.
Selected dimensions of a hybrid plasmonic waveguide 100 depend on the configuration and materials of the hybrid plasmonic waveguide 100. Generally, a thickness of the first dielectric material layer 102 is small relative to a thickness of the second dielectric material layer 103 to facilitate coupling between the metallic material layer 101 and second dielectric material layer 103. One example of a hybrid plasmonic waveguide 100 can have a width of 100 nm-10,000 nm. One example of a metallic material layer 101 can have a thickness of 80-100 nm. One example of a first dielectric material layer 102 can have a thickness of 5-50 nm. One example of a second dielectric material layer 103 can have a thickness of 300-2,000 nm.
In the example of
In one example the vias 402 include air vias. In one example the vias 402 include light transmissible polymer vias. In one example the embedded hybrid plasmonic waveguide 450 is formed within a dielectric layer 404 that is formed over a glass layer 401 such as a glass substrate or a glass interposer. In one example, the hybrid plasmonic waveguide 450 can be fabricated in a glass cavity with 60-80 degree taper angles to help couple light from the PIC 403 into the hybrid plasmonic waveguide 450.
In one embodiment, processor 610 has one or more processor cores 612 and 612N, where 612N represents the Nth processor core inside processor 610 where N is a positive integer. In one embodiment, system 600 includes multiple processors including 610 and 605, where processor 605 has logic similar or identical to the logic of processor 610. In some embodiments, processing core 612 includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions and the like. In some embodiments, processor 610 has a cache memory 616 to cache instructions and/or data for system 600. Cache memory 616 may be organized into a hierarchal structure including one or more levels of cache memory.
In some embodiments, processor 610 includes a memory controller 614, which is operable to perform functions that enable the processor 610 to access and communicate with memory 630 that includes a volatile memory 632 and/or a non-volatile memory 634. In some embodiments, processor 610 is coupled with memory 630 and chipset 620. Processor 610 may also be coupled to a wireless antenna 678 to communicate with any device configured to transmit and/or receive wireless signals. In one embodiment, an interface for wireless antenna 678 operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.
In some embodiments, volatile memory 632 includes, but is not limited to, Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM), and/or any other type of random access memory device. Non-volatile memory 634 includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.
Memory 630 stores information and instructions to be executed by processor 610. In one embodiment, memory 630 may also store temporary variables or other intermediate information while processor 610 is executing instructions. In the illustrated embodiment, chipset 620 connects with processor 610 via Point-to-Point (PtP or P-P) interfaces 617 and 622. Chipset 620 enables processor 610 to connect to other elements in system 600. In some embodiments of the example system, interfaces 617 and 622 operate in accordance with a PtP communication protocol such as the Intel® QuickPath Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used.
In some embodiments, chipset 620 is operable to communicate with processor 610, 605N, display device 640, and other devices, including a bus bridge 672, a smart TV 676, I/O devices 674, nonvolatile memory 660, a storage medium (such as one or more mass storage devices) 662, a keyboard/mouse 664, a network interface 666, and various forms of consumer electronics 677 (such as a PDA, smart phone, tablet etc.), etc. In one embodiment, chipset 620 couples with these devices through an interface 624. Chipset 620 may also be coupled to a wireless antenna 678 to communicate with any device configured to transmit and/or receive wireless signals. In one example, any combination of components in a chipset may be separated by a continuous flexible shield as described in the present disclosure.
Chipset 620 connects to display device 640 via interface 626. Display 640 may be, for example, a liquid crystal display (LCD), a light emitting diode (LED) array, an organic light emitting diode (OLED) array, or any other form of visual display device. In some embodiments of the example system, processor 610 and chipset 620 are merged into a single SOC. In addition, chipset 620 connects to one or more buses 650 and 655 that interconnect various system elements, such as I/O devices 674, nonvolatile memory 660, storage medium 662, a keyboard/mouse 664, and network interface 666. Buses 650 and 655 may be interconnected together via a bus bridge 672.
In one embodiment, mass storage device 662 includes, but is not limited to, a solid state drive, a hard disk drive, a universal serial bus flash memory drive, or any other form of computer data storage medium. In one embodiment, network interface 666 is implemented by any type of well-known network interface standard including, but not limited to, an Ethernet interface, a universal serial bus (USB) interface, a Peripheral Component Interconnect (PCI) Express interface, a wireless interface and/or any other suitable type of interface. In one embodiment, the wireless interface operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.
While the modules shown in
To better illustrate the method and apparatuses disclosed herein, a non-limiting list of embodiments is provided here:
Example 1 includes a photonic semiconductor package. The photonic semiconductor package includes a metallic material layer, a first dielectric material layer including at least one of bismuth, nitrogen, indium, and phosphorus, a second dielectric material layer including at least one of silicon, aluminum, gallium, and arsenic, wherein the first dielectric material layer is coupled between the metallic material layer and the second dielectric material layer.
Example 2 includes the photonic semiconductor package of example 1, wherein the first dielectric material includes a first index of refraction, and the second dielectric material includes a second index of refraction higher than the first index of refraction.
Example 3 includes the photonic semiconductor package of any one of examples 1-2, wherein the metallic material layer a material selected from the group consisting of gold, silver, coper, aluminum, and a titanium and nitrogen compound.
Example 4 includes the photonic semiconductor package of any one of examples 1-3, wherein the first dielectric material layer includes a material selected from the group consisting of a bismuth and oxygen compound, a silicon and oxygen compound, a silicon and nitrogen compound, and an indium and phosphorous compound.
Example 5 includes the photonic semiconductor package of any one of examples 1-4, wherein the second dielectric material layer is a material selected from the group consisting of silicon, an aluminum and gallium and arsenic compound, and an indium and gallium and arsenic compound.
Example 6 includes the photonic semiconductor package of any one of examples 1-5, further comprising a glass layer coupled to the layer furthest from the metallic material layer.
Example 7 includes the photonic semiconductor package of any one of examples 1-6, further comprising a polymer layer encapsulating the metallic material layer, the first dielectric material layer, and the second dielectric material layer.
Example 8 includes the photonic semiconductor package of any one of examples 1-7, further comprising a third dielectric material layer having a third index of refraction that is lower than the second index of refraction, wherein the third dielectric material layer is coupled to the second dielectric material layer, opposite the first low index dielectric material layer.
Example 9 includes the photonic semiconductor package of any one of examples 1-8, wherein the first dielectric material layer and second dielectric material layer are the same material.
Example 10 is a semiconductor device. The device includes a substrate, a semiconductor die coupled to the substrate, a photonic die, and a waveguide coupled to the photonic die. The waveguide includes a metallic material layer, a first low index dielectric material layer having a first index of refraction, and a high index dielectric material layer having a second index of refraction higher than the first index of refraction, wherein the first low index dielectric material layer is disposed between the metallic material layer and the and the high index material layer.
Example 11 includes the semiconductor device of example 10, further comprising a protective layer laminating the waveguide.
Example 12 includes the semiconductor device of any one of examples 9-11, wherein the substrate includes a glass layer coupled to the waveguide opposite the metallic material layer.
Example 13 includes the semiconductor device of any one of examples 9-12, further comprising a second low index dielectric material layer coupled between the high index dielectric material layer and the glass layer.
Example 14 includes the semiconductor device of any one of examples 9-13, further including a through glass via filled with a conductor, the conductor coupled to an electrical connection on the die.
Example 15 includes the semiconductor device of any one of examples 9-14, further comprising one or more other dielectric layers between the glass layer and the dies.
Example 16 includes the semiconductor device of any one of examples 9-15, wherein the waveguide is recessed within a cavity in the glass interposer.
Example 17 includes the semiconductor device of any one of examples 9-15, wherein the waveguide includes one or more bends.
Example 18 includes the semiconductor device of any one of examples 9-17, further comprising an additional polymer waveguide connecting the photonic die and the waveguide.
Example 19 includes the semiconductor device of any one of examples 9-18, further comprising an air via connecting the photonic die and the waveguide.
Example 20 is a method of forming a waveguide. The method includes forming a first low index dielectric material layer on a glass substrate, forming a high index dielectric material layer on the first low index material layer, forming a second low dielectric index material layer on the high index material layer, forming a metal layer on the second low index dielectric material layer, forming a resist layer on the metal layer, removing a portion of the resist layer to define the waveguide, removing exposed portions of the metal layer, the second low index dielectric material layer, and an upper portion of the high index dielectric material layer, and removing the remaining resist layer.
Example 21 includes the method of example 20, wherein the first low index dielectric material layers, second low index dielectric material layer, and high index dielectric material layer are formed by plasma enhanced chemical vapor deposition.
Example 22 includes the method of any one of examples 19-21, wherein the exposed portions of the metal layer, the second low index dielectric material layer, and an upper portion of the high index dielectric material layer are removed by reactive ion etching.
Example 23 includes the method of any one of examples 19-22, further comprising a forming a protective layer on the waveguide.
Throughout this specification, plural instances may implement components, operations, or structures described as a single instance. Although individual operations of one or more methods are illustrated and described as separate operations, one or more of the individual operations may be performed concurrently, and nothing requires that the operations be performed in the order illustrated. Structures and functionality presented as separate components in example configurations may be implemented as a combined structure or component. Similarly, structures and functionality presented as a single component may be implemented as separate components. These and other variations, modifications, additions, and improvements fall within the scope of the subject matter herein.
Although an overview of the inventive subject matter has been described with reference to specific example embodiments, various modifications and changes may be made to these embodiments without departing from the broader scope of embodiments of the present disclosure. Such embodiments of the inventive subject matter may be referred to herein, individually or collectively, by the term “invention” merely for convenience and without intending to voluntarily limit the scope of this application to any single disclosure or inventive concept if more than one is, in fact, disclosed.
The embodiments illustrated herein are described in sufficient detail to enable those skilled in the art to practice the teachings disclosed. Other embodiments may be used and derived therefrom, such that structural and logical substitutions and changes may be made without departing from the scope of this disclosure. The Detailed Description, therefore, is not to be taken in a limiting sense, and the scope of various embodiments is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled.
As used herein, the term “or” may be construed in either an inclusive or exclusive sense. Moreover, plural instances may be provided for resources, operations, or structures described herein as a single instance. Additionally, boundaries between various resources, operations, modules, engines, and data stores are somewhat arbitrary, and particular operations are illustrated in a context of specific illustrative configurations. Other allocations of functionality are envisioned and may fall within a scope of various embodiments of the present disclosure. In general, structures and functionality presented as separate resources in the example configurations may be implemented as a combined structure or resource. Similarly, structures and functionality presented as a single resource may be implemented as separate resources. These and other variations, modifications, additions, and improvements fall within a scope of embodiments of the present disclosure as represented by the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
The foregoing description, for the purpose of explanation, has been described with reference to specific example embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the possible example embodiments to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The example embodiments were chosen and described in order to best explain the principles involved and their practical applications, to thereby enable others skilled in the art to best utilize the various example embodiments with various modifications as are suited to the particular use contemplated.
It will also be understood that, although the terms “first,” “second,” and so forth may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first contact could be termed a second contact, and, similarly, a second contact could be termed a first contact, without departing from the scope of the present example embodiments. The first contact and the second contact are both contacts, but they are not the same contact.
The terminology used in the description of the example embodiments herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used in the description of the example embodiments and the appended examples, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
As used herein, the term “if” may be construed to mean “when” or “upon” or “in response to determining” or “in response to detecting,” depending on the context. Similarly, the phrase “if it is determined” or “if [a stated condition or event] is detected” may be construed to mean “upon determining” or “in response to determining” or “upon detecting [the stated condition or event]” or “in response to detecting [the stated condition or event],” depending on the context.
