TREA

Hybrid power MOSFET for high current-carrying capacity

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Information

  • Patent Grant
  • 6535050
  • Patent Number
    6,535,050
  • Date Filed
    Monday, July 23, 2001
    23 years ago
  • Date Issued
    Tuesday, March 18, 2003
    21 years ago
Information
Abstract
A hybrid power MOSFET having a low blocking-capability MOSFET and a high blocking-capability junction FET is disclosed. In accordance with the present invention, this cascode circuit has at least two high blocking-capability junction FETs which are electrically connected in parallel and whose gate connections are respectively electrically conductively connected to the source connection of the low blocking-capability MOSFET by means of a connecting line. Thus, a hybrid power MOSFET for a high current-carrying capacity is obtained whose design technology has been considerably simplified on account of the use of only one control line and n+1 chips.
Description




FIELD OF THE INVENTION




The present invention relates to a hybrid power MOSFET having a low blocking-capability MOSFET and a high blocking-capability junction FET.




BACKGROUND OF THE INVENTION




A hybrid power MOSFET having a low blocking-capability MOSFET and a high blocking-capability junction FET is known from DE 196 10 135 C1.

FIG. 1

is used herein to describe this known hybrid power MOSFET in more detail.




Referring to

FIG. 1

, this hybrid power MOSFET has a normally-off n-channel MOSFET


2


, in particular a low voltage power MOSFET, and a normally-on n-channel junction FET


4


. This high blocking-capability junction FET


4


is also referred to as a Junction Field Effect Transistor (JFET). These two FETs are electrically connected in series such that the source connection S of the junction FET


4


is electrically conductively connected to the drain connection D′ of the MOSFET


2


, and that the gate connection G of the junction FET


4


is electrically conductively connected to the source connection S′ of the MOSFET


2


. This electrical interconnection of these two semiconductor components is also commonly known as a cascode circuit. The low blocking-capability MOSFET


2


in this cascode circuit has an internal bipolar diode D


IN


which is connected in antiparallel with MOSFET


2


and is referred to generally as an inverse diode or internal freewheeling diode. The normally-off n-channel MOSFET


2


is made of silicon, whereas the normally-off n-channel JFET


4


is made of silicon carbide. This hybrid power MOSFET is designed for a high reverse voltage of over 600 volts and has only low losses in the passband.




This known cascode circuit is controlled using the gate voltage U


G′S′


of the normally-off MOSFET


2


. If MOSFET


2


is on or the antiparallel internal diode D


IN


of MOSFET


2


is conducting a current, the drain voltage U


D′S′


of MOSFET


2


is approximately zero. The coupling between the gate connection of JFET


4


and the source connection S′ of MOSFET


2


means that the gate voltage U


GS′


of JFET


4


is zero to slightly negative or positive. In accordance with a transfer characteristic, approximately the largest drain current I


D


flows through JFET


4


. If MOSFET


2


is turned off, the drain voltage U


D′S′


rises until the maximum permissible reverse voltage of MOSFET


2


has been reached. The value of the reverse voltage in a low voltage power MOSFET


2


is 30 volts, for example. As soon as the value of the drain voltage U


D′S′


of MOSFET


2


exceeds the value of the threshold voltage U


Th


of JFET


4


, the drain current I


D


of JFET


4


is zero in accordance with its transfer characteristic. In other words JFET


4


is off. The coupling between the gate connection G of JFET


4


and the source connection S′ of MOSFET


2


means that the drain voltage U


D′S′


of MOSFET


2


is fed back negatively to the gate G of JFET


4


.




The known hybrid power MOSFET can, in principle, be connected in parallel, thereby increasing the current-carrying capacity of the whole arrangement. The drawbacks of such a conventional parallel connection of n cascode circuits are as follows: (a) with n parallel cascode circuits, 2n chips are required, which complicates the design technology; and (b) with n parallel cascode circuits, n control lines are required on account of the decoupling of the gate connections of the n MOSFETs.




SUMMARY OF THE INVENTION




The present invention provides for increasing the current-carrying capacity of the known hybrid power MOSFET by using only one low blocking-capability MOSFET and at least two high blocking-capability junction FETs electrically connected in parallel, thus reducing the number of chips in a hybrid power MOSFET having n high blocking-capability junction FETs to n+1 chips. In addition, only one control line is required, since only one low blocking-capability MOSFET is used. This MOSFET has the function of a control head. In addition, the design technology for this inventive hybrid power MOSFET for a high current-carrying capacity is greatly simplified, since instead of 2n chips in a conventional parallel circuit only n+1 chips are now used in the cascode circuit.




In one advantageous refinement of the inventive hybrid power MOSFET of the present invention, a gate resistor is arranged in each connecting line between a gate connection of the parallel-connected junction FETs and a source connection of the low blocking-capability MOSFET. This decouples the control loops of the junction FETs from one another and thus significantly improves the switching response of the hybrid power MOSFET.




In another advantageous refinement of the inventive hybrid power MOSFET of the present invention, an inductance is arranged in each connecting line between the drain connection of the low blocking-capability MOSFET and a source connection of the parallel-connected junction FETs. This improves the balancing of the dynamic current division of the hybrid power MOSFET.




In another advantageous refinement of the present invention, each junction FET of the inventive hybrid power MOSFET has a gate resistor, and a respective inductance is arranged in the connecting lines of the MOSFET with the parallel-connected junction FETs. Thus, a hybrid power MOSFET is obtained whose switching procedure and whose balancing of the dynamic current distribution has been improved. This embodiment is particularly advantageous when the inductance used is a respective elongated bonding wire.











BRIEF DESCRIPTION OF THE DRAWINGS




For a complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings in which like reference numbers indicate like features, components and method step, and wherein:





FIG. 1

illustrates the circuit for a known hybrid power MOSFET;





FIG. 2

illustrates a circuit for an inventive hybrid power MOSFET of the present invention;





FIG. 3

illustrates an exemplary embodiment of the inventive hybrid power MOSFET of

FIG. 2.

;





FIG. 4

illustrates another exemplary embodiment of the inventive hybrid power MOSFET of

FIG. 2.

; and





FIG. 5

illustrates another exemplary embodiment of the inventive hybrid power MOSFET of FIG.


2


.











DETAILED DESCRIPTION OF THE INVENTION




Now referring to the drawings,

FIG. 2

illustrates an inventive hybrid power MOSFET of the present invention in detail. This hybrid power MOSFET has a low blocking-capability MOSFET


2


and n high blocking-capability junction FETs


4




1


to


4




n


. The number of junction FETs


4




1


to


4




n


used depends on the required current-carrying capacity of the hybrid power MOSFET.




These n JFETs


4




1


to


4




n


are electrically connected in parallel. The common source connection S of this parallel circuit


6


is electrically conductively connected to the drain connection D′ of the low blocking-capability MOSFET


2


. This MOSFET


2


has the function of a control head. The use of only one MOSFET


2


obviates n−1 control lines as compared with a conventional parallel circuit comprising a plurality of known hybrid power MOSFETs, which significantly improves the design of this inventive cascode circuit. The gate connections G


1


to G


n


of the parallel-connected JFETs


4




1


to


4




n


are connected to the source connection S′ of the low blocking-capability MOSFET


2


by means of a connecting line


8




1


to


8




n


. As in the case of the known hybrid power MOSFET, the low blocking-capability MOSFET


2


used in the inventive hybrid power MOSFET is a normally-off n-channel power MOSFET, in particular a low voltage power MOSFET, made of silicon. The JFETs


4




1


to


4




n


used are each made of silicon carbide.




In one advantageous embodiment of the inventive hybrid power MOSFET, shown in

FIG. 3

, the gate resistors Rg


1


to Rgn are arranged in each connecting line


8




1


to


8




n


of the parallel circuit


6


. The use of these gate resistors Rg


1


to Rgn decouples the control loops of JFETs


4




1


to


4




n


from one another. This significantly improves the switching response of this inventive cascode circuit.





FIG. 4

shows a further advantageous embodiment of the inventive hybrid power MOSFET of

FIG. 2

in more detail. In this embodiment, a respective inductance L


S1


to L


Sn


is arranged in the connecting lines


10




1


to


10




n


between the source connections S


1


to S


n


and the drain connection D


40


of the low blocking-capability MOSFET


2


. These inductances L


S1


to L


Sn


feed back the voltage drops across these inductances L


S1


to L


Sn


, on account of current changes, to the corresponding gate voltages of each individual JFET


4




1


to


4




n


, so that the current changes in the individual JFETs


4




1


to


4




n


are balanced. This permits an ideally equal current loading for all the JFETs


4




1


to


4




n


. Since small values for the inductance L


S1


to L


Sn


result in marked voltage drops across the inductances L


S1


to L


Sn


with corresponding current gradients, the value of these inductances L


S1


to L


Sn


can be very small. This means that the inductances L


S1


to L


Sn


provided can be a respective elongated bonding wire between the source connections S


1


to S


n


of the parallel-connected JFETs


4




1


to


4




n


and the drain connection D′ of the hybrid power MOSFET


2


.





FIG. 5

illustrates another advantageous embodiment of the hybrid power MOSFET shown in FIG.


2


. This embodiment combines the embodiment shown in

FIG. 3

with the embodiment shown in FIG.


4


. Thus, a cascode circuit is obtained whose balancing of the dynamic current splitting and whose switching response are improved.




Although the present invention has been described in detail with reference to specific exemplary embodiments thereof, various modifications, alterations and adaptations may be made by those skilled in the art without departing from the spirit and scope of the invention. It is intended that the invention be limited only by the appended claims.



Claims
  • 1. A hybrid power MOSFET, said hybrid power MOSFET comprising:a low blocking-capability MOSFET; and at least two high blocking-capability junction FETs, wherein said junction FETs are electrically connected in parallel, wherein a drain connection of said low blocking-capability MOSFET is connected to a source connection of a parallel circuit comprising said junction FETs, and wherein gate connections of said parallel-connected junction FETs are respectively electrically conductively linked to a source connection of said low blocking-capability MOSFET.
  • 2. The hybrid power MOSFET as claimed in claim 1, wherein a gate resistor is arranged in each connecting line between a gate connection of said parallel-connected junction FETs and said source connection of said low blocking-capability MOSFET.
  • 3. The hybrid power MOSFET as claimed in claim 1 or 2, wherein an inductance is arranged in each said connecting line between said drain connection of said low blocking-capability MOSFET and said source connection of said parallel-connected junction FETs.
  • 4. The hybrid power MOSFET as claimed in claim 3, wherein said inductance comprises a respective elongated bonding wire.
  • 5. The hybrid power MOSFET as claimed in claim 1, wherein said low blocking-capability MOSFET comprises a low voltage power MOSFET.
  • 6. The hybrid power MOSFET as claimed in claim 1, wherein said low blocking-capability MOSFET comprises silicon.
  • 7. The hybrid power MOSFET as claimed in claim 1, wherein each of said junction FETs comprises silicon carbide.
Priority Claims (1)
Number Date Country Kind
199 02 519 Jan 1999 DE
Parent Case Info

“This is a continuation of copending application Ser. No. PCT/DE00/00119 filed Jan. 13, 2000, PCT Publication WO 00/44088, which claims the priority of DE 199 02 519.3 filed Jan. 22, 1999.”

US Referenced Citations (1)
Number Name Date Kind
4492883 Janutka Jan 1985 A
Foreign Referenced Citations (2)
Number Date Country
19610135 Jun 1997 DE
0130082 Jan 1985 EP
Non-Patent Literature Citations (2)
Entry
Muraguchi et al., “A Novel MMIC Power Amplifier for Pocket-Size Cellular Telephones”, 1993 IEEE MTT-S Digest, pp. 793-796.
McGrath et al., “A 1.9-GHz GaAs Chip Set for the Personal Handyphone System”, 1995 IEEE Transactions on Microwave Theory and Techniques, Jul., No. 7, PT. II, 1995, 1733-1743.
Continuations (1)
Number Date Country
Parent PCT/DE00/00119 Jan 2000 US
Child 09/911167 US