Claims
- 1. A 2T precoder for a succession of digital words including a current digital word, each of said digital words having a bit length (M-1) where M is a positive odd integer more than one, said 2T precoder comprising:
- an M-parallel-bit-out register including a respective first bit latch wired to receive and temporarily store a particular bit insertion value and further including respective second through M.sup.th bit latches to receive and temporarily store the first through (M-1).sup.th consecutive bits of said current digital word; and
- first through M.sup.th two-input exclusive-OR gates connected to receive as respective first inputs the bits respectively stored in said first through M.sup.th bit latches of said M-parallel-bit-out register, said third through M.sup.th exclusive-OR gates connected to receive as respective second inputs the first through (M-2).sup.th consecutive bits of an M-bit current channel word, said first and second exclusive-OR gates connected to receive as respective second inputs the penultimate and last consecutive bits of an immediately previous channel word, said first through M.sup.th exclusive-OR gates supplying respective responses for defining the consecutive bits of said M-bit current channel word and providing a serial-word, parallel-bits-per-word 2T precoding result as soon as ripple propagation through said first through M.sup.th exclusive-OR gates is completed.
- 2. The 2T precoder of claim 1 in combination with a first parallel-to-serial converter for said serial-word 2T precoding result, said first parallel-to-serial converter comprising:
- a first M-parallel-bit-in/serial-bit-out register comprising first through M.sup.th respective bit latches for respectively temporarily storing the respective responses of said first through M.sup.th exclusive-OR gates, as loaded into said first M-parallel-bit-in/serial-bit-out register subsequent to ripple propagation through said first through M.sup.th exclusive-OR gates being completed for the current digital word stored in said M-parallel-bit-out register, said first M-parallel-bit-in/serial-bit-out register having a respective serial-bit output port for the bits temporarily stored in said M-parallel-bit-in/serial-bit-out register and being clocked for shift register operation through its said serial-bit output port subsequent to loading of its bit latches which shift register operation is complete before its bit latches are next loaded with responses to the digital word following said current digital word.
- 3. The combination of claim 2, wherein M is twenty-five.
- 4. The combination of claim 2 further including a second parallel-to-serial converter for said serial-word 2T precoding result, said second parallel-to-serial converter comprising:
- a second M-parallel-bit-in/serial-bit-out register comprising (M+1).sup.th through 2M.sup.th respective bit latches for respectively temporarily storing the respective responses of said first through M.sup.th exclusive-OR gates, as loaded into said second M-parallel-bit-in/serial-bit-out register subsequent to ripple propagation through said first through M.sup.th exclusive-OR gates being completed for the current digital word stored in said M-parallel-bit-out register, said second M-parallel-bit-in/serial-bit-out register having a respective serial-bit output port for the bits temporarily stored in said second M-parallel-bit-in/serial-bit-out register and being clocked for shift register operation through its said serial-bit output port subsequent to loading of its bit latches which shift register operation is complete before its bit latches are next loaded with responses to the digital word following said current digital word, the clocking for shift register operation of said second M-parallel-bit-in/serial-bit-out register being performed at higher clocking rate than the clocking for shift register operation of said first M-parallel-bit-in/serial-bit-out register.
- 5. The combination of claim 4, wherein M is twenty-five.
- 6. The 2T precoder of claim 1 in combination with a first parallel-to-serial converter for odd bits of said serial-word 2T preceding result, which odd bits are P=(M+1)/2 in number, said first parallel-to-serial converter comprising:
- a P-parallel-bit-in/serial-bit-out register comprising first through P.sup.th respective bit latches for respectively temporarily storing the respective responses of said first through M.sup.th exclusive-OR gates that are identified by odd ordinal number, as loaded into said P-parallel-bit-in/serial-bit-out register subsequent subsequent to ripple propagation through said first through M.sup.th exclusive-OR gates being completed for the current digital word stored in said M-parallel-bit-out register, said P parallel-bit-in/serial-bit-out register having a respective serial-bit output port for the bits temporarily stored in said P-parallel-bit-in/serial-bit-out register and being clocked for shift register operation through its said serial-bit output port subsequent to loading of its bit latches which shift register operation is complete before its bit latches are next loaded with selected responses to the digital word following said current digital word.
- 7. The combination of claim 6, wherein M is twenty-five and P is 13.
- 8. The combination of claim 6 further including a second parallel-to-serial converter for even bits of said serial-word 2T precoding result, which even bits are Q =(M-1)/2 in number, said second parallel-to-serial converter comprising:
- a Q-parallel-bit-in/serial-bit-out register comprising (P+1).sup.th through (P+Q).sup.th respective bit latches for respectively temporarily storing the respective responses of said first through M.sup.th exclusive-OR gates that are identified by even ordinal number, as loaded into said Q-parallel-bit-in/serial-bit-out register subsequent subsequent to ripple propagation through said first through M.sup.th exclusive-OR gates being completed for the current digital word stored in said M-parallel-bit-out register, said Q parallel-bit-in/serial-bit-out register having a respective serial-bit output port for the bits temporarily stored in said Q-parallel-bit-in/serial-bit-out register and being clocked for shift register operation through its said serial-bit output port subsequent to loading of its bit latches which shift register operation is complete before its bit latches are next loaded with selected responses to the digital word following said current digital word.
- 9. The combination of claim 8, wherein M is twenty-five, P is 13, and Q is twelve.
- 10. The 2T precoder of claim 1, wherein M is twenty-five.
- 11. A modulator for supplying an interleaved non-return-to-zero invert-on-ones (I-NRZI) output signal, said modulator comprising:
- a first 2T precoder as set forth in claim 1 arranged for its respective said particular bit insertion value to be a "1" and
- a second 2T precoder as set forth in claim 1 arranged for its respective said particular bit insertion value to be a "0", said first and second 2T precoders being connected for concurrently receiving the same succession of digital words and respectively supplying a first serial-word preceding result and a second serial-word precoding result as concurrent pairs of current channel words;
- a control signal generator for deciding which of each pair of current channel words is selected for inclusion in said I-NRZI output signal; and
- first parallel-to-serial conversion circuitry converting the parallel-bit words of the selected ones of current channel words to serial-bit form, for generating said I-NRZl output signal.
- 12. The modulator of claim 11, wherein said control signal generator decides which of each pair of current channel words is to be selected for inclusion in said I-NRZI output signal by analyzing samples of at least one of each said pair of current channel words supplied thereto, said modulator further comprising:
- second parallel-to-serial conversion circuitry for converting to a first serial bit stream odd alternate bits of one of each pair of current channel words;
- third parallel-to-serial conversion circuitry for converting to a second serial bit stream even alternate bits of one of each pair of current channel words;
- first code-to-arithmetic mapper circuitry for converting bits of said first serial bit stream to respective arithmetic samples supplied to said control signal generator as a first input signal; and
- second code-to-arithmetic mapper circuitry for converting bits of said second serial bit stream to respective arithmetic samples supplied to said control signal generator as a second input signal.
- 13. The modulator of claim 12, further comprising:
- fourth parallel-to-serial conversion circuitry for converting to a third serial bit stream odd alternate bits of the other of each pair of current channel words not converted to said first serial bit stream by said second parallel-to-serial conversion circuitry;
- fifth parallel-to-serial conversion circuitry for converting to a fourth serial bit stream even alternate bits of the other of each pair of current channel words not converted to said second serial bit stream by said third parallel-to-serial conversion circuitry;
- third code-to-arithmetic mapper circuitry for converting bits of said third serial bit stream to respective arithmetic samples supplied to said control signal generator as a third input signal; and
- fourth code-to-arithmetic mapper circuitry for converting bits of said fourth serial bit stream to respective arithmetic samples supplied to said control signal generator as a fourth input signal.
- 14. The modulator of claim 11, wherein said first parallel-to-serial conversion circuitry comprises:
- a first parallel-to-serial converter for converting said first serial-word precoding results to a first serial bit stream;
- a second parallel-to-serial converter for converting said second serial-word precoding results to a second serial bit stream; and
- a selector for selecting time-interleaved portions of said first and second serial bit streams to generate said I-NRZI output signal in accordance with said control signal generator deciding which of each pair of current channel words is selected for inclusion in said I-NRZI output signal.
- 15. The modulator of claim 14, wherein said control signal generator decides which of each pair of current channel words is to be selected for inclusion in said I-NRZI output signal by analyzing samples of at least one of each said pair of current channel words supplied thereto, said modulator further comprising:
- first code-to-arithmetic mapper circuitry for converting bits of said first serial bit stream to respective arithmetic samples supplied to said control signal generator as a first input signal; and
- second code-to-arithmetic mapper circuitry for converting bits of said second serial bit stream to respective arithmetic samples supplied to said control signal generator as a second input signal.
- 16. The modulator of claim 14, wherein said control signal generator decides which of each pair of current channel words is to be selected for inclusion in said I-NRZI output signal by analyzing samples of at least one of each said pair of current channel words supplied thereto, said modulator further comprising:
- a third parallel-to-serial converter for converting said first serial-word preceding results to a third serial bit stream;
- a fourth parallel-to-serial converter for converting said second serial-word precoding results to a fourth serial bit stream;
- first code-to-arithmetic mapper circuitry for converting bits of said third serial bit stream to respective arithmetic samples supplied to said control signal generator as a first input signal; and
- second code-to-arithmetic mapper circuitry for converting bits of said fourth serial bit stream to respective arithmetic samples supplied to said control signal generator as a second input signal.
- 17. The modulator of claim 11, wherein said control signal generator decides which of each pair of current channel words is to be selected for inclusion in said I-NRZI output signal by analyzing samples of at least one of each said pair of current channel words supplied thereto, said modulator further comprising:
- second parallel-to-serial conversion circuitry for converting said first serial-word preceding results to a first serial bit stream;
- third parallel-to-serial conversion circuitry for converting said second serial-word preceding results to a second serial bit stream;
- first code-to-arithmetic mapper circuitry for converting bits of said first serial bit stream to respective arithmetic samples supplied to said control signal generator as a first input signal; and
- second code-to-arithmetic mapper circuitry for converting bits of said second serial bit stream to respective arithmetic samples supplied to said control signal generator as a second input signal.
- 18. A digital recording apparatus for recording with NRZI modulated signals generated in response to information words, said digital recording apparatus including a 2T precoder for precoding each information word on a parallel bit basis to implement pipeline processing during the generation of the NRZI modulated signals.
Priority Claims (1)
Number |
Date |
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Kind |
94-28377 |
Oct 1994 |
KRX |
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Parent Case Info
This is a continuation-in-part of U.S. patent application Ser. No. 08/472,275 filed 7 Jun. 1995 and of U.S. patent application Ser. No. 08/506,041 filed 24 Jul. 1995, now U.S. Pat. No. 5,642,241.
The present invention relates to digital signal recording apparatus recording interleaved non-return-to-zero, invert-on-ONEs (I-NRZI) modulation that includes pilot signals used for head tracking during playback.
US Referenced Citations (1)
Number |
Name |
Date |
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5642241 |
Kim |
Jun 1997 |
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Related Publications (1)
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Date |
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506041 |
Jul 1995 |
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Continuation in Parts (1)
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472275 |
Jun 1995 |
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