I-Q MISMATCH CALIBRATION AND METHOD

Abstract

Techniques are provided for reducing mismatch between the in-phase (I) and quadrature (Q) channels of a communications transmitter or receiver. In an exemplary embodiment, separate voltages are applied to bias the gates or bulks of the transistors in a mixer of the I channel versus a mixer of the Q channel. In another exemplary embodiment, separate voltages are applied to bias the common-mode reference voltage of a transimpedance amplifier associated with each channel. Techniques are further provided for deriving bias voltages to minimize a measured residual sideband in a received or transmitted signal, or to optimize other parameters of the received or transmitted signal. Techniques for generating separate bias voltages using a bidirectional and unidirectional current digital-to-analog converter (DAC) are also disclosed.

Description

TECHNICAL FIELD

The disclosure relates to communications transceivers and, more particularly, to techniques for correcting mismatch between in-phase (I) and quadrature (Q) mixers in communications transceivers.

BACKGROUND

In a communications transmitter, information may be modulated onto orthogonal signals known as in-phase (I) and quadrature (Q) carriers to form I and Q channels. At the receiver, the I and Q channels may be demodulated to recover the information of interest. Typically, a mixer is provided to modulate or demodulate each channel, i.e., an I mixer for the I channel, and a Q mixer for the Q channel.

Accurate transmission and reception of information requires that the I and Q channels remain orthogonal to each other over the communications link. In practice, mismatch between the I and Q channels, e.g., the mixers of the I and Q channels at either the transmitter or the receiver, introduces correlation between the I and Q channels, causing information from the I channel to “bleed” into the Q channel, and vice versa. This leads to corruption of the information signals.

It would be desirable to provide techniques for reducing mismatch between the I and Q channels.

SUMMARY

An aspect of the present disclosure provides an apparatus comprising a unidirectional current digital to analog converter configured to convert an input current to an analog current, a voltage digital to analog converter configured to convert a base digital voltage to a base analog voltage, and a circuit comprising a plurality of sets of switches and two buffers, and wherein voltage output from a first buffer is based on the analog current and base analog voltage and is greater than voltage output from a second buffer by a voltage offset when a first set of switches is closed, and voltage output from the second buffer is based on the analog current and base analog voltage and is greater than voltage output of the first buffer by the voltage offset when a second set of switches is closed.

Another aspect of the present disclosure provides a method for generating a voltage offset and output voltage comprising converting an input current to an analog current, converting a base digital voltage to a base analog voltage, receiving the analog current and base analog voltage, selectively closing a first set of switches and providing the output voltage from a first buffer at an amount greater than a voltage provided from a second buffer by the voltage offset based on the analog current and base analog voltage; and selectively closing a second set of switches and providing the output voltage from the second buffer at an amount greater than a voltage provided from the first buffer by the voltage offset based on the analog current and base analog voltage.

Yet another aspect of the present disclosure provides an apparatus for generating a voltage offset and output voltage comprising means for converting an input current to an analog current, means for converting a base digital voltage to a base analog voltage, means for receiving the analog current and base analog voltage, and means for selectively closing a first set of switches and providing the output voltage from a first buffer at an amount greater than a voltage provided from a second buffer by the voltage offset based on the analog current and base analog voltage and selectively closing a second set of switches and providing the output voltage from the second buffer at an amount greater than a voltage provided from the first buffer by the voltage offset based on the analog current and base analog voltage.

Yet another aspect of the present disclosure provides a non-transitory computer readable media including program instructions which when executed by a processor cause the processor to perform a method for generating a voltage offset and output voltage, the method comprising converting an input current to an analog current, converting a base digital voltage to a base analog voltage, receiving the analog current and base analog voltage, selectively closing a first set of switches and providing the output voltage from a first buffer at an amount greater than a voltage provided from a second buffer by the voltage offset based on the analog current and base analog voltage, and selectively closing a second set of switches and providing the output voltage from the second buffer at an amount greater than a voltage provided from the first buffer by the voltage offset based on the analog current and base analog voltage.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 depicts an exemplary embodiment of a prior art receiver for a communications system.

FIG. 2 depicts an exemplary embodiment of the receiver shown in FIG. 1, wherein an additional offset calibration control 200 generates one control voltage or set of control voltages VI to bias the I mixer 110, and one control voltage or set of control voltages VQ to bias the Q mixer 120.

FIG. 3A depicts an exemplary embodiment of the I mixer 110 shown in FIG. 2, wherein the control voltage VI is applied to bias the gates of transistors M1, M2, M3, M4.

FIG. 3B depicts an exemplary embodiment of the receiver of FIG. 2 wherein the offset calibration control 200 generates a voltage VI=Vgate1, which is supplied as Vgate to the gates of the transistors of the I mixer 110 as described with reference to FIG. 3A.

FIG. 3C depicts an alternative exemplary embodiment of the I mixer 110 shown in FIG. 2, wherein the control voltage VI is applied to bias the substrates (or bulks) of transistors M1, M2, M3, M4.

FIG. 3D depicts an exemplary embodiment of the receiver of FIG. 2 wherein the offset calibration control 200 generates a voltage VI=Vbulk1 to bias the bulks of the transistors of the I mixer 110 as described with reference to FIG. 3C.

FIG. 4 depicts an exemplary embodiment of an active mixer for the I channel configurable according to the techniques of the present disclosure.

FIG. 5A depicts a direct conversion receiver wherein fully differential transimpedance amplifiers (TIA's) ITIA 510 and QTIA 520 are coupled to the I and Q mixers 110 and 120, respectively.

FIG. 5B depicts a voltage-based architecture for a direct conversion receiver wherein a transconductance (Gm) stage precedes each mixer, followed by a voltage amplification (Av) stage.

FIG. 5C depicts a portion of exemplary circuitry for the architecture of FIG. 5B, wherein Gm stage 550 of FIG. 5B is implemented as a simple differential pair with a resistive load RL.

FIG. 5D depicts a scheme wherein a common-mode bias voltage of the Gm stage output may be directly controlled.

FIG. 6 depicts an exemplary embodiment wherein separate gate bias voltages VgateI1 and VgateI2 are provided to the I mixer, and separate gate bias voltages VgateQ1 and VgateQ2 are provided to the Q mixer.

FIG. 6A depicts a generalized mixer calibration control 600 that can adjust both the net offset between the I and the Q mixers, and the offset between transistors M1, M4 and M2, M3 in the differential pairs of each mixer.

FIG. 7 depicts an exemplary embodiment of a direct conversion receiver wherein the gate bias voltage, the substrate bias voltage, and the common mode reference voltage of each mixer are all made adjustable by offset calibration control 200.

FIG. 8 depicts an exemplary embodiment of a transceiver apparatus according to the present disclosure, wherein the digital output signals I and Q of ADC_I 150 and ADC_Q 160 are supplied to a baseband processor 800.

FIG. 9 depicts an exemplary embodiment of an algorithm implemented by offset calibration control 200 for calibrating bias voltages VI and VQ to minimize RSB as measured by the baseband processor 800.

FIG. 10 depicts an exemplary embodiment wherein the techniques disclosed herein are applied to correct for I-Q mismatch in a transmitter apparatus.

FIG. 11 shows an exemplary embodiment of a voltage and voltage offset generator utilizing a bidirectional current digital-to-analog converter (DAC) to generate the voltages VI and VQ.

FIG. 12 depicts an exemplary embodiment of a voltage and voltage offset generator utilizing a unidirectional current DAC.

DETAILED DESCRIPTION

The detailed description set forth below in connection with the appended drawings is intended as a description of exemplary embodiments of the present invention and is not intended to represent the only exemplary embodiments in which the present invention can be practiced. The term “exemplary” used throughout this description means “serving as an example, instance, or illustration,” and should not necessarily be construed as preferred or advantageous over other exemplary embodiments. The detailed description includes specific details for the purpose of providing a thorough understanding of the exemplary embodiments of the invention. It will be apparent to those skilled in the art that the exemplary embodiments of the invention may be practiced without these specific details. In some instances, well known structures and devices are shown in block diagram form in order to avoid obscuring the novelty of the exemplary embodiments presented herein.

In this specification and in the claims, it will be understood that when an element is referred to as being “connected to” or “coupled to” another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected to” or “directly coupled to” another element, there are no intervening elements present.

FIG. 1 depicts an exemplary embodiment of a prior art receiver for a communications system. In FIG. 1, differential RF input signal RF_INp/RF_INn is provided to a low-noise amplifier (LNA) 100, which amplifies the input signal to produce a differential RF signal RFp/RFn. RFp/RFn is provided to an I mixer 110 and a Q mixer 120. I mixer 110 mixes RFp/RFn with a differential in-phase local oscillator signal LO_Ip/LO_In, while Q mixer 120 mixes RFp/RFn with a differential quadrature local oscillator signal LO_Qp/LO_Qn. The outputs of the mixers 110, 120 are provided to low-pass filters 130, 140, respectively, and subsequently digitized by analog-to-digital converters 150, 160 to produce digital outputs I and Q.

Note the receiver depicted in FIG. 1 is a direct conversion receiver, i.e., the received RF signal is converted directly to baseband by the mixers 110, 120. One of ordinary skill in the art will realize that the techniques disclosed herein may readily be applied to receivers having a non-zero intermediate frequency (IF). Such exemplary embodiments are contemplated to be within the scope of the present disclosure.

Note the particular receiver architecture depicted in FIG. 1 may be considered as having two signal paths: an I signal path including I mixer 110, LPF_I 130, ADC_I 150, and a Q signal path including Q mixer 120, LPF_Q 140, ADC_Q 160. Unless otherwise noted, one of ordinary skill in the art will realize that comments made with reference to one of the (I or Q) signal paths or channels may generally be applied to the other signal path or channel.

One of ordinary skill in the art will realize that an I signal path or a Q signal path may include fewer or more elements than shown in the representative architecture of FIG. 1. For example, an I or Q signal path may also include filters, amplifiers, transimpedance (Gm) blocks in addition to the elements shown. It is contemplated that the techniques disclosed herein may be analogously applied by one of ordinary skill in the art to other such elements not explicitly described. One of ordinary skill in the art will also realize that I and Q signal paths may be present in transmitter architectures as well as receiver architectures, and that the techniques of the present disclosure may be correspondingly applied to transmitter architectures as well.

In FIG. 1, the I local oscillator signal LO_I and the Q local oscillator signal LO_Q are designed to be 90 degrees out of phase with each other, while the I mixer 110 and Q mixer 120 are designed to have identical gain responses. In practice, the phase difference between LO_I and LO_Q may deviate from 90 degrees, and the gains of the I mixer 110 and Q mixer 120 may be mismatched. These factors, as well as other imbalances between the I and Q signal paths, may be collectively referred to as “I-Q mismatch.” I-Q mismatch may lead to undesirable corruption of the demodulated information signals.

According to an aspect the present disclosure, techniques are provided to reduce I-Q mismatch by applying an offset between the corresponding voltages used to bias the I and Q signal paths.

FIG. 2 depicts an exemplary embodiment of the receiver shown in FIG. 1, wherein an additional offset calibration control 200 generates one control voltage or set of control voltages VI to bias the I mixer 110, and one control voltage or set of control voltages VQ to bias the Q mixer 120. One of ordinary skill in the art will realize that the techniques disclosed herein may readily be modified to accommodate, equivalently, a fixed (non-adjustable) bias voltage or set of bias voltages for either the I or the Q mixer, and a variable (adjustable) bias voltage for the other mixer. Such exemplary embodiments are contemplated to be within the scope of the present disclosure.

While VI and VQ are shown as being applied to the I and Q mixers in FIG. 2, one of ordinary skill in the art will realize that the bias voltages may be applied to other elements such as a Gm blocks and/or trans-impedance amplifier blocks, in accordance with the principles described later herein. One of ordinary skill in the art will realize that offsets in the bias voltages may be applied to any element in either signal path that contributes to the net gain (e.g., amplitude or phase) of that signal path. Such exemplary embodiments are contemplated to be within the scope of the present disclosure.

FIG. 3A depicts an exemplary embodiment of the I mixer 110 shown in FIG. 2, wherein the control voltage VI is applied to bias the gates of transistors M1, M2, M3, M4. In FIG. 3A, the differential in-phase local oscillator signal LO_Ip/LO_In is AC coupled to the gates of transistors M1, M2, M3, M4 through coupling capacitors C1 and C2. The control voltage VI is set to the gate bias voltage Vgate, which is applied to the gates of transistors M1, M2, M3, M4 through resistors R1 and R2. RFp and RFn of differential signal RFp/RFn are AC coupled to the sources of the differential pairs M1/M2 and M3/M4, respectively. During operation, the differential output current Ioutp/Ioutn contains a signal component proportional to the mixed product of the LO signal and the RF signal.

Note one of ordinary skill in the art will realize that the exemplary embodiment depicted in FIG. 3A may be similarly applied to bias the corresponding gates of transistors in a Q mixer (not shown) using the control voltage VQ.

FIG. 3B depicts an exemplary embodiment of the receiver of FIG. 2 wherein the offset calibration control 200 generates a voltage VI=Vgate1, which is supplied as Vgate to the gates of the transistors of the I mixer 110 as described with reference to FIG. 3A. The offset calibration control 200 also generates a voltage VQ=Vgate2 supplied to the Q mixer 120, which is used to bias the corresponding gates of transistors in a Q mixer implemented analogously to the I mixer shown in FIG. 3A. By introducing an intentional offset between the voltages VI and VQ, mismatch between the I and Q signal paths may be corrected.

FIG. 3C depicts an alternative exemplary embodiment of the I mixer 110 shown in FIG. 2, wherein the control voltage VI is applied to bias the substrates (or bulks) of transistors M1, M2, M3, M4. In FIG. 3C, the gate biasing of transistors M1, M2, M3, M4 may be fixed, or it may also be made variable in accordance with the principles disclosed previously herein. Note for simplicity, the gate biasing details of the transistors have been omitted from FIG. 3C.

Note one of ordinary skill in the art will realize that the exemplary embodiment depicted in FIG. 3C may be similarly applied to bias the corresponding bulks of transistors in a Q mixer (not shown) using the control voltage VQ.

FIG. 3D depicts an exemplary embodiment of the receiver of FIG. 2 wherein the offset calibration control 200 generates a voltage VI=Vbulk1 to bias the bulks of the transistors of I mixer 110 as described with reference to FIG. 3C. The offset calibration control 200 also generates a voltage VQ=Vbulk2 supplied to the Q mixer 120, which is used to bias the corresponding bulks of transistors in a Q mixer implemented analogously to the mixer shown in FIG. 3C. By introducing an intentional offset between the voltages Vbulk1 and Vbulk2, mismatch between the I and Q signal paths may be corrected.

One of ordinary skill in the art will appreciate that the technique depicted in FIG. 3D requires the transistors (M1, M2, M3, M4) of the I channel mixer to be located in a different well from the corresponding transistors of the Q channel mixer, since the bulk voltage of the I channel mixer should be different from that of the Q channel mixer. This may be possible in RF process technologies having a deep N-well option.

One of ordinary skill in the art will also realize that the techniques described with reference to the passive mixer shown in FIGS. 3A and 3C may also be applied to active mixer topologies. Such exemplary embodiments are contemplated to be within the scope of the disclosure.

For example, FIG. 4 depicts an exemplary embodiment of an active mixer for the I channel configurable according to the techniques of the present disclosure. In FIG. 4, transistors M5 and M6 provide bias current to differential pairs M1, M2 and M3, M4, respectively, of the active mixer. The gate bias VI applied to the transistors M1, M2, M3, M4 of FIG. 4 may be offset relative to the gate bias VQ applied to a Q mixer (not shown) to correct for I-Q imbalance, as described with reference to FIG. 3A. The bulk bias (not shown) of the transistors may also be made adjustable, as described with reference to FIG. 3C.

In an exemplary embodiment, the offset calibration control 200 may generate a gate bias VBIASI applied to the bias transistors M5, M6 that is offset relative to a corresponding gate bias VBIASQ applied to corresponding bias transistors of a Q mixer (not shown) to correct for I-Q imbalance. In yet another exemplary embodiment, the RF signal RF_p/RF_n may be AC coupled to the gates of transistors M5, M6, rather than to the drains of M5, M6 as shown in FIG. 4. Such exemplary embodiments are contemplated to be within the scope of the present disclosure.

One of ordinary skill in the art may readily derive alternative circuit topologies for active or passive mixers, and apply the principles of the present disclosure to bias an I mixer element with an offset relative to a Q mixer element. Such exemplary embodiments are contemplated to be within the scope of the present disclosure.

FIG. 5A depicts a direct conversion receiver wherein fully differential transimpedance amplifiers (TIA's) ITIA 510 and QTIA 520 are coupled to the I and Q mixers 110 and 120, respectively, in case the mixers have current outputs. The TIA's convert the differential output currents of such mixers into differential voltages. Each TIA is provided with an input for receiving a voltage VCM1 or VCM2 for setting a reference voltage for a common-mode feedback (CMFB) circuit of the fully differential TIA. One of ordinary skill in the art will realize that the CMFB circuit is designed to drive the common-mode voltage output of each TIA close to the level set by the reference voltage VCM1 or VCM2.

In an exemplary embodiment, an offset is introduced between the common mode voltage VCM1 applied to the ITIA 510 and the common mode voltage VCM2 applied to the QTIA 520 by offset calibration control 200. The voltages VI and VQ generated by offset calibration control 200 may correspond to the voltages VCM1 and VCM2. By introducing an intentional offset between the voltages VCM1 and VCM2, mismatch between the I and Q channels may be corrected.

One of ordinary skill in the art will realize that according to the present disclosure, an offset may generally be introduced between any corresponding common-mode bias voltages existing in the I and Q channels. For example, FIG. 5B depicts a voltage-based architecture for a direct conversion receiver wherein a transconductance (Gm) stage precedes each mixer, followed by a voltage amplification (Av) stage. FIG. 5C depicts a portion of exemplary circuitry for the architecture of FIG. 5B, wherein Gm stage 550, 560 of FIG. 5B is implemented as a simple differential pair with a resistive load RL. One of ordinary skill in the art will realize that the common-mode voltage of the differential output of the Gm stage 550, 560 in FIG. 5C may be controlled by any of several factors, including the resistance value RL, the size of the transistors M1, M2, and/or the value of the bias current I_B. An offset may be introduced in any of these factors between the I and Q channels of a receiver to correct for mixer imbalance according to the present disclosure.

Alternatively, a common-mode bias voltage for either channel may be directly controlled using a scheme such as depicted in FIG. 5D for the Gm stage. In FIG. 5D, a reference voltage VREFI may set the common-mode voltage of the Gm stage output for the I mixer via feedback amplifier ACM. Similarly, a reference voltage VREFQ may set the common-mode voltage of a corresponding Gm stage output for a Q mixer (not shown). By introducing an offset between VREFI and VREFQ, the principles of the present disclosure may be applied.

In an exemplary embodiment, the techniques for applying a bias offset between the gates and substrates of the I and the Q mixers according to the present disclosure may be combined with the techniques for applying a bias offset between the individual transistors of a differential pair of each mixer, according to the disclosure of U.S. patent application Ser. No. 11/864,310, entitled “Offset correction for passive mixers,” filed Sep. 28, 2007, assigned to the assignee of the present application, the contents of which are hereby incorporated by reference in their entirety. For example, FIG. 6 depicts an exemplary embodiment wherein separate gate bias voltages VgateI1 and VgateI2 are provided to the I mixer, and separate gate bias voltages VgateQ1 and VgateQ2 are provided to the Q mixer. FIG. 6A then depicts a generalized calibration control 600 that can adjust both the common-mode offset between the I and the Q mixers, and the differential offset between transistors M1, M4 and M2, M3 in the differential pairs of each mixer.

One of ordinary skill in the art will realize that further gate voltages (not shown) may be applied to separately bias each of the transistors M1-M4 in each mixer in FIG. 6.

FIG. 7 depicts an exemplary embodiment of a direct conversion receiver wherein the gate bias voltage, the substrate bias voltage, and the common mode reference voltage of each channel are all made adjustable by offset calibration control 200. In this exemplary embodiment, the signals VI and VQ are composite signals, each comprising more than one control voltage per channel.

One of ordinary skill in the art will realize that, in general, each signal VI and/or VQ may be a composite signal that contains some or all of the bias voltages disclosed hereinabove for adjusting bias for a channel. In an exemplary embodiment, any or all of the bias voltages for one of the channels may be fixed, i.e., non-adjustable, while the corresponding bias voltages for the other channel may be made adjustable via offset calibration control 200. Such exemplary embodiments are contemplated to be within the scope of the present disclosure.

Techniques for providing bias offsets to elements in the I-Q signal paths have been disclosed hereinabove. Techniques for adjusting the bias offsets to reduce I-Q mismatch in the channels are further disclosed hereinbelow.

FIG. 8 depicts an exemplary embodiment of a transceiver apparatus according to the present disclosure, wherein the digital output signals I and Q of ADC_I 150 and ADC_Q 160 are supplied to a baseband processor 800. The baseband processor 800 measures one or more characteristics of the digital signals I and Q, and is coupled to the offset calibration control 200. Based on characteristics of the I and Q signals measured by the baseband processor 800, the offset calibration control 200 generates control voltages VI and VQ.

In an exemplary embodiment, offset calibration control 200 may set voltages VI and VQ to minimize a residual sideband (RSB) of the receiver as measured by the baseband processor 800 from the signals I and Q.

In an exemplary embodiment such as the one depicted in FIG. 6A, a general offset calibration control 600 may jointly optimize the RSB and the second-order input intercept point (IIP2) of the receiver. One of ordinary skill in the art will be able to derive such optimization schemes based on the disclosure of the present application and that of U.S. Patent Application Serial No. 11/864,310, entitled “Offset correction for passive mixers,” previously referenced herein.

In FIG. 8, an antenna 820 is coupled to an antenna connector 840. The antenna 820 generates a differential signal p/n, which is coupled to a duplexer 830. The duplexer 830 may be configured to couple the antenna connector 840 to either the receive chain (RX) 850 or the transmit chain (TX) 810.

To control an input signal RF_INp/RF_INn reaching the receiver for calibration purposes, a controlled input signal may be supplied to the receiver via antenna connector 840. Alternatively, the transmitter (TX) 810 may generate a controlled signal, and the duplexer 830 may couple the TX output to the RX input through residual coupling. Alternatively, in an architecture (not shown), the controlled signal generated by the TX 810 may be coupled directly to the RX input, i.e., bypassing the duplexer 830, during a calibration phase. In an exemplary embodiment, the controlled input signal may comprise a single reference tone.

FIG. 9 depicts an exemplary embodiment of an algorithm implemented by offset calibration control 200 for calibrating bias voltages VI and VQ to minimize RSB as measured by the baseband processor 800. In FIG. 9, a calibration phase begins at step 900 by selecting initial values for voltages VI, VQ. Also at step 900, an input signal RF_INp and RF_INn are provided to the receiver, via one of the techniques discussed above.

At step 910, one or more parameters of signals I and Q corresponding to the selected VI, VQ may be measured and recorded by the baseband processor 800. In an exemplary embodiment, the parameter of interest may be a measured residual sideband (RSB) in the signals I and Q. In alternative exemplary embodiments, the parameter(s) of interest may be any parameter(s) that may be affected by voltages VI, VQ generated by offset calibration control 200.

At step 920, the algorithm determines whether a final bias setting for VI, VQ has been reached. If not, then VI, VQ may be advanced to a next candidate VI, VQ setting in step 930. The algorithm then returns to step 910, wherein the parameter(s) of interest corresponding to the new VI, VQ may be measured. Once the final VI, VQ setting has been reached in step 920, the algorithm proceeds to step 940.

In this way, by stepping through candidate VI, VQ settings, the parameter(s) of interest measured in step 910 may be “sweeped” over a suitable range of VI, VQ settings. After a suitable range has been sweeped, the VI, VQ setting corresponding to the optimum value of the parameter(s) of interest is identified at step 940. In an exemplary embodiment, the setting or settings corresponding to the lowest RSB in the signals I, Q may be identified.

At step 950, the VI, VQ settings identified in step 940 are selected by offset calibration control 200 and applied to the I and Q channels of the receiver in FIG. 8.

While a specific algorithm for determining an optimal VI, VB setting has been described hereinabove, one of ordinary skill in the art will realize that other algorithms for sweeping through calibration settings to determine an optimal setting may be applied. For example, one may employ calibration algorithms disclosed in U.S. patent application Ser. No. 11/864,310, entitled “Offset correction for passive mixers,” previously referenced herein.

Note the calibration techniques disclosed herein may also be applied to optimize any other parameters of interest besides those explicitly described, such as the amplitude or phase gain of either mixer. Such exemplary embodiments are also contemplated to be within the scope of the present disclosure.

In an exemplary embodiment, the calibration phase described in FIG. 9 may be performed when the signal input to the LNA RFp/RFn is known. For example, calibration can be done at the factory, when a chip is tested prior to shipping. Alternatively, calibration can be done during normal operation as follows. Where full duplexing is supported (i.e., simultaneous transmission and reception by a single radio), TX 810 in FIG. 8 may transmit a signal, which is coupled to RX 850 through the residual coupling of the duplexer 830. Note TX 810 may transmit at a suitably high power level to overcome any attenuation between the transmit path and receive path introduced by, for example, the duplexer 830 and/or TX/RX filters (not shown).

In an exemplary embodiment, the offset calibration control 200 may comprise a processor for implementing the steps described in FIG. 9. Code instructing the processor to perform the steps may be stored in any medium such as RAM or ROM accessible by the processor. Offset calibration control 200 may also comprise circuitry, including digital-to-analog conversion circuitry, for generating voltages VI, VQ based on the results of processing the steps of FIG. 9. Such conversion circuitry is later described herein with reference to FIGS. 11 and 12.

FIG. 10 depicts an exemplary embodiment wherein the techniques disclosed herein are applied to correct for I-Q mismatch in a transmitter apparatus. In FIG. 10, I mixer 110 and Q mixer 120 accept baseband input signals BB_I (in-phase) and BB_Q (quadrature-phase) filtered by low-pass filters 1000 and 1010. The mixers 110, 120 modulate the baseband signals to a higher frequency by multiplying with local oscillator signals LO_I and LO_Q. The converted signals are input to a variable-gain amplifier (VGA) 1020, whose output is coupled to a power amplifier (PA) 1030.

In an exemplary embodiment, offset calibration control 200 may generate bias voltages VI and VQ according to the techniques of the present disclosure to calibrate the mixers 110, 120 for I-Q mismatch. Note all of the techniques described herein with respect to biasing an I or Q mixer in a receiver may be applied to bias an I or Q mixer in a transmitter. Also, one of ordinary skill in the art will realize that some exemplary embodiments may partition the functionality of the circuit blocks differently than shown in FIG. 10, for example, the LPF's 1000, 1010 may be incorporated into the functionality of the mixers 110, 120. Such exemplary embodiments are contemplated to be within the scope of the present disclosure.

In an exemplary embodiment, to perform calibration of VI and VQ, the RSB of the PA output may be measured by a “sense loop” (not shown) to downconvert the residual sideband from RF to baseband. The downconverted RSB may be digitized using an ADC, and processed using a baseband processor to adjust the offset calibration control. In an exemplary embodiment, the TX calibration may be done using the architecture shown in FIG. 8 during a “loopback mode” wherein the TX output is coupled directly to the RX input rather than to the antenna.

One of ordinary skill in the art will realize that the techniques disclosed herein need not be applied to the transmitter and receiver configurations explicitly described herein. Rather, the techniques may be applied to any communications apparatus employing I and Q mixers, TIA's, and/or Gm modules. Such exemplary embodiments are contemplated to be within the scope of the present disclosure.

In a further aspect of the present disclosure, techniques are provided for offset calibration control 200 to generate the voltages VI and VQ given a single base voltage and an offset. FIG. 11 shows an exemplary embodiment of a voltage and voltage offset generator utilizing a bidirectional current digital-to-analog converter (DAC) to generate the voltages VI and VQ. In FIG. 11, a digital base voltage VI (DIGITAL) is provided to a voltage DAC 1100. The voltage DAC 1100 outputs a corresponding analog voltage VI (ANALOG). In an exemplary embodiment, the voltage DAC 1100 may be a simple resistor chain selectively tapped by one of a plurality of switches. The output of voltage DAC 1100 is coupled to a buffer 1110. In an exemplary embodiment, the output of the buffer 1110 may be supplied by the offset calibration control 200 in FIG. 2 as the control voltage VI.

Also in FIG. 11, a digital offset voltage Offset (DIGITAL) is provided to a bidirectional current digital-to-analog converter (DAC) 1140. Current DAC 1140 outputs an analog current I_DAC having an amplitude Offset (ANALOG). At node A, corresponding to the output of current DAC 1140, the voltage is as follows:

VA=VI(ANALOG)+Offset(ANALOG)*R;

wherein R is a variable resistance adjustable by the range control 1120. In an exemplary embodiment, R is selectable among four different values by specifying a 2-bit digital control signal (not shown).

In the exemplary embodiment shown, current DAC 1140 is a bidirectional current DAC which can both supply current and sink current. For values of Offset (DIGITAL) corresponding to a positive value, DAC 1140 can supply current, while for values of Offset (DIGITAL) corresponding to a negative value, DAC 1140 can sink current, or vice versa. In this way, a voltage VA can be generated that is either higher or lower than the base voltage VI, depending on the programmed sign of Offset (DIGITAL).

In an exemplary embodiment, the voltage VA may be supplied by the offset calibration control 200 in FIG. 2 as the control voltage VQ (ANALOG).

One of ordinary skill in the art will realize that in alternative exemplary embodiments, VQ may be taken as the base voltage, and an offset applied to VQ to generate VI. In other exemplary embodiments, as disclosed hereinbefore, either VI or VQ may comprise a plurality of control voltages, any or all of which may be generated using the techniques shown in FIG. 11. Such exemplary embodiments are contemplated to be within the scope of the present disclosure.

FIG. 12 depicts an exemplary embodiment of a voltage and voltage offset generator utilizing a unidirectional current DAC 1240 to generate the voltages VI and VQ. In FIG. 12, the unidirectional current DAC 1240 sources a current I_DAC having an amplitude Offset (ANALOG). One of ordinary skill in the art will realize that in an alternative exemplary embodiment (not shown), with appropriate modifications to the circuitry of FIG. 12, the current DAC 1240 may sink rather than source current.

In FIG. 12, base voltage Vbase (DIGITAL) is supplied to a voltage DAC 1100. The output voltage Vbase (ANALOG) of the voltage DAC 1100 is coupled to either buffer 1200 or buffer 1210, depending on the configuration of switches S1, S2, S3, S4, S5, S6.

In a first configuration, wherein VX is high and VXB is low, S1, S2, S5 are closed, and S3, S4, S6 are open. In this configuration, the output of the voltage DAC 1100 is coupled to the input of buffer 1200, and VA is equal to Vbase (ANALOG). The current I_DAC sourced by the current DAC 1240 flows from node D through switch S5 to the output of buffer 1200. The voltage VD at node D is thus given by:

VD=Vbase(ANALOG)+Offset (ANALOG)*R;

wherein R is a variable resistance configurable by range control 1120, as previously described. VD is coupled to the input of buffer 1210 through switch S2, and the output voltage VB of the buffer 1210 is equal to VD. Thus:

VB=VA+Offset(ANALOG)*R. (first configuration)

In a second configuration, wherein VXB is high and VX is low, S1, S2, S5 are open, and S3, S4, S6 are closed. In this configuration, the output of the voltage DAC 1100 is coupled to the input of buffer 1210, and VB is equal to Vbase (ANALOG). The current I_DAC sourced by the current DAC 1240 flows from node D through switch S6 to the output of buffer 1210. The voltage VD at node D is given by:

VD=VB+Offset(ANALOG)*R.

VD is coupled to the input of buffer 1200 through switch S4, and the output voltage VA of the buffer 1200 is equal to VD. In this case:

VA=VB+Offset(ANALOG)*R. (second configuration)

Thus it is seen that in the first configuration, VB is higher than VA by a value Offset (ANALOG) * R, while in the second configuration, VA is higher than VB by Offset (ANALOG) * R.

In an exemplary embodiment, the voltages VI and VQ generated by offset calibration control 200 in FIG. 2 may correspond to the voltages VA and VB in FIG. 12. In this exemplary embodiment, the voltages VI and VQ may be specified by Vbase (DIGITAL), Offset (DIGITAL), variable resistance R, and the configuration of the switches via control voltages VX and VXB.

Those of skill in the art would understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the exemplary embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the exemplary embodiments of the invention.

The various illustrative logical blocks, modules, and circuits described in connection with the exemplary embodiments disclosed herein may be implemented or performed with a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

The steps of a method or algorithm described in connection with the exemplary embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal

In one or more exemplary embodiments, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

The previous description of the disclosed exemplary embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these exemplary embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other exemplary embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the exemplary embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: a unidirectional current digital to analog converter configured to convert an input current to an analog current;a voltage digital to analog converter configured to convert a base digital voltage to a base analog voltage; anda circuit comprising a plurality of sets of switches and two buffers, and wherein voltage output from a first buffer is based on the analog current and base analog voltage and is greater than voltage output from a second buffer by a voltage offset when a first set of switches is closed, and voltage output from the second buffer is based on the analog current and base analog voltage and is greater than voltage output of the first buffer by the voltage offset when a second set of switches is closed.

2. The apparatus of claim 1, wherein the base analog voltage is provided to the first buffer when the second set of switches is closed and to the second buffer when the second set of switches is closed.

3. The apparatus of claim 1, wherein voltage output from the first buffer and the second buffer is provided to a variable resistor controlled by a range control device.

4. The apparatus of claim 3, wherein output from the variable resistor is combined with the analog current to form a feedback sum.

5. The apparatus of claim 4, wherein the feedback sum is provided to the first buffer when the first set of switches is closed and to the second buffer when the second set of switches is closed.

6. The apparatus of claim 1, wherein the first set of switches is open when the second set of switches is closed.

7. The apparatus of claim 3, wherein the voltage offset is resistance of the variable resistor multiplied by the analog current.

8. A method for generating a voltage offset and output voltage comprising: converting an input current to an analog current;converting a base digital voltage to a base analog voltage;receiving the analog current and base analog voltage;selectively closing a first set of switches and providing the output voltage from a first buffer at an amount greater than a voltage provided from a second buffer by the voltage offset based on the analog current and base analog voltage; andselectively closing a second set of switches and providing the output voltage from the second buffer at an amount greater than a voltage provided from the first buffer by the voltage offset based on the analog current and base analog voltage.

9. The method of claim 8, further comprising providing the base analog voltage to the first buffer when the second set of switches is closed and to the second buffer when the first set of switches is closed.

10. The method of claim 8, further comprising providing voltage output from the first buffer and the second buffer a variable resistor controlled by a range control device.

11. The method of claim 10, further comprising combining output from the variable resistor with the analog current to form a feedback sum.

12. The method of claim 11, further comprising providing the feedback sum to the first buffer when the first set of switches is closed and to the second buffer when the second set of switches is closed.

13. The method of claim 8, wherein the first set of switches is open when the second set of switches is closed.

14. The method of claim 10, wherein the voltage offset is resistance of the variable resistor multiplied by the analog current.

15. An apparatus for generating a voltage offset and output voltage comprising: means for converting an input current to an analog current;means for converting a base digital voltage to a base analog voltage;means for receiving the analog current and base analog voltage; andmeans for selectively closing a first set of switches and providing the output voltage from a first buffer at an amount greater than a voltage provided from a second buffer by the voltage offset based on the analog current and base analog voltage and selectively closing a second set of switches and providing the output voltage from the second buffer at an amount greater than a voltage provided from the first buffer by the voltage offset based on the analog current and base analog voltage.

16. The apparatus of claim 15, further comprising means for providing the base analog voltage to the first buffer when the second set of switches is closed and to the second buffer when the first set of switches is closed.

17. The apparatus of claim 15, further comprising means for providing voltage output from the first buffer and the second buffer a variable resistor controlled by a range control device.

18. The apparatus of claim 17, further comprising means for combining output from the variable resistor with the analog current to form a feedback sum.

19. The apparatus of claim 18, further comprising means for providing the feedback sum to the first buffer when the first set of switches is closed and to the second buffer when the second set of switches is closed.

20. The apparatus of claim 15, wherein the first set of switches is open when the second set of switches is closed.

21. The method of claim 17, wherein the voltage offset is resistance of the variable resistor multiplied by the analog current.

22. A non-transitory computer readable media including program instructions which when executed by a processor cause the processor to perform a method for generating a voltage offset and output voltage, the method comprising: converting an input current to an analog current;converting a base digital voltage to a base analog voltage;receiving the analog current and base analog voltage;selectively closing a first set of switches and providing the output voltage from a first buffer at an amount greater than a voltage provided from a second buffer by the voltage offset based on the analog current and base analog voltage; andselectively closing a second set of switches and providing the output voltage from the second buffer at an amount greater than a voltage provided from the first buffer by the voltage offset based on the analog current and base analog voltage.