Patent Application
20250061080
This non-provisional application claims priority under 35 U.S.C. § 119 (a) on Patent Application No(s). 202311037009.5 filed in China, on Aug. 16, 2023, the entire contents of which are hereby incorporated by reference.
The present invention relates to the technical field of communication, especially to coding and decoding and transmission of physical layer data, and in particular to an I2C interface system for I2C transmission, a data writing method and a data reading method.
I2C bus is a simple and bidirectional serial bus developed by the Philips company. Devices interconnected by the I2C bus are called I2C devices, and the interface where an I2C device accesses the I2C bus is called an I2C interface. I2C bus has become a de facto international standard, and the design specification of the I2C bus and its protocols (called standard I2C specification) is usually based on the description of THE I2C-BUS SPECIFICATION VERSION 2.1 Jan. 2000 document.
An I2C interface includes an I2C clock line (generally named after SCL) and an I2C data line (generally named after SDA). An I2C master controller is connected to an I2C interface modules of one or more I2C slave devices through the I2C clock line and I2C data line. The I2C master controller drives the I2C clock line, initiates I2C write operation or read operation, and judges whether data is sent successfully through acknowledge bits. Bit errors on the bus caused by signal interference and other reasons cannot be recognized by I2C slave devices.
The electrical characteristics of the I2C interface require the devices participating in I2C communication to be “common-ground”, otherwise it cannot be transmitted, therefore I2C communication is not suitable for application scenarios with a long transmission distance or a large signal interference. In order to solve this problem, devices for forwarding I2C data are usually added to the I2C bus, but there are new problems when forwarding devices are introduced:
the I2C communication mechanism requires that every time the I2C master controller sends a byte, the I2C slave device should reply an acknowledge bit, which is I2C ACK when the acknowledge bit level is low and I2C NAK, and I2C NAK when the acknowledge bit level is high; in the prior art, every byte sent by the I2C master controller will be transmitted to the module that finally receives the data (called the functional module in this invention), and the functional module will generate the acknowledge bit and send it back to the I2C master controller, therefore the acknowledge speed of the transmission system is slow, which leads to a slow transmission speed.
At present, there is a lack of an efficient solution for I2C transmission.
In order to solve the problem of slow I2C transmission in the prior art, an object of the present invention is to provide an I2C interface system, which includes an I2C interface module and at least one functional module;
Another object of the present invention is to provide an I2C data writing method, which uses an I2C interface system to write data, including:
Preferably, when the data received by the I2C interface module reaches a length indicated by the write command length field, the I2C interface module receiving the write command packet.
Preferably, the write command packet further includes a write command packet check code;
Preferably, when the I2C interface module receives the write status packet and the status information of the write status packet is successful, the I2C interface module stopping pulling down the I2C clock line level and returning I2C ACK to the I2C master controller,
Preferably, when the I2C interface module receives the write status packet and the status information of the write status packet is failed, the I2C interface module stopping pulling down the I2C clock line level and returning I2C NAK to the I2C master controller,
Preferably, before the data received by the I2C interface module reaches the length indicated by the write command length field, the I2C interface module receives the I2C START signal or the I2C STOP signal, then the I2C interface module ends the reception of the current write command packet, and the I2C interface module does not receive the write command packet;
Preferably, when the data received by the I2C interface module reaches the length indicated by the write command length field, but the write command packet check code is verified to be incorrect, the I2C interface module ends the reception of the current write command packet, and the I2C interface module does not receive the write command packet;
Preferably, the I2C interface module includes a timeout timer;
Another object of the present invention is to provide an I2C data writing method, which uses an I2C interface system to write data, including:
Preferably, when the data received by the I2C interface module reaches the length indicated by the write command length field, the I2C interface module receives the write command packet.
Preferably, the write command packet further includes a write command packet check code;
Preferably, when the subsequent I2C operation initiated by the I2C master controller is an I2C read operation,
Preferably, before the data received by the I2C interface module reaches the length indicated by the write command length field, the I2C interface module receives an I2C START signal or an I2C STOP signal, then the I2C interface module ends the reception of the current write command packet, and the I2C interface module does not receive the write command packet;
Preferably, when the data received by the I2C interface module reaches the length indicated by the write command length field, but the write command packet check code is verified to be incorrect, the I2C interface module ends the reception of the current write command packet, and the I2C interface module does not receive the write command packet;
Preferably, the I2C interface module includes a timeout timer;
Preferably, when a subsequent I2C operation initiated by the I2C master controller is an I2C write operation,
Preferably, when the subsequent I2C operation initiated by the I2C master controller is an I2C read operation,
Another object of the present invention is to provide an I2C data reading method, which uses an I2C interface system to read data, including:
Preferably, when the data received by the I2C interface module reaches the length indicated by the read command length field, the I2C interface module receives the read command packet.
Preferably, the read command packet further includes a read command packet check code.
When the data received by the I2C interface module reaches the length indicated by the read command length field and the check code of the read command packet is verified to be correct, the I2C interface module receives the read command packet.
Preferably, when the I2C interface module receives the read data packet, the I2C interface module stops pulling down the I2C clock line level and returns I2C ACK or I2C NAK to the I2C master controller;
If the subsequent I2C operation initiated by the I2C master controller is an I2C write operation, the I2C interface module returns I2C NAK to the I2C master controller;
Preferably, before the data received by the I2C interface module reaches the length indicated by the read command length field, the I2C interface module receives an I2C START signal or tan I2C STOP signal, then the I2C interface module ends the reception of the current read command packet, and the I2C interface module does not receive the read command packet;
Preferably, when the data received by the I2C interface module reaches the length indicated by the read command length field, but the check code of the read command packet is verified to be incorrect, the I2C interface module ends the reception of the current read command packet, and the I2C interface module does not receive the read command packet;
Preferably, the I2C interface module includes a timeout timer;
Preferably, the read data includes data read from the functional module, or read status information generated by the functional module executing the read command, or both data read from the functional module and read status information generated by the functional module executing the read command.
Another object of the present invention is to provide an I2C data reading method, which uses an I2C interface system to read data, including:
Preferably, when the data received by the I2C interface module reaches the length indicated by the read command length field, the I2C interface module receives the read command packet.
Preferably, the read command packet further includes a read command packet check code.
When the data received by the I2C interface module reaches the length indicated by the read command length field and the check code of the read command packet is verified to be correct, the I2C interface module receives the read command packet.
Preferably, before the data received by the I2C interface module reaches the length indicated by the read command length field, the I2C interface module receives an I2C START signal or an I2C STOP signal, then the I2C interface module ends the reception of the current read command packet, and the I2C interface module does not receive the read command packet;
Preferably, when the data received by the I2C interface module reaches the length indicated by the read command length field, but the check code of the read command packet is verified to be incorrect, the I2C interface module ends the reception of the current read command packet, and the I2C interface module does not receive the read command packet;
Preferably, the I2C interface module includes a timeout timer;
Preferably, the read data includes data read from the functional module, or read status information generated by the functional module executing the read command, or both data read from the functional module and read status information generated by the functional module executing the read command.
Preferably, when the subsequent I2C operation initiated by the I2C master controller is an I2C write operation,
Preferably, when the subsequent I2C operation initiated by the I2C master controller is an I2C read operation,
The I2C interface system, data writing method and data reading method for efficiently transmitting I2C provided by the present invention are suitable for application scenarios with long transmission links, and are also compatible with local applications with short transmission links, thus providing an ideal solution for I2C transmission.
In order to explain the specific embodiment of the present invention or the technical solution in the prior art more clearly, the drawings needed in the description of the specific embodiment or the prior art will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained according to these drawings without creative work for those skilled in the art.
The reference signs in the above drawings have the following meanings:
In order to make the above and other features and advantages of the present invention more clear, the present invention will be further described with reference to the accompanying drawings. It should be understood that the specific embodiments given here are for the purpose of explaining to those skilled in the art, and are only illustrative and not restrictive.
Clock line (SCL) and I2C data line (SDA) are collectively called an I2C bus, which has become a de facto international standard. The design specification of I2C bus and its protocols (called standard I2C specification) is usually based on the description in THE I2C-BUS SPECIFICATION VERSION 2.1 Jan. 2000.
As shown in
The I2C interface module 200 is connected to the I2C master controller 100 through an I2C clock line 500 (SCL) and an I2C data line 400 (SDA), and the functional module 300 is connected to the I2C interface module 200. The I2C interface module 200 can be connected with a plurality of functional modules 300, such as a functional module 1, a functional module 2, . . . , and a functional module N. In this embodiment, the I2C interface module 200 is connected to a functional module 300 as an example.
The present invention does not limit the connection mode between the I2C interface module 200 and the functional module 300, the I2C interface module 200 can be connected to one or more functional modules 300 through one or more transmission lines. Meanwhile, the present invention does not limit the location of the I2C interface module 200 and functional module 300, and the I2C interface module 200 and the functional modules 300 can be located in the same integrated circuit chip, or in different integrated circuit chips on a PCB, or the I2C interface module 200 and the functional modules 300 can also be located in different system devices.
An I2C master controller 100 can be connected to one or more I2C interface modules 200 through the same I2C bus (clock line 500 and I2C data line 400) and transmit byte sequences carrying information through an I2C read operation or I2C write operation. In this embodiment, description will be made by taking the I2C master controller 100 connected to the I2C interface module 200 through the same I2C bus (clock line 500 and I2C data line 400) as example.
As shown in
In this embodiment, both the write address byte and the write operation data byte are 8 bits, in which the write address byte contains 7 bits of I2C address (ADDR) and 1 bit of write operation indication bit (W). The present invention does not limit the number of bits of the write address byte and the write operation data byte, and in other embodiments, the write address byte and the write operation data byte can be other bits.
When the I2C master controller 100 initiates an I2C write operation, the I2C master controller 100 first drives the I2C clock line 500 and the I2C data line 400 according to the standard I2C specification to generate an I2C START signal(S), and then sends a write address byte. After receiving the write address byte, the I2C interface module 200 drives the I2C data line 400 to generate an acknowledge bit. According to the standard I2C specification, the acknowledge bit can be I2C ACK (I2C data line level is low) or I2C NAK (I2C data line level is high).
When the acknowledge bit of the write address byte is I2C ACK, the I2C master controller 100 can send one or more write operation data bytes, and the I2C interface module 200 drives the I2C data line 400 to generate the acknowledge bit after receiving each write operation data byte, and the acknowledge bit of the write operation data byte can be I2C ACK (I2C data line level is low) or I2C NAK (I2C data line level is high).
According to the standard I2C specification, when sending a write address byte and one or more write operation data bytes, the I2C master controller 100 sends the number of bits contained in the write address byte and the write operation data byte by driving the I2C data line 400, and drives the I2C clock line 500 to generate a clock pulse for each bit contained in the write address byte and the write operation data byte.
According to the standard I2C specification, the I2C master controller 100 will also drive the I2C clock line 500 to generate a clock pulse corresponding to the acknowledge bit of the write address byte and the acknowledge bit of the write operation data byte. The I2C master controller 100 ends the current write operation by sending an I2C STOP signal (P) or an I2C START signal(S) defined by the standard I2C specification.
As shown in
In this embodiment, both the read address byte and the read operation data byte are 8 bits, in which the read address byte contains 7 bits of I2C address (ADDR) and 1 bit of read operation indication bit (R). The present invention does not limit the number of bits of the read address byte and the read operation data byte, and in other embodiments, the read address byte and the read operation data byte can be other bits.
When the I2C master controller 100 initiates an I2C read operation, the I2C master controller 100 first drives the I2C clock line 500 and the I2C data line 400 according to the standard I2C specification to generate an I2C START signal(S), and then sends a read address byte. After receiving the read address byte, the I2C interface module 200 drives the I2C data line 400 to generate an acknowledge bit, which can be I2C ACK (I2C data line level is low) or I2C NAK (I2C data line level is high) according to the standard I2C specification.
When the acknowledge bit of the read address byte is I2C ACK, the I2C interface module 200 can return one or more read operation data bytes by driving the I2C data line 400. After receiving each read operation data byte, the I2C master controller 100 drives the I2C data line to generate the acknowledge bit, and the acknowledge bit of the read operation data byte can be I2C ACK (the I2C data line level is low) or I2C NAK (the I2C data line level is high).
According to the standard I2C specification, when the I2C master controller 100 sends a read address byte and the I2C interface module 20 returns one or more read operation data bytes, the I2C master controller 100 sends the number of bits contained in the read address byte by driving the I2C data line 400, and the I2C interface module 200 returns the bits contained in the read operation data byte by driving the I2C data line 400, and I2C master controller 100 drives the I2C clock line 500 to generate a clock pulse for each bit contained in the read address byte and the read operation data byte.
According to the standard I2C specification, the I2C master controller 100 will also drive the I2C clock line 500 to generate a clock pulse corresponding to the acknowledge bit of the read address byte and the acknowledge bit of the read operation data byte. The I2C master controller 100 ends the current read operation by sending an I2C STOP signal (P) or an I2C START signal(S) defined by the standard I2C specification.
An I2C write operation or I2C read operation cycle starts with the I2C START signal(S), but there are two ways to end it. The first way is to end it with the I2C STOP signal (P), and the timing is shown in
The second is to generate a new I2C START signal(S) and proceed to the next I2C write operation or I2C read operation. The timing is shown in
Using any of the above termination methods will not affect the data writing method and data reading method of the present invention. For convenience of description, the termination of an I2C operation (I2C write operation or I2C read operation) is described in this embodiment with an I2C STOP signal (P).
First working mode of data writing method.
According to an embodiment of the present invention, there is provided an I2C data writing method, which uses the I2C interface system provided by the present invention to write data, including:
The functional module 300 receives the write command packet and executes a write command. When the functional module 300 completes the write command, it returns the write status packet to the I2C interface module 200.
When the I2C interface module 200 receives the write status packet and the status information of the write status packet is successful, the I2C interface module 200 stops pulling down the I2C clock line 500 level and returns I2C ACK to the I2C master controller 100.
When the I2C interface module 200 receives the write status packet and the status information of the write status packet is failed, the I2C interface module 200 stops pulling down the I2C clock line 500 level and returns I2C NAK to the I2C master controller 100.
The write command packet of the present invention is sent by write operation data bytes (BYTE (1), . . . , BYTE (N), which are shaded), and the write command packet includes a write command length field and a write command data field.
The write command data field of the present invention contains the write command, and the write command packet is used to be distinguished from the read command packet.
The read command packet of the present invention is also sent through write operation data bytes (BYTE (1), . . . , BYTE (N), shaded), and the read command packet includes a read command length field and a read command data field, and the read command data field contains a read command.
For example, when the I2C master controller 100 initiates a write command packet, the I2C master controller 100 initiates an I2C write operation to send a write address byte and one or more write operation data bytes (BYTE (1), . . . , BYTE (N), shaded) including the write command packet to the I2C interface module 200. When the I2C master controller 100 initiates a read command packet, the I2C master controller 100 initiates an I2C write operation to send a write address byte and one or more write operation data bytes (BYTE (1), . . . , BYTE (N), shaded) including the read command packet to the I2C interface module 200.
The I2C interface module 200 has a logic circuit of an I2C interface, and the I2C interface module 200 receives and responds to data from the I2C master controller 100. The I2C interface modules 200 and I2C master controller 100 are interconnected by an I2C bus (a clock line 500 and an I2C data line 400). One I2C master controller 100 is connected to one or more I2C interface modules 200, and each I2C interface module 200 has a unique I2C address (ADDR) on its I2C bus (clock line 500 and I2C data line 400). According to the standard I2C specification, each I2C write operation or I2C read operation except I2C write broadcast is only for one I2C address (ADDR), and the I2C interface module 100 using other I2C addresses does not participate in the I2C write operation or I2C read operation.
With reference to
The write command packet includes a write command length field and a write command data field.
The 0x06 byte corresponds to the write command length field, which is represented by 1 byte in this embodiment, and can be represented by multiple bytes in other embodiments.
The bytes 0x11, 0x21, 0x31, 0x41, 0x51 and 0x61 correspond to the write command data fields. In this embodiment, the write command data fields are 6 bytes in total. When the I2C interface module 200 receives the last bit of 0x61 byte, that is, when the data received by the I2C interface module 200 reaches the length indicated by the write command length field, the I2C interface module 200 receives the write command packet.
In the embodiment shown in
In another embodiment of the present invention, the value of the write command length field can also be defined in advance to be equal to the length of the write command packet (including the length occupied by the write command length field and the length of the write command data field); the data received by the I2C interface module 200 reaches the length indicated by the write command length field, which means that the I2C interface module 200 receives all the data of the write command packet (including the write command length field and the write command data field).
The value of the write command length field can also be predefined to include some or all of the following data fields: write address byte, write command length field, write command data field, write command packet check code (described below in this document), etc.
The present invention does not limit the content contained in the value of the write command length field, and the preset definition of the content contained in the value of the write command length field only needs to enable the I2C interface module 200 to receive all the data of the write command packet according to the preset definition. The data received by the I2C interface module 200 reaches the length indicated by the write command length field, which means that the I2C interface module 200 receives all the data of the write command packet.
In the embodiment shown in
In the present invention, when the I2C interface module 200 sends the write command packet to the functional module 300, the contents in the write command packet can be modified, added or deleted, which is not limited or specified by the present invention.
When the I2C interface module 200 receives the write status packet and the status information of the write status packet is successful, the I2C interface module 200 stops pulling down the I2C clock line 500 level and returns the I2C ACK to the I2C master controller 100.
When the I2C interface module 200 receives the write status packet and the status information of the write status packet is failed, the I2C interface module 200 stops pulling down the I2C clock line 500 level and returns the I2C NAK to the I2C master controller 100.
It should be noted that the data structure of the write command packet of the present invention is not specifically limited. For example, in some embodiments, the length of the write command length field can be one byte or two or more bytes, and the present invention does not limit the content of the value of the write command length field. Specifically, through the agreement between the I2C master controller 100 and the I2C interface module 200, as long as the write command packet includes the write command length field and the write command data field, and the I2C interface module 200 can receive all the data of the write command packet according to the preset definition of the value of the write command length field. In the following embodiments, the length of the write command length field is still one byte, and the value of the write command length field is equal to the length of the write command data field.
According to the embodiment of the present invention, the write command packet further includes a write command packet check code. If the data received by the I2C interface module 200 reaches the length indicated by the write command length field and the write command packet check code is verified to be correct, the I2C interface module 200 receives the write command packet.
As shown in
The I2C master controller 100 initiates an I2C write operation. After receiving the write command length field (0x06), the I2C interface module 200 can judge that the I2C master controller 100 will sequentially write a write command data field with a length of 6 bytes, i.e., 0x11. 0x21. 0x31, 0x41. 0x51, 0x61, and a write command packet check code (CRC) with a length of 1 byte.
After receiving the write command length field (0x06), the I2C interface module 200 counts the bytes of the received write command data field, and after receiving the last byte 0x61 of the write command data field, it calculates the write command packet check code (CRC) by using the six bytes of 0x11, 0x21, 0x31, 0x41, 0x51 and 0x61. When the I2C interface module 200 receives the write command packet check code (CRC), it compares the received write command packet check code (CRC) with the calculated write command packet check code. If they are consistent, the data received by the I2C interface module 200 reaches the length indicated by the write command length field in the write command packet, and the write command packet check code is verified to be correct, and the I2C interface module 200 receives the write command packet.
The present invention does not limit the data on which the write command packet check code (CRC) is calculated. For example, other data besides the write command data field can also be used for the calculation of the write command packet check code (CRC), including but not limited to the write address byte, the write command length field, and the like.
As shown in
According to the embodiment of the present invention, when the I2C interface module 200 receives the write status packet and the status information of the write status packet is successful, the I2C interface module 200 stops pulling down the I2C clock line level and returns I2C ACK to the I2C master controller 100.
When the I2C interface module 200 receives the write status packet and the status information of the write status packet is failed, the I2C interface module 200 stops pulling down the I2C clock line 500 level and returns I2C NAK to the I2C master controller 100.
The subsequent I2C operation referred to in the present invention refers to the I2C operation before it, and the I2C operation can be an I2C write operation or an I2C read operation.
For example, as shown in
The embodiment shown in
At the {circle around (1)} moment, the I2C interface module 200 receives the write status packet and the status information of the write status packet is successful. The I2C interface module 200 stops pulling down the I2C clock line 500 level and terminates the HOLD state (terminating the continuous low-level state).
At the {circle around (2)} moment, the I2C interface module 200 returns I2C ACK to the I2C master controller 100, and the I2C master controller 100 terminates the I2C operation with a serial number of m (I2C write operation) and initiates the I2C operation with a serial number of m+1 (a subsequent I2C operation), and the subsequent I2C operation is an I2C write operation or I2C read operation.
After the I2C interface module 200 returns the I2C ACK in the I2C operation with a serial number of m, it continues to receive the subsequent I2C operation initiated by the I2C master controller 100 (that is, it returns the I2C ACK after receiving the read address byte or write address byte in the I2C operation with a serial number of m+1 and continues the I2C operation with a serial number of m+1), and repeats the above process, so that the I2C master controller 100 continuously initiates the I2C operation.
According to the embodiment of the present invention, when the I2C interface module 200 receives the write status packet and the status information of the write status packet is failed, the I2C interface module 200 stops pulling down the I2C clock line 500 level and returns I2C NAK to the I2C master controller 100.
If the subsequent I2C operation initiated by the I2C master controller 100 is an I2C write operation, the I2C interface module 200 returns I2C NAK to the I2C master controller 100.
If the subsequent I2C operation initiated by the I2C master controller 100 is an I2C read operation, the I2C interface module 200 returns the status information of the write status packet to the I2C master controller 100.
For example, as shown in
At the {circle around (1)} moment, the I2C interface module 200 receives the write status packet and the status information of the write status packet is failed. The I2C interface module 200 stops pulling down the I2C clock line 500 level and terminates the HOLD state (terminating the continuous low-level state).
At the {circle around (2)} moment, the I2C interface module 200 returns the I2C NAK to the I2C master controller 100, and the I2C master controller 100 terminates the I2C operation (I2C write operation) with a serial number of m.
As shown in
As shown in
The I2C master controller 100 reads the STATUS information of the write status packet while continuing the I2C operation (subsequent I2C operation/I2C read operation) with a serial number of m+1.
After completing the I2C operation with a serial number of m+1 (subsequent I2C operation/I2C read operation), the I2C master controller 100 initiates the I2C operation with a serial number of m+2.
After completing the I2C operation with a serial number of m+1 (subsequent I2C operation/I2C read operation), the I2C interface module 200 continues to receive the I2C operation with a serial number of m+2 initiated by the I2C master controller 100 (that is, the I2C interface module 200 returns to the I2C ACK after receiving the read address byte or write address byte in the I2C operation with a serial number of m+2 and continues the I2C operation with a serial number of m+2), and repeats the above process, and the I2C master controller 100 continuously initiates the I2C operation.
According to the embodiment of the present invention, before the data received by the I2C interface module 200 reaches the length indicated by the write command length field, the I2C interface module 200 receives the I2C START signal or the I2C STOP signal, then the I2C interface module 200 ends the reception of the current write command packet, and the I2C interface module 200 does not receive the write command packet.
If the subsequent I2C operation initiated by the I2C master controller 100 is an I2C write operation, the I2C interface module 200 returns an I2C NAK to the I2C master controller 100.
If the subsequent I2C operation initiated by the I2C master controller 100 is an I2C read operation, the I2C interface module 200 returns status information to the I2C master controller. In this case, the I2C interface module 200 has not received a write command packet, therefore the I2C interface module 200 will not send a write command packet to the functional module 300 or receive a write status packet from the functional module 300. Therefore, the status information returned by the I2C interface module 200 to the I2C master controller 100 does not come from the write status packet. The present invention does not specify the status information returned by the I2C interface module 200 to the I2C master controller 100 in this example, but in some embodiments, the status information may include but is not limited to the information indicating that the I2C interface module 200 has not received the write command packet.
For example, as shown in
The I2C master controller 100 terminates the I2C operation with a serial number of m (I2C write operation), and the I2C master controller 100 initiates the I2C operation with a serial number of m+1 (subsequent I2C operation). The process of the I2C operation (subsequent I2C operation) initiated by the I2C master controller 100 with a serial number of m+1 is the same as that in the above, and will not be described here again.
According to the embodiment of the present invention, when the data received by the I2C interface module 200 reaches the length indicated by the write command length field, but the write command packet check code is verified to be incorrect, the I2C interface module 200 ends the reception of the current write command packet, and the I2C interface module 200 does not receive the write command packet.
If the subsequent I2C operation initiated by the I2C master controller 100 is an I2C write operation, the I2C interface module 200 returns an I2C NAK to the I2C master controller 100.
If the subsequent I2C operation initiated by the I2C master controller 100 is an I2C read operation, the I2C interface module 200 returns status information to the I2C master controller 100. In this case, the I2C interface module 200 has not received a write command packet, therefore the I2C interface module 200 will not send a write command packet to the functional module 300 or receive a write status packet from the functional module 300. Therefore, the status information returned by the I2C interface module 200 to the I2C master controller 100 does not come from the write status packet. The present invention does not specify the status information returned by the I2C interface module 200 to the I2C master controller 100 in this example, but in some embodiments, the status information may include but is not limited to the information indicating that the I2C interface module 200 has not received the write command packet.
For example, as shown in
The I2C master controller 100 terminates the I2C operation with a serial number of m (I2C write operation), and the I2C master controller 100 initiates the I2C operation with a serial number of m+1 (subsequent I2C operation). The process of the I2C operation (subsequent I2C operation) initiated by the I2C master controller 100 with a serial number of m+1 is the same as that in the above, and will not be described here again.
According to an embodiment of the present invention, the I2C interface module 200 includes a timeout timer.
The I2C master controller 100 sends a write command packet through I2C write operation, and the I2C interface module 200 sends the write command packet to the functional module 300 after receiving the write command packet. The I2C interface module 200 continuously waits for the write status packet returned by the functional module 300 and the timeout timer performs timing.
When the I2C interface module 200 does not receive the write status packet before the timeout, the I2C interface module 200 stops pulling down the I2C clock line 500 level after the timeout, and returns the I2C NAK to the I2C master controller 100.
If the subsequent I2C operation initiated by the I2C master controller 100 is an I2C write operation, the I2C interface module 200 returns an I2C NAK to the I2C master controller 100.
If the subsequent I2C operation initiated by the I2C master controller 100 is an I2C read operation, the I2C interface module 200 returns status information to the I2C master controller 100. In this case, the I2C interface module 200 has not received the write status packet, therefore the status information returned by the I2C interface module 200 to the I2C master controller 100 does not come from the write status packet. The present invention does not specify the status information returned by the I2C interface module 200 to the I2C master controller 100 in this example, but in some embodiments, the status information may include, but is not limited to, the information indicating that the I2C interface module 200 did not receive the write status packet before the timeout.
For example, as shown in
When the timer times out at the moment {circle around (2)}, the I2C interface module 200 does not receive the write status packet before the timeout, and after the timeout, the I2C interface module 200 stops pulling down the I2C clock line 500 level, terminates the HOLD state (terminates the continuous low-level state), and returns the I2C NAK to the I2C master controller 100.
For example, as shown in
Second working mode of the data writing method.
According to an embodiment of the present invention, there is provided an I2C data writing method, which uses the I2C interface system provided by the present invention to write data, including:
The functional module 300 receives the write command packet and executes the write command, and returns a write status packet to the I2C interface module 200 after the functional module 300 completes the write command.
After the I2C interface module 200 receives the write command packet,
If the subsequent I2C operation initiated by the I2C master controller 100 is an I2C write operation, and the I2C interface module 200 receives the write status packet returned by the functional module 300 to the I2C interface module 200 and the status information of the write status packet is failed, the I2C interface module 200 returns an I2C NAK to the I2C master controller 100.
The write command packet of the present invention is sent by write operation data bytes (BYTE (1), . . . , BYTE (N), which are shaded), and the write command packet includes a write command length field and a write command data field.
As shown in
After the I2C interface module 200 receives the nth write operation data byte (BYTE (N)) (that is, after the I2C interface module 200 receives the complete write command packet), the I2C interface module 200 may return I2C ACK or I2C NAK to the I2C master controller 100, which is specifically selected according to the agreement between the I2C master controller 100 and the I2C interface module 200. It can be agreed between I2C master controller 100 and I2C interface module 200 that whether it is I2C ACK or I2C NAK after the Nth write operation data byte (BYTE (N)), it indicates the successful reception of the Nth write operation data byte (i.e. the complete write command packet), or it can be agreed that I2C NAK indicates that the Nth write operation data byte (BYTE (N)) is not successfully received (i.e. the complete write command packet is not successfully received). In the following description of the present invention, whether the I2C interface module 200 returns I2C ACK or I2C NAK to the I2C master controller 100 after the Nth write operation data byte (BYTE (N)), it indicates the successful reception of the nth write operation data byte (i.e., the complete write command packet).
After the I2C master controller 100 finishes sending the Nth write operation data byte (BYTE (N)), regardless of whether the I2C interface module 200 returns I2C ACK or I2C NAK to the I2C master controller 100, the I2C master controller 100 terminates the I2C operation with a serial number of m (I2C write operation) and can optionally initiate the I2C operation with a serial number of m+1 (a subsequent I2C operation).
When the I2C operation with a serial number of m+1 (subsequent I2C operation) is an I2C write operation, if the I2C interface module 200 receives the write status packet (a corresponding write status packet in the I2C operation with a serial number of m) returned by the functional module 300 to the I2C interface module 200 and the status information of the write status packet is successful, after the I2C master controller 100 sends the write address byte, the I2C interface module 200 returns an I2C ACK to the I2C master controller 100, and the I2C interface module 200 receives the write operation data bytes sent by the I2C operation (subsequent I2C operation/I2C write operation) with a serial number of m+1 initiated by the I2C master controller 100, as shown in
If the I2C interface module 200 receives the write status packet (a corresponding write status packet in the I2C operation with a serial number of m) returned by the functional module 300 to the I2C interface module 200 and the status information of the write status packet is failed, after the I2C master controller 100 sends the write address byte, the I2C interface module 200 returns the I2C NAK to the I2C master controller 100, and the master controller 100 terminates initiating the m+1 I2C operation (a subsequent I2C operation/I2C write operation), as shown in
According to an embodiment of the present invention, when the data received by the I2C interface module 200 reaches the length indicated by the write command length field, the I2C interface module 200 receives the write command packet. Specifically, the process of determining that the I2C interface module 200 has received the write command packet is the same as the determination process in the first working mode of the data writing method, and the details are not repeated here.
According to the embodiment of the present invention, the write command packet further includes a write command packet check code. When the data received by the I2C interface module 200 reaches the length indicated by the write command length field and the write command packet check code is verified to be correct, the I2C interface module 200 receives the write command packet. Specifically, the process of determining that the I2C interface module 200 has received the write command packet is the same as the determination process in the first working mode of the data writing method, and the details are not repeated here.
According to the embodiment of the present invention, when the subsequent I2C operation initiated by the I2C master controller 100 is an I2C read operation, the I2C interface module 200 returns the status information of the write status packet to the I2C master controller 100 after receiving the write status packet returned by the functional module 300 to the I2C interface module 200.
As shown in
After the I2C interface module 200 receives the Nth write operation data byte (BYTE (N)) (that is, after the I2C interface module 200 receives the complete write command packet), the I2C interface module 200 may return I2C ACK or I2C NAK to the I2C master controller 100.
After the I2C master controller 100 finishes sending the Nth write operation data byte (BYTE (N)), regardless of whether the I2C interface module 200 returns I2C ACK or I2C NAK to the I2C master controller 100, the I2C master controller 100 terminates the I2C operation with a serial number of m (I2C write operation) and can optionally initiate the I2C operation with a serial number of m+1 (a subsequent I2C operation).
When the I2C operation with a serial number of m+1 (subsequent I2C operation) is an I2C read operation, if the I2C interface module 200 receives the write status packet (a corresponding status packet in the I2C operation with a serial number of m) returned by the functional module 300 to the I2C interface module 200, after the I2C master controller 100 sends the read address byte, the I2C interface module 200 returns an I2C ACK to the I2C master controller 100 and returns the status information (STATUS) of the write status packet (the corresponding status packet in the I2C operation with a serial number of m).
According to an embodiment of the present invention, before the data received by the I2C interface module 200 reaches the length indicated by the write command length field, the I2C interface module 200 receives the I2C START signal or the I2C STOP signal, and the I2C interface module 200 terminates the reception of the current write command packet, and the I2C interface module 200 does not receive the write command packet.
If the subsequent I2C operation initiated by the I2C master controller 100 is an I2C write operation, the I2C interface module 200 returns an I2C NAK to the I2C master controller 100.
If the subsequent I2C operation initiated by the I2C master controller 100 is an I2C read operation, the I2C interface module 200 returns status information to the I2C master controller 100.
The process after the I2C master controller 100 initiates the subsequent I2C read operation is the same as that in the first working mode of the data writing method, and will not be described here.
According to the embodiment of the present invention, when the data received by the I2C interface module 200 reaches the length indicated by the write command length field, but the write command packet check code is verified to be incorrect, the I2C interface module 200 ends the reception of the current write command packet, and the I2C interface module 200 does not receive the write command packet.
If the subsequent I2C operation initiated by the I2C master controller 100 is an I2C write operation, the I2C interface module 200 returns an I2C NAK to the I2C master controller 100.
If the subsequent I2C operation initiated by the I2C master controller 100 is an I2C read operation, the I2C interface module 200 returns status information to the I2C master controller 100.
The process after the I2C master controller 100 initiates the subsequent I2C read operation is the same as that in the first working mode of the data writing method, and will not be described here.
According to an embodiment of the present invention, the I2C interface module 200 includes a timeout timer.
The I2C master controller 100 sends a write command packet through I2C write operation, and the I2C interface module 200 sends the write command packet to the functional module 300 after receiving the write command packet. The I2C interface module 200 continuously waits for the write status packet returned by the functional module 300 and the timeout timer performs timing.
When the I2C interface module 200 does not receive the write status packet before the timeout, if the subsequent I2C operation initiated by the I2C master controller 100 is an I2C write operation after the timeout, the I2C interface module 200 returns the I2C NAK to the I2C master controller 100.
When the I2C interface module 200 does not receive the write status packet before the timeout, if the subsequent I2C operation initiated by the I2C master controller 100 is an I2C read operation after the timeout, the I2C interface module 200 returns the status information to the I2C master controller 100.
The process after the I2C master controller 100 initiates the subsequent I2C read operation is the same as that in the first working mode of the data writing method, and will not be described here.
According to an embodiment of the present invention, when the subsequent I2C operation initiated by the I2C master controller 100 is an I2C write operation, if the I2C interface module 200 receives the write status packet returned by the functional module 300 to the I2C interface module 200 and the status information of the write status packet is failed, the I2C interface module 200 returns an I2C NAK to the I2C master controller 100. If the subsequent I2C operation initiated by the I2C master controller 100 is an I2C write operation, the I2C interface module 200 continues to return I2C NAK to the I2C master controller 100. If the subsequent I2C operation initiated by the I2C master controller 100 is an I2C read operation, the I2C interface module 200 returns the status information of the write status packet to the I2C master controller 100, and continues to receive the subsequent I2C operation initiated by the I2C master controller 100 after the I2C read operation.
As shown in
After the I2C interface module 200 receives the nth write operation data byte (BYTE (N)) (that is, after the I2C interface module 200 receives the complete write command packet), the I2C interface module 200 may return I2C ACK or I2C NAK to the I2C master controller 100.
After the I2C master controller 100 finishes sending the nth write operation data byte (BYTE (N)), regardless of whether the I2C interface module 200 returns I2C ACK or I2C NAK to the I2C master controller 100, the I2C master controller 100 terminates the I2C operation with a serial number of m (I2C write operation) and can optionally initiate the I2C operation with a serial number of m+1 (a subsequent I2C operation).
When the I2C operation with a serial number of m+1 (subsequent I2C operation) is an I2C write operation, if the I2C interface module 200 receives the write status packet (a corresponding status packet in the I2C operation with a serial number of m) returned by the functional module 300 to the I2C interface module 200 and the status information of the write status packet is failed, after the I2C master controller 100 sends the write address byte, the I2C interface module 200 returns an I2C NAK to the I2C master controller 100, and the master controller 100 terminates initializing the I2C operation of m+1 (a subsequent I2C operation/I2C write operation), and the I2C master controller 100 may select to initiate the I2C operation with a serial number of m+2 (a subsequent I2C operation).
If the I2C operation (a subsequent I2C operation) with a serial number of m+2 initiated by the I2C master controller 100 is an I2C write operation, the I2C interface module 200 returns an I2C NAK to the I2C master controller 100, and the master controller 100 terminates initializing the I2C operation of m+2 (a subsequent I2C operation/I2C write operation), as shown in
If the I2C operation (subsequent I2C operation) initiated by the I2C master controller 100 with a serial number of m+2 is an I2C read operation, after receiving the read address byte, the I2C interface module 200 returns an I2C ACK to the I2C master controller 100, and returns the status information (STATUS) of the write status packet (corresponding status packet during the I2C operation with a serial number of m) to the I2C master controller 100. After the I2C operation with a serial number of m+2 (subsequent I2C operation/I2C read operation), the I2C interface module 200 continues to receive the I2C operation with a serial number of m+3 (a subsequent I2C operation) initiated by the I2C master controller 100 (that is, the I2C interface module 200 returns to I2C ACK after receiving the read address byte or write address byte in the I2C operation with a serial number of m+3 and continues the I2C operation with a serial number of m+3), as shown in
According to an embodiment of the present invention, when the subsequent I2C operation initiated by the I2C master controller 100 is an I2C write operation, if the I2C interface module 200 does not receive the write status packet returned by the functional module 300 to the I2C interface module 200, the I2C interface module 200 pulls down the I2C clock line 500 level.
If the I2C interface module 200 receives the write status packet returned by the functional module 300 to the I2C interface module 200 and the status information of the write status packet is successful, the I2C interface module 200 stops pulling down the I2C clock line 500 level and receives the subsequent I2C write operation initiated by the I2C master controller 100.
If the I2C interface module 200 receives the write status packet returned by the functional module 300 to the I2C interface module 200 and the status information of the write status packet is failed, the I2C interface module 200 stops pulling down the I2C clock line 500 level and returns the I2C NAK to the I2C master controller 100.
As shown in
After the I2C interface module 200 receives the nth write operation data byte (BYTE (N)) (that is, after the I2C interface module 200 receives the complete write command packet), the I2C interface module 200 may return I2C ACK or I2C NAK to the I2C master controller 100.
After the I2C master controller 100 finishes sending the nth write operation data byte (BYTE (N)), regardless of whether the I2C interface module 200 returns I2C ACK or I2C NAK to the I2C master controller 100, the I2C master controller 100 terminates the I2C operation with a serial number of m (I2C write operation) and may select to initiate the I2C operation with a serial number of m+1 (a subsequent I2C operation).
When the I2C operation (a subsequent I2C operation) with a serial number of m+1 initiated by the I2C master controller 100 is an I2C write operation, if the I2C interface module 200 does not receive the write status packet (a corresponding write status packet in the I2C operation with a serial number of m) returned by the functional module 300 to the I2C interface module 200, the I2C interface module 200 pulls down the I2C clock line level after receiving the write address byte, and suspends the progress of the I2C operation with a serial number of m+1.
If the I2C interface module 200 receives the write status packet (a corresponding write status packet in the I2C operation with a serial number of m) returned by the functional module 300 to the I2C interface module 200 and the status information of the write status packet is successful, the I2C interface module 200 stops pulling down the I2C clock line 500 level, returns the I2C ACK to the I2C master controller 100, and receives the I2C operation with a serial number of m+1 initiated by the I2C master controller 100 (subsequent I2C operation/I2C write operation), as shown in
If the I2C interface module 200 receives the write status packet (corresponding write status packet in the I2C operation with a serial number of m) returned by the functional module 300 to the I2C interface module 200 and the status information of the write status packet is failed, the I2C interface module 200 stops pulling down the I2C clock line 500 level and returns an I2C NAK to the I2C master controller 100, and the master controller 100 stops initiating the I2C operation of m+1 (A subsequent I2C operation/I2C write operation), as shown in
According to an embodiment of the present invention, when the subsequent I2C operation initiated by the I2C master controller 100 is an I2C read operation, if the I2C interface module 200 does not receive the write status packet returned by the functional module 300 to the I2C interface module 200, the I2C interface module 200 pulls down the I2C clock line level.
If the I2C interface module 200 receives the write status packet returned by the functional module 300 to the I2C interface module 200, the I2C interface module 200 stops pulling down the I2C clock line level and returns the status information of the write status packet to the I2C master controller 100.
As shown in
If the I2C interface module 200 receives the write status packet (a corresponding write status packet in the I2C operation with a serial number of m) returned by the functional module 300 to the I2C interface module 200, the I2C interface module 200 stops pulling down the I2C clock line level, returns I2C ACK to the I2C master controller 100, and returns the status information (STATUS) of the write status packet to the I2C master controller 100.
First working mode of data reading method.
According to an embodiment of the present invention, there is provided an I2C data reading method, which uses the I2C interface system provided by the present invention to read data, including the following steps:
The functional module 300 receives the read command packet and executes the read command. After the functional module 300 completes the read command, it returns a read data packet to the I2C interface module 200, which includes read data.
According to an embodiment of the present invention, read data includes data read from the functional module 300, or read status information generated by the functional module 300 executing a read command, or both data read from the functional module 300 and read status information generated by the functional module 300 executing a read command.
When the I2C interface module 200 receives the read data packet, the I2C interface module 200 stops pulling down the I2C clock line level.
The read command packet of the present invention is transmitted by write operation data bytes (BYTE (1), . . . , BYTE (N), shaded) as shown in
With reference to
The read command packet includes a read command length field and a read command data field.
0x06 bytes correspond to the read command length field, which is represented by 1 byte in this embodiment, and can be represented by multiple bytes in other embodiments.
Bytes 0x11, 0x21, 0x31, 0x41, 0x51 and 0x61 correspond to the read command data fields. In this embodiment, the read command data fields are 6 bytes in total. When the I2C interface module 200 receives the last bit of 0x61 byte, that is, when the data received by the I2C interface module 200 reaches the length indicated by the read command length field, the I2C interface module 200 receives the read command packet.
In the embodiment shown in
In another embodiment of the present invention, the value of the read command length field can also be predefined to be equal to the length of the read command packet (including the length occupied by the read command length field and the length of the read command data field), and the data received by the I2C interface module 200 reaches the length indicated by the read command length field, which means that the I2C interface module 200 receives all the data of the read command packet (including the read command length field and the read command data field).
The value of the read command length field can also be defined in advance to include some or all of the following data fields: write address byte, read command length field, read command data field, read command packet check code (described below in this document), etc.
The present invention does not limit the content contained in the value of the read command length field, and the preset definition of the content contained in the value of the read command length field only needs to enable the I2C interface module 200 to receive all the data of the read command packet according to the preset definition, and the data received by the I2C interface module 200 reaching the length indicated by the read command length field means that the I2C interface module 200 receives all the data of the read command packet.
In the following embodiments, the length of the read command length field is still one byte, and the value of the read command length field is equal to the length of the read command data field.
In the embodiment shown in
In the present invention, when the I2C interface module 200 sends the read command packet to the functional module 300, the contents in the read command packet can be modified, added or deleted, and the present invention does not limit or stipulate this. The I2C interface module 200 receives the read data packet, and returns I2C ACK or I2C NAK to the I2C master controller 100 after the I2C interface module 200 stops pulling down the I2C clock line level.
The present invention does not restrict or stipulate that the I2C interface module 200 returns I2C ACK or I2C NAK to the I2C master controller 100 after receiving the read data packet and stopping pulling down the I2C clock line level. As an embodiment, the I2C interface module 200 can choose that when the I2C interface module 200 receives the read data packet and the status information (read data) of the read data packet is successful, the I2C interface module 200 stops pulling down the I2C clock line 500 level and returns an I2C ACK to the I2C master controller 100, and when the I2C interface module 200 receives the read data packet and the status information of the read data packet is failed, the I2C interface module 200 stops pulling down the I2C clock line 500 level and returns an I2C NAK to the I2C master controller 100.
It should be noted that both the write command packet and the read command packet of the present invention are initiated by the I2C master controller 100 and sent to the I2C interface module 200 through write operation data bytes (BYTE (1), . . . , BYTE (N)), and the I2C interface module 200 is only the transmitter of the write command packet or the read command packet, not the final receiver or the command executor. The functional module 300 can identify whether the received command packet is a read command packet or a write command packet. When the functional module 300 identifies that the received command packet is a read command packet, it needs to return a read packet to the I2C interface module 200, and when the functional module 300 identifies that the received command packet is a write command packet, it needs to return a write status packet to the I2C interface module 200.
In a specific embodiment, the I2C master controller 100 initiates an I2C write operation, and after receiving the read command length field (0x06), the I2C interface module 200 can judge that the I2C master controller 100 will sequentially write the read command data fields with a total length of 6 bytes, namely 0x11, 0x21, 0x31, 0x41, 0x51 and 0x61.
According to the embodiment of the present invention, the read command packet further includes a read command packet check code. If the data received by the I2C interface module 200 reaches the length indicated by the read command length field and the check code of the read command packet is verified to be correct, the I2C interface module 200 receives the read command packet.
Specifically, as shown in
The I2C master controller 100 initiates an I2C write operation. After receiving the read command length field (0x06), the I2C interface module 200 can judge that the I2C master controller 100 will sequentially write a read command data field with a length of 6 bytes, namely 0x11, 0x21, 0x31, 0x41, 0x51 and 0x61, and a read command packet check code (CRC) with a length of 1 byte.
After receiving the read command length field (0x06), the I2C interface module 200 counts the bytes of the received read command data field, and after receiving the last byte 0x61 of the read command data field, calculates the read command packet check code (CRC) by using the six bytes of 0x11, 0x21, 0x31, 0x41, 0x51 and 0x61. When the I2C interface module 200 receives the read command packet check code (CRC), it compares the received read command packet check code (CRC) with the calculated read command packet check code. If they are consistent, the data received by the I2C interface module 200 reaches the length indicated by the read command length field, and the read command packet check code is verified to be correct, and the I2C interface module 200 receives the read command packet.
The present invention does not limit the data on which the calculation of the read command packet check code (CRC) is based. For example, other data besides the read command data field can also be used for the calculation of the read command packet check code (CRC), including but not limited to the write address byte, the read command length field and the like.
As shown in
According to the embodiment of the present invention, when the I2C interface module 200 receives the read data packet, the I2C interface module 200 stops pulling down the I2C clock line 500 level and returns I2C ACK or I2C NAK to the I2C master controller 100.
If the subsequent I2C operation initiated by the I2C master controller 100 is an I2C write operation, the I2C interface module 200 returns an I2C NAK to the I2C master controller 100.
If the subsequent I2C operation initiated by I2C master controller 100 is an I2C read operation, I2C interface module 200 returns read data to I2C master controller 100.
As shown in
At the moment {circle around (1)}, the I2C interface module 200 receives the read data packet, and the I2C interface module 200 stops pulling down the I2C clock line 500 level and terminates the HOLD state (terminating the continuous low state).
At the moment {circle around (2)}, the I2C interface module 200 returns I2C ACK or I2C NAK to the I2C master controller 100, and the I2C master controller 100 terminates the I2C operation with a serial number of m, and the I2C master controller 100 initiates the I2C operation with a serial number of m+1 (a subsequent I2C operation).
If the I2C operation with a serial number of m+1 (a subsequent I2C operation) initiated by the I2C master controller 100 is an I2C write operation, the I2C interface module 200 returns an I2C NAK to the I2C master controller 100 after receiving the write address byte, so that the I2C operation with a serial number of m+1 (a subsequent I2C operation/I2C write operation) is terminated, as shown in
If the I2C operation with a serial number of m+1 (a subsequent I2C operation) initiated by the I2C master controller 100 is an I2C read operation, after the I2C interface module 200 receives the read address byte, the I2C interface module 200 returns an I2C ACK to the I2C master controller 100 and continues to return the read data (DATA), so that the I2C master controller 100 can continue to perform the I2C operation with a serial number of m+1 (a subsequent I2C operation/I2C read operation).
When the I2C master controller 100 continues to execute the I2C operation with a serial number of m+1 (subsequent I2C operation/I2C read operation), it reads data (DATA), and the I2C interface module 200 continues to receive the I2C operation of m+2 initiated by the I2C master controller 100 after completing the I2C operation with a serial number of m+1 ((a subsequent I2C operation/I2C read operation) (which means that the I2C interface module 200 returns to the I2C ACK after receiving the read address byte or the write address byte in the I2C operation with a serial number of m+2, and continues the I2C operation with the serial number m+2), as shown in
According to the embodiment of the present invention, if the I2C interface module 200 receives the I2C START signal or the I2C STOP signal before the data received by the I2C interface module 200 reaches the length indicated by the read command length field, the I2C interface module 200 ends the reception of the current read command packet, and the I2C interface module 200 does not receive the read command packet.
If the subsequent I2C operation initiated by the I2C master controller 100 is an I2C write operation, the I2C interface module 200 returns an I2C NAK to the I2C master controller 100.
If the subsequent I2C operation initiated by the I2C master controller 200 is an I2C read operation, the I2C interface module 200 returns status information to the I2C master controller 100. In this embodiment, the I2C interface module 200 has not received the read command packet, therefore the I2C interface module 200 will not send the read command packet to the functional module 300, nor will it receive the read data packet from the functional module 300. Therefore, the status information returned by the I2C interface module 200 to the I2C master controller 100 does not come from the read data packet. The present invention does not specify the status information returned by the I2C interface module 200 to the I2C master controller 100 in this embodiment, but in some embodiments, the status information may include but is not limited to the information indicating that the I2C interface module 200 has not received the read command packet.
According to the embodiment of the present invention, when the data received by the I2C interface module 200 reaches the length indicated by the read command length field, but the check code of the read command packet is verified to be incorrect, the I2C interface module 200 ends the reception of the current read command packet, and the I2C interface module 200 does not receive the read command packet.
If the subsequent I2C operation initiated by the I2C master controller 100 is an I2C write operation, the I2C interface module 200 returns an I2C NAK to the I2C master controller 100.
If the subsequent I2C operation initiated by the I2C master controller 100 is an I2C read operation, the I2C interface module 200 returns status information to the I2C master controller 100. In this embodiment, the I2C interface module 200 has not received the read command packet, therefore the I2C interface module 200 will not send the read command packet to the functional module 300, nor will it receive the read data packet from the functional module 300. Therefore, the status information returned by the I2C interface module 200 to the I2C master controller 100 does not come from the read data packet. The present invention does not specify the status information returned by the I2C interface module 200 to the I2C master controller 100 in this embodiment, but in some embodiments, the status information may include but is not limited to the information indicating that the I2C interface module 200 has not received the read command packet.
According to an embodiment of the present invention, the I2C interface module 200 includes a timeout timer.
The I2C master controller 100 sends a read command packet through an I2C write operation. After receiving the read command packet, the I2C interface module 200 pulls down the I2C clock line 500 level and sends the read command packet to the functional module 300. The I2C interface module 200 continues to wait for the read data packet returned by the functional module 300 and the timeout timer counts.
When the I2C interface module 200 does not receive the read data packet before the timeout, the I2C interface module 200 stops pulling down the I2C clock line level after the timeout, and returns the I2C NAK to the I2C master controller.
If the subsequent I2C operation initiated by I2C master controller 200 is an I2C write operation, I2C interface module 200 returns I2C NAK to I2C master controller 100.
If the subsequent I2C operation initiated by the I2C master controller 100 is an I2C read operation, the I2C interface module 200 returns status information to the I2C master controller 100. In this embodiment the I2C interface module 200 has not received the read data packet, therefore the status information returned by the I2C interface module 200 to the I2C master controller 100 does not come from the read data packet. The present invention does not specify the status information returned by the I2C interface module 200 to the I2C master controller 100 in this embodiment, but in some embodiments, the status information may include, but is not limited to, the information indicating that the I2C interface module 200 did not receive the read data packet before the timeout.
Second working mode of data reading method.
According to an embodiment of the present invention, there is provided an I2C data reading method, which uses the I2C interface system provided by the present invention to read data, including the following steps:
The functional module 300 receives the read command packet and executes the read command. After the functional module 300 completes the read command, it returns a read data packet to the I2C interface module 200, which includes read data.
According to an embodiment of the present invention, read data includes data read from the functional module 300, or read status information generated by the functional module 300 executing a read command, or both data read from the functional module 300 and read status information generated by the functional module 300 executing a read command.
After the I2C interface module 200 receives the read command packet, if the subsequent I2C operation initiated by the I2C master controller 100 is an I2C write operation, and the I2C interface module 200 receives the read data packet returned by the functional module 300 to the I2C interface module 200, the I2C interface module 200 returns an I2C NAK to the I2C master controller 100.
If the subsequent I2C operation initiated by I2C master controller 100 is an I2C read operation, and I2C interface module 200 receives the read data packet returned by functional module 300 to an I2C interface module 200, I2C interface module 200 returns the read data to I2C master controller 100.
The read command packet of the present invention is sent through write operation data bytes (BYTE (1), . . . , BYTE (N), which are shaded), and the read command packet includes the number of read command length fields and read command data fields.
As shown in
After the I2C interface module 200 receives the nth write operation data byte (BYTE (N)) (that is, after the I2C interface module 200 receives the complete read command packet), the I2C interface module 200 may return I2C ACK or I2C NAK to the I2C master controller 100, which is selected specifically by the agreement between the I2C master controller 100 and the I2C interface module 200. It can be agreed between I2C master controller 100 and I2C interface module 200 that after the Nth write operation data byte (BYTE (N)), whether it is I2C ACK or I2C NAK, it indicates the successful reception of the nth write operation data byte (i.e. the complete read command packet), or it can be agreed that I2C NAK indicates that the Nth write operation data byte (BYTE (N)) is not successfully received (i.e. the complete read command packet is not successfully received). In the following description of the present invention, whether the I2C interface module 200 returns I2C ACK or I2C NAK to the I2C master controller 100 after the Nth write operation data byte (BYTE (N)), it indicates the successful reception of the Nth write operation data byte (i.e., the complete read command packet). After the I2C master controller 100 finishes sending the data byte (BYTE (N)) of the Nth write operation, regardless of whether the I2C interface module 200 returns I2C ACK or I2C NAK to the I2C master controller 100, the I2C master controller 100 terminates the I2C operation with a serial number of m (I2C write operation) and can choose to continue to initiate the I2C operation with a serial number of m+1 (subsequent I2C operation).
If the I2C operation with a serial number of m+1 (a subsequent I2C operation) is an I2C write operation, and the I2C interface module 200 receives the read data packet (a corresponding read data packet during the I2C operation with a serial number of m) returned by the functional module 300 to the I2C interface module 200, the I2C interface module 200 returns an I2C NAK to the I2C master controller 100 after receiving the write address byte, and the master controller 100 stops initiating the I2C operation with a serial number of m+1 (a subsequent I2C operation)
If the I2C operation with a serial number of m+1 (subsequent I2C operation) is an I2C read operation, and the I2C interface module 200 receives the read data packet (corresponding read data packet during the I2C operation with a serial number of m) returned by the functional module 300 to the I2C interface module 200, the I2C interface module 200 returns an I2C ACK to the I2C master controller 100 after receiving the read address byte, and returns the read data (DATA) to the I2C master controller 100. The I2C master controller can choose to initiate the I2C operation with a serial number of m+2 after the I2C read operation with a serial number of m+1, and the I2C interface module 200 continues to receive the I2C operation with a serial number of m+2 initiated by the I2C master controller 100 after the I2C read operation with a serial number of m+1 (which means that the I2C interface module 200 returns I2C ACK after receiving the read address byte or write address byte in the I2C operation with a serial number of m+2 and continues the I2C operation with a serial number of m+2), as shown in
According to the embodiment of the present invention, when the data received by the I2C interface module 200 reaches the length indicated by the read command length field, the I2C interface module 200 receives the read command packet. Specifically, the process of determining that the I2C interface module 200 receives the read command packet is the same as the determination process in the first working mode of the data reading method, which is not repeated here.
According to the embodiment of the present invention, the read command packet also includes a read command packet check code. When the data received by the I2C interface module 200 reaches the length indicated by the read command length field and the read command packet check code is verified to be correct, the I2C interface module receives the read command packet. Specifically, the process of determining that the I2C interface module 200 receives the read command packet is the same as that in the first working mode of the data reading method, which is not repeated here.
According to the embodiment of the present invention, before the data received by the I2C interface module 200 reaches the length indicated by the read command length field, the I2C interface module 200 receives the I2C START signal or the I2C STOP signal, therefore the I2C interface module 200 ends the reception of the current read command packet, and the I2C interface module 200 does not receive the read command packet.
If the subsequent I2C operation initiated by the I2C master controller 100 is an I2C write operation, the I2C interface module 200 returns an I2C NAK to the I2C master controller.
If the subsequent I2C operation initiated by the I2C master controller 100 is an I2C read operation, the I2C interface module 200 returns status information to the I2C master controller.
The process after the I2C master controller 100 initiates the subsequent I2C read operation is the same as that in the first working mode of the data reading method, and will not be described here.
According to the embodiment of the present invention, when the data received by the I2C interface module 200 reaches the length indicated by the read command length field, but the check code of the read command packet is verified to be incorrect, the I2C interface module 200 ends the reception of the current read command packet, and the I2C interface module 200 does not receive the read command packet.
If the subsequent I2C operation initiated by the I2C master controller 100 is an I2C write operation, the I2C interface module 200 returns an I2C NAK to the I2C master controller 100.
If the subsequent I2C operation initiated by the I2C master controller 100 is an I2C read operation, the I2C interface module 200 returns status information to the I2C master controller 100.
The process after the I2C master controller 100 initiates the subsequent I2C read operation is the same as that in the first working mode of the data reading method, and will not be described here.
According to an embodiment of the present invention, the I2C interface module 200 includes a timeout timer.
The I2C master controller 100 sends a read command packet through an I2C write operation, and the I2C interface module 200 sends the read command packet to the functional module 300 after receiving the read command packet. The I2C interface module 200 continuously waits for the read data packet returned by the functional module 300 and the timeout timer performs timing.
When the I2C interface module 200 does not receive the read data packet before the timeout, if the subsequent I2C operation initiated by the I2C master controller 100 is an I2C write operation after the timeout, the I2C interface module 200 returns the I2C NAK to the I2C master controller 100.
When the I2C interface module 200 does not receive the read data packet before the timeout, if the subsequent I2C operation initiated by the I2C master controller 100 is an I2C read operation after the timeout, the I2C interface module 200 returns the status information to the I2C master controller 100.
The process after the I2C master controller 100 initiates the subsequent I2C read operation is the same as that in the first working mode of the data reading method, and will not be described here.
As shown in
If the I2C operation (a subsequent I2C operation) with a serial number of m+2 initiated by the I2C master controller 100 is an I2C write operation, the I2C interface module 200 continues to return I2C NAK to the I2C master controller 100, and the master controller 100 terminates initiating the I2C operation of m+2 (a subsequent I2C operation/I2C write operation), as shown in
If the I2C operation with a serial number of m+2 initiated by the I2C master controller 100 (a subsequent I2C operation) is an I2C read operation, after the I2C interface module 200 receives the read address byte, the I2C interface module 200 returns an I2C ACK to the I2C master controller 100 and continues to return the read data (DATA) contained in the corresponding read data packet during the I2C operation with a serial number of m. The I2C master controller can choose to initiate the I2C operation with a serial number of m+3 after the I2C read operation with a serial number of m+2, and the I2C interface module 200 continues to receive the I2C operation with a serial number of m+3 initiated by the I2C master controller 100 (that is, the I2C interface module 200 returns I2C ACK after receiving the read address byte or write address byte in the I2C operation with a serial number of m+3, and continues the I2C operation with a serial number of m+3), as shown in
According to an embodiment of the present invention, when the subsequent I2C operation initiated by the I2C master controller 100 is an I2C write operation, if the I2C interface module 200 does not receive the read data packet returned by the functional module 300 to the I2C interface module 200, the I2C interface module pulls down the I2C clock line level.
If the I2C interface module 200 receives the read data packet returned by the functional module 300 to the I2C interface module 200, the I2C interface module 200 stops pulling down the I2C clock line level, and the I2C interface module 200 returns the I2C NAK to the I2C master controller 100.
When the subsequent I2C operation initiated by the I2C master controller 100 is an I2C read operation, if the I2C interface module 200 does not receive the read data packet returned by the functional module 300 to the I2C interface module 100, the I2C interface module 200 pulls down the I2C clock line level.
If the I2C interface module 200 receives the read data packet returned by the functional module 300 to the I2C interface module 200, the I2C interface module 200 stops pulling down the I2C clock line level and returns the read data to the I2C master controller 100.
As shown in
After the I2C interface module 200 receives the nth write operation data byte (BYTE (N)) (that is, after the I2C interface module 200 receives the complete read command packet), the I2C interface module 200 may return I2C ACK or I2C NAK to the I2C master controller 100.
After the I2C master controller 100 finishes sending the Nth read command data byte (BYTE (N)), regardless of whether the I2C interface module 200 returns I2C ACK or I2C NAK to the I2C master controller 100, the I2C master controller 100 terminates the I2C operation with a serial number of m (I2C write operation) and can choose to continue to initiate the I2C operation with a serial number of m+1 (a subsequent I2C operation).
When the I2C operation (a subsequent I2C operation) with a serial number of m+1 initiated by the I2C master controller 100 is an I2C write operation, if the I2C interface module 200 does not receive the read data packet (corresponding read data packet in the I2C operation with a serial number of m) returned by the functional module 300 to the I2C interface module 200, the I2C interface module 200 pulls down the I2C clock line 500 level after receiving the write address byte, and suspends the progress of the I2C operation with a serial number of m+1 and waits for receiving the read data packet.
If the I2C interface module 200 receives the read data packet (corresponding read data packet in the I2C operation with a serial number of m) returned by the functional module 300 to the I2C interface module 200, the I2C interface module 200 stops pulling down the I2C clock line 500 level, and the I2C interface module 200 returns the I2C NAK to the I2C master controller 100, and the master controller 100 stops initiating the I2C operation of m+1 (subsequent I2C operation/I2C write operation), as shown in
As shown in
If the I2C interface module 200 receives the read DATA packet (corresponding read DATA packet in the I2C operation with a serial number of m) returned by the functional module 300 to the I2C interface module 200, the I2C interface module 200 stops pulling down the I2C clock line level and returns the I2C ACK and the read data (DATA) contained in the read data packet to the I2C master controller 100, and the I2C master controller 100 terminates the I2C operation with a serial number of m+1 after receiving the read data (DATA).
Although the embodiments of the present invention have been shown and described above, it can be understood that the above-mentioned embodiments are exemplary and cannot be understood as limitations of the present invention, and changes, modifications, substitutions and variations made to the above-mentioned embodiments by those skilled in the art within the scope of the present invention belong to the protection scope of the present invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202311037009.5 | Aug 2023 | CN | national |
