Patent Application
20190227743
The present disclosure generally relates to a storage device, and more specifically, relates to identifying a read operation for a storage device based on a workload of a host system.
A storage device may include one or more memory components that store data. For example, a solid-state drive (SSD) may include memory devices such as non-volatile memory devices. The SSD may further include an SSD controller that may manage each of the memory devices and allocate data to be stored at the memory devices. A host system may utilize the SSD and request data from the SSD. The SSD controller may be used to retrieve data from the corresponding memory devices and return the retrieved data to the host system.
The present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various implementations of the disclosure.
Aspects of the present disclosure are directed to identifying a read operation for a storage device based on a workload of a host system. In general, a host system may utilize a storage device that includes one or more memory devices. The host system may provide data to be stored at the storage device and may subsequently retrieve data stored at the storage device. The data may be stored and read from the memory devices within the storage device. The workload of the host system may be a group of read requests provided by the host system to retrieve data from the memory devices.
An example of a storage device is a solid-state drive (SSD) that includes non-volatile memory and a controller to manage the non-volatile memory. The controller may identify or indicate an operation to be used by the non-volatile memory to retrieve data that is stored at a particular location of the non-volatile memory. The data stored at the non-volatile memory may be organized at memory pages (i.e., memory cells) that correspond to logical units of the non-volatile memory. Each of the memory pages may be accessed by a word line and a bit line of the non-volatile memory. For example, the controller may provide an operation to assert (e.g., provide a voltage input) at particular word line and a particular bit line to retrieve data stored at a corresponding memory page of the non-volatile memory. As a result, data may be retrieved from memory pages of the non-volatile memory by providing voltage inputs at word lines and bit lines.
The data at the non-volatile memory may be retrieved by using different read operations that are used by the non-volatile memory to read data from within the memory pages of the non-volatile memory. For example, a first type of read operation may be a word line ramp read operation that corresponds to a varying or increasing voltage input that is applied at a word line while different bit lines associated with the word line are also asserted. Such a word line ramp read operation may result in the reading or retrieving of data stored at each memory page that is accessed by the same word line that was asserted and the various different bit lines that were asserted. Thus, the data corresponding to multiple memory pages may be retrieved by using the word line ramp read operation. A second type of read operation may be a discrete read operation that corresponds to asserting the word line by applying a specified voltage input at the word line and asserting a single bit line. Such a discrete read operation may result in the reading or retrieving of data stored at a single memory page (or portion of a page) that is accessed by the word line and the single bit line. Thus, the data corresponding to a single memory page (or portion) may be retrieved by using the discrete read operation.
As such, the use of the word line ramp read operation may result in retrieving data from more memory pages than the discrete read operation, but the word line ramp read operation may take a longer period of time to be performed than a single discrete read operation. However, the use of the word line ramp read operation to retrieve data from each memory page of a particular word line may use less cumulative time than the performance of the discrete read operations to retrieve data from each memory page of the particular word line since the word line may be separately asserted for each instance of a bit line being asserted for each discrete read operation. Thus, if a host system provides a read request for data stored at the non-volatile memory, then a particular read operation of the non-volatile memory may result in the retrieving of data faster than another read operation that is performed by the non-volatile memory. For example, if the host system is providing read requests for deterministic data (e.g., data stored at various memory pages or sequential memory pages on the same word line), then the word line ramp read operation may be used to retrieve the requested data in less time than the discrete read operation for each bit line associated with the word line. Alternatively, if the host system is providing read requests for random data (e.g., for data accessed at different word lines of the non-volatile memory), then the discrete read operation may be used to retrieve the requested data faster than the word line ramp read operation as data from a single memory page (rather than multiple memory pages associated with the word line) may be requested. However, the non-volatile memory may not be aware of the types of read requests being provided by the host system and may thus not perform the word line ramp read operation or the discrete read operation when one of the types of read operations may retrieve requested data in less time.
Aspects of the present disclosure address the above and other deficiencies by identifying a particular read operation for the non-volatile memory device of a solid-state drive to perform based on a workload of the host system. For example, the controller of the solid-state drive may identify whether the workload of the host system is a deterministic workload (e.g., the host system has been requesting data stored at sequential memory pages or memory pages from a group of sequential memory pages) or if the workload of the host system is a random workload (e.g., the host system has been requesting data that is stored at memory pages at random locations or different word lines). If the workload from the host system is a deterministic workload, then the controller may indicate for the non-volatile memory to perform the word line ramp read operation to retrieve data stored at each of the memory pages accessed by a particular word line. Otherwise, if the workload from the host system is a random workload, then the controller may indicate for the non-volatile memory to perform the discrete read operation to retrieve data from particular memory pages accessed by a word line and a particular bit line.
The use of the controller of the solid-state drive to identify a type of read operation to be performed by the non-volatile memory when retrieving data may improve the performance of the solid-state drive. For example, the word line ramp read operation may be used when the workload of the host system is deterministic as the memory pages accessed by a single asserted word line may be subsequently used by the host system. Thus, a single word line ramp read operation may be used to retrieve the memory pages as opposed to multiple discrete read operations to retrieve the memory pages, resulting in the retrieving of the memory pages expected to be used or requested by the host system in less time. Furthermore, the discrete read operation may be used to retrieve a memory page as opposed to the word line ramp read operation when the workload of the host system is random as the data requested by the host system may be accessed by asserting different word lines of the non-volatile memory and memory pages across a single word line may include data that is not expected to be used or requested by the host system. As a result, the read performance of the solid-state drive may be improved as read operations from a host system are performed in less time.
The host system 120 may be a computing device such as a desktop computer, laptop computer, network server, mobile device, or such computing device that includes a memory and a processing device. The host system 120 may include or be coupled to the storage device 110 so that the host system 120 may read data from or write data to the storage device 110. For example, the host system 120 may be coupled to the storage device 110 via a physical host interface. Examples of a physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, universal serial bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), etc. The physical host interface may be used to transmit data between the host system 120 and the storage device 110. The host system 120 may further utilize an NVM Express (NVMe) interface to access the memory devices 112A to 112N when the storage device 110 is coupled with the host system 120 by the PCIe interface.
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The controller 111 may communicate with the memory devices 112A to 112N to perform operations such as reading data, writing data, or erasing data at the memory devices 112A to 112N and other such operations. The controller 111 may include hardware such as one or more integrated circuits and/or discrete components, software such as firmware or other instructions, or a combination thereof. In general, the controller 111 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 112A to 112N. The controller 111 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between a logical block address and a physical block address that are associated with the memory devices 112A to 112N.
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The storage device 110 may include additional circuitry or components that are not illustrated. For example, the storage device 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., a row decoder and a column decoder) that may receive an address from the controller 111 and decode the address to access the memory devices 112A to 112N.
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The host interface circuitry 214 may be coupled to host-memory translation circuitry 216. The host interface circuitry 214 may interface with a host system. In general, the host interface circuitry 214 may be responsible for converting command packets received from the host system into command instructions for the host-memory translation circuitry 216 and for converting host-memory translation responses into host system commands for transmission to the requesting host system.
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The memory management circuitry 218 may be coupled to the host-memory translation circuitry 216 and the switch 220. The memory management circuitry 218 may control a number of memory operations including, but not limited to, initialization, wear leveling, garbage collection, reclamation, and/or error detection/correction. While the memory management circuitry 218 may include a processor 228, a number of embodiments of the present disclosure provide for control of memory operations in circuitry (e.g., without relying on the execution of instructions such as software and/or firmware) by the processor 228. Memory management circuitry 218 may include block management circuitry 240 to retrieve data from the volatile memory 212 and/or memory units 250 of non-volatile memory. For example, the block management circuitry 240 may retrieve information such as identifications of valid data blocks of the memory units 250, erase counts, and other status information of the memory units 250 to perform memory operations.
The switch 220 may be coupled to the host-memory translation circuitry 216, the memory management circuitry 218, the non-volatile memory control circuitry 222, and/or the volatile memory control circuitry 224. The switch 220 may include and/or be coupled to a number of buffers. For example, the switch 220 may include internal static random access memory (SRAM) buffers (ISBs) 225. The switch may be coupled to DRAM buffers 227 that are included in the volatile memory 212. In some embodiments, the switch 220 may provide an interface between various components of the controller 200. For example, the switch 220 may account for variations in defined signaling protocols that may be associated with different components of the controller 200 in order to provide consistent access and implementation between different components.
The non-volatile memory control circuitry 222 may store information corresponding to a received read command at one of the buffers (e.g., the ISBs 225 or the buffer 227). Furthermore, the non-volatile memory control circuitry 222 may retrieve the information from one of the buffers and write the information to a corresponding memory unit 250 of the non-volatile memory. The number of memory units 250 may be coupled to the non-volatile memory control circuitry 222 by a number of channels. In some embodiments, the number of channels may be controlled collectively by the non-volatile memory control circuitry 222. In some embodiments, each memory channel may be coupled to a discrete channel control circuit 248. A particular channel control circuit 248 may control and be coupled to more than one memory unit 250 by a single channel.
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The CRQ 242 may be configured to receive a command from the switch 220 and relay the command to one of the RQs 244 (e.g., the RQ 244 associated with the channel that is associated with the particular memory unit 250 for which the command is targeted). The RQ 244 may be configured to relay a first number of commands for a particular memory unit 250 to the CQ 246 that is associated with the particular memory unit 250 in an order that the first number of commands were received by the RQ 244. A command pipeline may structured such that commands to a same memory unit 250 move in a particular order (e.g., in the order that they were received by the RQ 244). The RQ 244 may be configured to queue a command for a particular memory unit 250 in response to the CQ 246 associated with the particular memory unit 250 being full and the CRQ 242 may be configured to queue a command for a particular RQ 244 in response to the particular RQ 244 being full.
The RQ 244 may relay a number of commands for different memory units 250 to the CQs 246 that are associated with the different memory units 250 in an order according to a status of the different memory units 250. For example, the status of the different memory units 250 may be a ready/busy status. The command pipeline is structured such that the commands between different memory units 250 may move out of order (e.g., in an order that is different from the order in which they were received by the RQ 244 according to what is efficient for overall memory operation at the time). For example, the RQ 244 may be configured to relay a first one of the second number of commands to a first CQ 246 before relaying a second command from the second number of commands to a second CQ 246 in response to the status of the different memory unit 250 associated with the second CQ 246 being busy, where the first command is received later in time than the second command. The RQ 244 may be configured to relay the second command to the second CQ 246 in response to the status of the memory unit 250 associated with the second CQ 246 being ready (e.g., subsequent to relaying the first command).
In some embodiments, the control circuits for each channel may include discrete error detection/correction circuitry 232 (e.g., error correction code (ECC) circuitry), coupled to each channel control circuit 248 and/or a number of error detection/correction circuits 232 that can be used with more than one channel. The error detection/correction circuitry 232 may be configured to apply error correction such as Bose-Chaudhuri-Hocquenghem (BCH) error correction to detect and/or correct errors associated with information stored in the memory units 250. The error detection/correction circuitry 232 may be configured to provide differing error correction schemes for SLC, MLC, or QLC operations. The non-volatile memory control circuitry 222 may further include the read indicator component 113 of
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The processing logic may further select a read operation from multiple types of read operations based on the identified type of workload of the host system (block 330). The types of read operations may be operations that a memory device (e.g., a NAND flash memory device) may perform to retrieve data at memory pages of the memory device. Thus, the type of read operation may be an operation that is performed internally within one of the memory devices. One type of read operation may be a discrete read operation that retrieves data associated with a word line and a bit line of the memory device. Another type of read operation may be a word line ramp read operation that retrieves data associated with a word line and multiple bit lines of the memory device. In some embodiments, the discrete read operation may be used by the memory device when the workload of the host system is identified as a random workload and the word line ramp read operation may be used by the memory device when the workload of the host system is identified as a deterministic workload. Furthermore, the processing device may provide an indication of the selected read operation to be performed by a memory device (block 340). The indication provided to the memory device may be an operation code (opcode) that is an instruction that specifies the type of read operation to be performed by the memory device. Thus, a memory device that is storing data requested by the host system may use the specified read operation when retrieving data from memory pages of the memory device. Further details with regards to the types of read operations that may be performed by the memory device are described in conjunction with
As such, a controller of a storage device (e.g., a solid-state drive) may identify a workload of a host system. If the workload is deterministic, then the controller may indicate to a memory device to retrieve data stored at multiple memory pages by using a word line ramp read operation. Otherwise, if the workload is random, then the controller may indicate to the memory device to retrieve data stored at a memory page by using the discrete read operation. In some embodiments, after the workload has been identified as being deterministic or random, the identification of the workload may be stored at a controller coupled with the memory device. The stored identification may be used by the controller to provide an indication (e.g., opcode) for the memory device to perform a particular type of read operation for subsequently received read requests.
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In response to determining that the read requests are associated with sequential logical block addresses, then the processing logic may identify that the workload of the host system is a deterministic workload (block 430). Furthermore, the processing logic may receive a subsequent read request and indicate to a memory device to perform a word line ramp read operation to retrieve data for the subsequent read request (block 440). For example, an opcode specifying the word line ramp read operation may be provided to the memory device to retrieve the data for the subsequent read request. When performed, the word line ramp read operation may apply an increasing voltage input to a word line to read data of multiple memory pages associated with multiple bit lines of the memory device as described in conjunction with
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In some embodiments, the data received from the discrete read operation may be stored at the buffer memory before being provided to the host system. In some embodiments, the discrete read operation may return less data from the memory device than the word line ramp read operation. As a result, the discrete read operation may result in less data being stored at the buffer memory than when the word line ramp read operation is performed by a memory device of a storage device.
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In some embodiments, the workload from the host system may be identified as having changed from a deterministic workload to a random workload (or vice versa). The workload of the host system may be identified for groups of consecutively received read requests from the host system. For example, a first group of read requests may include a threshold number of read requests. The workload of the host system may be identified based on the logical block addresses of the read requests from the first group. Subsequently, a second group of read requests may be received from the host system. The second group of read requests may include the threshold number of read requests and the read requests may be consecutively received. The workload of the host system may then be identified based on the logical block addresses of the read requests from the second group. If the identified workload is different between the first group of read requests and the second group of read requests, then the type of read operation that is performed for subsequently received read requests may be changed. The identification of the workload may continue for subsequent groups of read requests so that the identified workload may change between a deterministic workload and a random workload as subsequent groups of read requests are received, resulting in the change between performing a word line ramp read operation and a discrete read operation by a memory device.
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Thus, the different read operations performed by a memory device based on an indication may correspond to different input voltage signals that are applied to an input (e.g., a word line) of the memory device. Although
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Although identifying a workload of a host system as deterministic or random is described to determine whether to indicate for a memory device to perform a word line ramp read operation or a discrete read operation, any other characteristics associated with the host system or the workload of the host system may be used to determine which type of read operation to select to be performed by a memory device. Examples of such characteristics include, but are not limited to, an identification of an application providing the read requests associated with the workload, an identification of a client system providing the read requests, etc. For example, a first identified application may be used to specify that each read request should be performed using the word line ramp read operation, a second identified application may be used to specify that each read request should be performed using the discrete read operation, and a third identified application may specify that each read request should be identified as being either a deterministic workload or a random workload as previously described.
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The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term “machine” shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.
The example computer system 900 includes a processing device 902, a main memory 904 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 906 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 918, which communicate with each other via a bus 930.
Processing device 902 represents one or more general-purpose processing devices such as a microprocessor, a central processing unit, or the like. More particularly, the processing device may be complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processing device 902 may also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. The processing device 902 is configured to execute instructions 926 for performing the operations and steps discussed herein.
The computer system 900 may further include a network interface device 908 to communicate over the network 920. The computer system 900 also may include a video display unit 910 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 912 (e.g., a keyboard), a cursor control device 914 (e.g., a mouse), a graphics processing unit 922, a signal generation device 916 (e.g., a speaker), graphics processing unit 922, video processing unit 928, and audio processing unit 932.
The data storage device 918 may include a machine-readable storage medium 924 (also known as a computer-readable medium) on which is stored one or more sets of instructions or software 926 embodying any one or more of the methodologies or functions described herein. The instructions 926 may also reside, completely or at least partially, within the main memory 904 and/or within the processing device 902 during execution thereof by the computer system 900, the main memory 904 and the processing device 902 also constituting machine-readable storage media. The machine-readable storage medium 924, data storage device 918, and/or main memory 904 may correspond to the storage device 110 of
In one implementation, the instructions 926 include instructions to implement functionality corresponding to a read indicator component (e.g., read indicator component 113 of
Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the ways used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.
It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the above discussion, it is appreciated that throughout the description, discussions utilizing terms such as “receiving” or “determining” or “providing” or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage devices.
The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.
The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the disclosure as described herein.
The present disclosure may be provided as a computer program product, or software, that may include a machine-readable medium having stored thereon instructions, which may be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium such as a read only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory devices, etc.
In the foregoing specification, implementations of the disclosure have been described with reference to specific example implementations thereof. It will be evident that various modifications may be made thereto without departing from the broader spirit and scope of implementations of the disclosure as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.
