Patent Application
20240178663
This application relates to electrostatic discharge (ESD) circuits for protecting terminals according to International Electrotechnical Commission (IEC) standards, and more particularly an ESD circuit that provides IEC protection of high-frequency terminals.
The manufacture of integrated circuits and their assembly into electronic devices typically takes place under controlled ESD conditions. Due to the ESD precautions taken during manufacture and assembly, the potential ESD stress from contact with a technician is relatively subdued. To simulate this stress, a human body model (HBM) has been developed. Due to the ESD precautions taken during manufacture and assembly, the stress from the HBM is not as severe as developed by the International Electrotechnical Commission (IEC) for modeling ESD stress that could be subjected to an electronic device by an end user. The levels of voltage and current that an integrated circuit terminal must endure to meet the IEC standards are thus significantly greater than HBM levels.
To meet IEC standards and thus accommodate such high levels of voltage and current, an integrated circuit terminal often couples to a robust ESD clamp circuit (which may also be denoted as an ESD trigger circuit) that may conduct the increased amounts of charge from the integrated circuit terminal to a voltage node such as ground or the power supply voltage rail. A clamp circuit that can safely accommodate IEC levels of charge will typically load the integrated circuit with significant amounts of capacitance. Such elevated capacitive loading by the IEC clamp circuit may result in unacceptable bit error rates for high-speed (and thus high-frequency) data signaling.
In accordance with an aspect of the disclosure, an electrostatic discharge (ESD) circuit is provided that includes; an integrated circuit terminal; a pass transistor having a drain coupled to the integrated circuit terminal; a voltage node; a first ESD diode coupled between the integrated circuit terminal and the voltage node; and an ESD trigger circuit coupled between a gate of the pass transistor and the voltage node, the ESD trigger circuit being configured to couple the gate of the pass transistor to the voltage node in response to an electrostatic shock of the integrated circuit terminal and to isolate the gate of the pass transistor from the voltage node in an absence of the electrostatic shock of the integrated circuit terminal.
In accordance with another aspect of the disclosure, a method of electrostatic discharge is provided that includes the acts of: receiving a charge at a terminal of an integrated circuit from an electrostatic shock; conducting the charge from the terminal through a diode to a voltage node to pulse a voltage of the voltage node; and coupling the voltage node to a gate of a pass transistor having a drain coupled to the terminal in response to a detection of the pulse of the voltage of the voltage node.
In accordance with yet another aspect of the disclosure, an electrostatic discharge (ESD) circuit is provided that includes: an integrated circuit terminal; a node for a high-speed data signal; a pass transistor coupled between the node for the high-speed data signal and the integrated circuit terminal; and an ESD trigger circuit configured to couple a power supply node for a power supply voltage to a gate of the pass transistor in response to a positive electrostatic shock to the integrated circuit terminal.
In accordance with yet another aspect of the disclosure, an electrostatic discharge (ESD) circuit is provided that includes: an integrated circuit terminal; a node for a high-speed data signal; a pass transistor coupled between the node for the high-speed data signal and the integrated circuit terminal; and an ESD trigger circuit configured to couple a negative voltage node for a negative voltage to a gate of the pass transistor in response to a negative electrostatic shock to the integrated circuit terminal.
These and other advantageous features may be better appreciated through the following detailed description.
Implementations of the present disclosure and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.
The increased capacitive loading from an IEC clamp circuit is particularly problematic when a terminal of an integrated circuit is used not only to transmit (or receive) high-speed data during a high-speed data mode of operation but also is used to transmit (or receive) audio signals during an audio mode of operation. A dual-mode integrated circuit 100 is shown in
Diodes D1, D2, D3, and D4 protect terminals DP and DN from HBM-levels of charge but do not provide IEC ESD protection. To provide IEC ESD protection, integrated circuit 100 could include ESD clamp circuits that couple to terminals DP and DN. As defined herein, an ESD clamp circuit that can accommodate an IEC amount of electrostatic-induced charge is denoted as an IEC clamp circuit. But such IEC clamp circuits would load terminals DP and DN with several tens of pico-Farads of capacitance as will be discussed further herein. During the high-speed data mode of operation, integrated circuit 100 may generate a DP signal (DPin) that couples through a switch S1 and the DP terminal to an external device (not illustrated) that couples to the DP terminal through a USB plug 105. Similarly, integrated circuit 100 may generate a DN signal (DNin) that couples through switch S3 and the DN terminal to the external device via USB plug 105. Due to the bidirectionality of the DP and DN terminals, the external device may instead drive the DP and DN terminals such that the DPin and DNin signals are received signals rather than being generated by integrated circuit 100.
During the audio mode of operation, integrated circuit 100 may generate a headphone right (HPHR) signal and the headphone left (HPHL) signal. Alternatively, these audio signals may be generated by another integrated circuit and routed to integrated circuit 100. The HPHR signal couples through a switch S2 to the DP terminal. Similarly, the HPHL signal couples through a switch S4 to the DN terminal. Switches S1 and S3 are open during the audio mode of operation. Similarly, switches S2 and S4 are open during the high-speed data mode of operation.
To pass both a strong binary one and a strong binary zero, switches S1 and S3 may be constructed using transmission gates that include both an n-type metal-oxide-semiconductor (NMOS) pass transistor and a p-type metal-oxide-semiconductor (PMOS) pass transistor. Alternatively, switches S1 and S3 may be constructed using just a single pass transistor of either polarity. The pass transistor(s) used to construct switches S1 and S3 are off during the audio mode of operation and on during the high-speed data mode. Switches S2 and S4 may also be constructed using pass transistors. Although the pass transistors forming switches S2 and S4 are off during the high-speed data mode of operation, these pass transistors and the associated audio driving circuitry (not illustrated) load the DP and DN terminals with capacitance. This capacitive loading may thus become untenable should the DP and DN terminals couple to IED clamp circuits.
To avoid the capacitive loading from an IED clamp circuit, integrated circuit 100 includes an ESD trigger circuit 110 that reacts to an electrostatic-shock-induced charging of an integrated circuit terminal such as the DP or DN terminal by pulsing the voltage of the gate and bulk of the pass transistors that form the switches coupled to the integrated circuit terminal. ESD trigger circuit 110 may also be denoted as an RC clamp circuit or as an edge-triggered RC clamp circuit. Since ESD trigger circuit 110 does not couple to the DP and DN terminals, these terminals are not loaded with the capacitance of an IEC clamp circuit, yet the pass transistor(s) coupled to the integrated circuit terminal are protected from IEC levels of electrostatic-shock-induced charge.
To provide a better appreciation of the function of ESD trigger circuit 110, an example NMOS pass transistor M1 in an integrated circuit 200 is shown in
In the audio mode of operation, the audio signals that conduct through the audio pass transistors 210 may be either positive or negative in voltage. To assure that pass transistor M1 stays off during the audio mode in the presence of such negative signals, a controller 205 asserts the gate voltage of a transistor M2 that couples between a negative voltage node for a negative voltage Vneg and the gate of the pass transistor M1. In this fashion, the gate of the pass transistor M1 is charged to the negative voltage Vneg during the audio mode of operation to ensure that the pass transistor M1 does not conduct. During a high-speed data mode of operation, controller 205 switches off transistor M2 and switches on another transistor (not illustrated) that couples between the gate of the pass transistor M1 and a power supply node for a power supply voltage Vdd. Pass transistor M1 is thus on during the high-speed data mode of operation so that high-speed data signals may conduct through the pass transistor M1 to the integrated circuit terminal DX. A transistor M3 couples between the bulk of the pass transistor M1 and the negative voltage node. A controller such as controller 205 controls a gate voltage of transistor M3 with a Vbulk control signal so that transistor M3 is on during the audio mode to bias a bulk voltage Vbias of the pass transistor to the negative voltage Vneg.
Although an electrostatic-shock-induced charging of the DX terminal can be either positive or negative, it can be shown that it is a positive electrostatic charge that poses a danger to an NMOS pass transistor such as pass transistor M1. Conversely, it is a negative electrostatic charge that poses a danger to a PMOS pass transistor (not shown in
To provide additional ESD protection with respect to a positive electrostatic charge, the DX terminal couples to the power supply node through a Dpositive diode that is a generic representation of either diode D1 or diode D3 of integrated circuit 100. Similarly, to provide ESD protection with respect to a negative electrostatic charge, the DX terminal couples to the negative voltage node Vneg through a Vnegative diode that is a generic representation of either diode D2 or diode D4 of integrated circuit 100. In the presence of a positive electrostatic charging of the DX terminal, the Dpositive diode becomes forward biased so that the positive charge conducts to the power supply node. ESD trigger circuit 215 responds to the resulting positive pulsing of the power supply voltage Vdd by coupling the power supply node to the gate of transistor M1. This coupling through ESD trigger circuit 215 causes the gate voltage of the pass transistor M1 to also pulse positively. Since transistor M2 is on, the pulsing of the gate voltage of the pass transistor M1 conducts through transistor M2 to raise the negative voltage of the negative voltage Vneg. With transistor M3 also being on during the audio mode of operation, the positive pulsing of the negative voltage Vneg causes the bulk voltage Vbulk of the pass transistor M1 to also pulse high. In this fashion, the gate-to-drain voltage and gate-to-bulk voltage of the pass transistor M1 are maintained at safe levels despite the DX terminal being suddenly exposed to an IEC level of positive electrostatic charge.
An IEC level of positive electrostatic charge on terminal DX may raise a voltage of the terminal DX to approximately 10 V (albeit briefly). It will be appreciated that this voltage value is exemplary and that other values may be used. Similarly, a negative voltage Vneg of −2 V is also exemplary and may be changed in alternative implementations. If the negative voltage Vneg is −2 V and terminal DX is charged to 10 V, a gate-to-drain voltage of the pass transistor M1 would then be approximately_-12 V without the presence of ESD trigger circuit 215. Such a relatively large gate-to-drain voltage may damage the pass transistor M1. But with the protective action of ESD trigger circuit 215, the gate voltage will also pulse briefly high such as to approximately 7.5 V. The gate-to-drain voltage of the pass transistor M1 is thus approximately just −2.5 V, which is readily tolerated. Similarly, the conduction by ESD trigger circuit 215 may pulse the bulk voltage Vbulk of the pass transistor M1 to approximately 5 V. The bulk-to-drain voltage of the pass transistor in response to the positive electrostatic shock is thus limited to approximately 5 V, which again is tolerated by the pass transistor M1. Note that ESD trigger circuit 215 does not load the DX terminal but instead indirectly detects the pulsing of the DX terminal voltage by detecting the resulting pulsing of the power supply voltage Vdd. In this fashion, ESD trigger circuit 215 advantageously does not load the DX terminal with extra capacitance. In contrast, a traditional IEC clamp circuit would load terminal DX with a substantial amount of capacitance (e.g., tens of pico-Farads). ESD trigger circuit 215 is thus quite advantageous with respect to providing IEC ESD protection without contributing to any capacitive loading of the DX terminal. In this fashion, the DX terminal has a suitably low level of capacitive loading for high-speed data signaling.
An example circuit implementation 300 of ESD trigger circuit 215 is shown in
As noted earlier, the pass transistor may also be a PMOS transistor. An example PMOS pass transistor P4 in an integrated circuit 400 is shown in
To assure that pass transistor P4 stays off during the audio mode, a controller 405 grounds the gate voltage Vcontrol of a PMOS transistor P5 that couples between the power supply node and the gate of the pass transistor P4. In this fashion, the gate of the pass transistor P4 is charged to the power supply voltage Vdd during the audio mode of operation to ensure that the pass transistor P4 does not conduct. During a high-speed data mode of operation, controller 405 switches off transistor P5 and switches on another transistor (not illustrated) that couples between the gate of the pass transistor P4 and a ground node. Pass transistor P4 is thus on during the high-speed data mode of operation so that high-speed data signals may conduct through the pass transistor M4 to the integrated circuit terminal DX. A PMOS transistor P6 couples between the bulk of the pass transistor P4 and the power supply node. A controller such as controller 405 controls a gate voltage of transistor P6 with a Vbulk control signal so that transistor P6 is on during the audio mode to bias a bulk voltage Vbias of the pass transistor P4 to the power supply voltage Vdd.
Although an electrostatic-shock-induced charging of the DX terminal can be either positive or negative, it can be shown that it is a negative electrostatic charge that poses a danger to a PMOS pass transistor such as pass transistor P4. As noted earlier, ESD trigger circuit 110 is generic to the polarity of the pass transistors but in example implementations, there are separate trigger circuits for protecting NMOS pass transistors as compared to ESD trigger circuits for protecting PMOS pass transistors. For pass transistor M4, a PMOS-pass-transistor-protecting ESD trigger circuit 415 couples between the negative voltage node and the gate of pass transistor P4. During normal operation (no electrostatic shock of the DX terminal), ESD trigger circuit 415 isolates the negative voltage node from the gate of the pass transistor P4. However, in response to a negative electrostatic charging of the DX terminal, ESD trigger circuit 415 couples the negative voltage node to the gate of the pass transistor P4.
To provide additional ESD protection with respect to a negative electrostatic charge, the DX terminal couples to the negative voltage node through a Dnegative diode that is a generic representation of either diode D2 or diode D4 of integrated circuit 100. Similarly, to provide ESD protection with respect to a positive electrostatic charge, the DX terminal couples to the power supply node through a Dpositive diode that is a generic representation of either diode D1 or diode D3 of integrated circuit 100. In the presence of a negative electrostatic charging of the DX terminal, the Dnegative diode becomes forward biased so that the negative charge conducts to the negative voltage node Vneg. A nominal value of the negative voltage may be −2 V but in the presence of the negative electrostatic charging of the DX terminal, the negative voltage may be pulled substantially more negative such as to approximately −10 V. It will be appreciated that such a voltage value is merely exemplary and may be higher or lower depending upon the exact amount of negative electrostatic charge delivered to the DX terminal and the voltage for the negative voltage node. Trigger circuit 415 responds to the resulting negative pulsing of the negative voltage node Vneg by coupling the negative voltage node to the gate of the pass transistor P4. This coupling through ESD trigger circuit 415 causes the gate voltage of the pass transistor P4 to also pulse negatively. Since transistor P5 is on, the negative pulsing of the gate voltage of the pass transistor P4 conducts through transistor P5 to negatively pulse the power supply voltage Vdd. Since transistor P6 is on, the negative pulsing of the DX terminal causes the bulk voltage Vbulk of the pass transistor P4 to also pulse negatively. In this fashion, the gate-to-drain voltage and gate-to-bulk voltage of the pass transistor P4 are kept to safe levels despite the DX terminal being suddenly exposed to an IEC level of negative electrostatic charge. As noted earlier, an IEC level of negative electrostatic charge on terminal DX lowers a voltage of the terminal DX to approximately −10 V (albeit briefly). If the power supply voltage Vdd is 1 V, a gate-to-drain voltage of the pass transistor P4 would then be 11 V without the presence of ESD trigger circuit 415. Such a relatively large gate-to-drain voltage may damage the pass transistor P4. But with the protective action of ESD trigger circuit 415, the gate voltage will also briefly pulse negatively such as to approximately −8 V. The gate-to-drain voltage of the pass transistor P4 is thus approximately just 2 V, which is readily tolerated. Similarly, the conduction by ESD trigger circuit 415 may negatively pulse the bulk voltage Vbulk of the pass transistor P4 to approximately −6 V. The bulk-to-drain voltage of the pass transistor P4 in response to the negative electrostatic shock is thus limited to approximately 4 V, which again is tolerated by the pass transistor P4. Note that ESD trigger circuit 415 does not load the DX terminal but instead indirectly detects the pulsing of the DX terminal voltage by detecting the resulting pulsing of the negative voltage Vneg. In this fashion, trigger circuit 415 advantageously does not load the DX terminal with extra capacitance. In contrast, a traditional IEC clamp circuit would load terminal DX with a substantial amount of capacitance (e.g., tens of pico-Farads). ESD trigger circuit 415 is thus quite advantageous with respect to providing IEC levels of ESD protection without contributing to any significant capacitive loading of the DX terminal. In this fashion, the DX terminal has a suitably low level of capacitive loading for high-speed data signaling.
An example circuit implementation 500 of ESD trigger circuit 415 is shown in
A method of operation for an ESD circuit will now be discussed with regard to the flowchart shown in
A ESD circuit as disclosed herein may be incorporated in any suitable mobile device or electronic system. For example, as shown in
The disclosure will now be summarized in the following series of clauses:
Clause 1. An electrostatic discharge (ESD) circuit, comprising:
It will be appreciated that many modifications, substitutions and variations can be made in and to the materials, apparatus, configurations and methods of use of the devices of the present disclosure without departing from the scope thereof. In light of this, the scope of the present disclosure should not be limited to that of the particular implementations illustrated and described herein, as they are merely by way of some examples thereof, but rather, should be fully commensurate with that of the claims appended hereafter and their functional equivalents.
