IGBT/FET-based energy savings device for reducing a predetermined amount of voltage using pulse width modulation

Information

  • Patent Grant
  • 8723488
  • Patent Number
    8,723,488
  • Date Filed
    Tuesday, December 20, 2011
    13 years ago
  • Date Issued
    Tuesday, May 13, 2014
    10 years ago
Abstract
An energy savings device, system, and method wherein a predetermined amount of voltage below a nominal line voltage and/or below a nominal appliance voltage is saved, thereby conserving energy. Phase input connections are provided for inputting analog signals into the device and system. A volts zero crossing point detector determines the zero volts crossing point of the signal. The positive half cycle and negative half cycle of the signal are identified and routed to a digital signal processor for processing the signal. The signal is reduced by pulse width modulation and the reduced amount of energy is outputted, thereby yielding an energy savings for an end user.
Description
BACKGROUND OF THE INVENTION

This invention relates to energy savings devices, systems and methods, more particularly, an insulated gate bipolar transistor/field effect transistor (IGBT/FET) based energy savings device, system and method for use wherein a predetermined amount of voltage below a nominal line voltage and/or below a nominal appliance voltage is saved, thereby conserving energy.


Since the industrial revolution, the world's consumption of energy has grown at a steady rate. Most power generated and energy consumed is from the combustion of fossil fuels, a nonrenewable, natural resource that is rapidly becoming depleted. As the depletion of Earth's natural resources continues, power generation and energy conservation has become an increasingly important issue with governments in both this country and abroad. In addition, not only are governments concerned with power generation and energy conservation, but businesses and consumers are also concerned as the costs for such resources are rapidly increasing.


Not only do there exist worldwide concerns with power generation and energy conservation, but there also exist concerns with power distribution as well, especially in emerging economies. Although power generation and energy conservation are of great importance, the problem of power distribution is also of great concern as it involves existing infrastructure that is usually inadequate for properly distributing power and not readily suitable to be improved upon. This problematical situation is manifested by “brown outs” wherein a nominal AC voltage cannot be maintained in the face of a grid/generation overload.


Currently, governmental entities and power companies attempt to remedy brown out occurrences by elevating the AC voltage or adding power shedding generation at appropriate locations on the power grid. This method usually results in a wide disparity of voltages available to consumers in homes and/or business. The voltage increases may range from ten percent to fifteen percent (10%-15%) and, since power is calculated by Voltage2/load, the result of the governmental entities' and power companies' “remedy” can result in increased charges to the consumer of up to twenty-five percent (25%). Thus, rather than conserving energy, governmental entities and power companies are expending energy.


Furthermore, although most appliances and equipment used in businesses and homes are capable of performing, exactly to specification, at the nominal voltage minus ten percent (10%), most energy savings devices do not exploit this feature. Thus, a further potential for energy savings is oftentimes ignored.


Therefore, a need exists for an IGBT/FET-based energy savings device, system and method wherein a predetermined amount of voltage below a nominal line voltage and/or below a nominal appliance voltage is saved, thereby conserving energy.


The relevant prior art includes the following references:














Patent/Serial No.

Issue/Publication


(US unless stated otherwise)
Inventor
Date







6,664,771
Scoggins et al.
Dec. 16, 2003


6,486,641
Scoggins et al.
Nov. 26, 2002


2005/0068013
Scoggins
Mar. 31, 2005


6,489,742
Lumsden
Dec. 03, 2002


7,010,363
Donnelly et al.
Mar. 07, 2006


5,652,504
Bangerter
Jul. 29, 1997


5,625,236
Lefebvre et al.
Apr. 29, 1997


5,543,667
Shavit et al.
Aug. 06, 1996


5,442,335
Cantin et al.
Aug. 15, 1995


5,134,356
El-Sharkawi et al.
Jul. 28, 1992


5,003,192
Beigel
Mar. 26, 1991


3,959,719
Espelage
May 25, 1976


4,706,017
Wilson
Nov. 10, 1987


2007/0279053
Taylor et al.
Dec. 06, 2007


6,963,195
Berkcan
Nov. 08, 2005


6,184,672
Berkcan
Feb. 06, 2001


3,582,774
Forgacs
Jun. 01, 1971


5,994,898
DiMarzio et al.
Nov. 30, 1999


7,358,724
Taylor et al.
Apr. 15, 2008


7,259,546
Hastings et al.
Aug. 21, 2007


7,250,748
Hastings et al.
Jul. 31, 2007


7,298,132
Woolsey et al.
Nov. 20, 2007


7,298,133
Hastings et al.
Nov. 20, 2007


7,157,898
Hastings et al.
Jan. 02, 2007


6,912,911
Oh et al.
Jul. 05, 2005


5,180,970
Ross
Jan. 19, 1993


6,414,475
Dames et al.
Jul. 02, 2002


2008/0084201
Kojori
Apr. 10, 2008


7,358,724
Taylor et al.
Apr. 15, 2008


6,426,632
Clunn
Jul. 30, 2002


6,265,881
Meliopoulos et al.
Jul. 24, 2001


5,202,621
Reischer
Apr. 13, 1993


4,616,174
Jorgensen
Oct. 07, 1986


4,513,274
Halder
Apr. 23, 1985


4,096,436
Cook et al.
Jun. 20, 1978


3,976,987
Anger
Aug. 24, 1976


2008/0084200
Kojori
Apr. 10, 2008


2004/0239335
McClelland et al.
Dec. 02 ,2004


7,301,308
Aker et al.
Nov. 27 ,2007


6,548,989
Duff, Jr.
Apr. 15 ,2003


6,548,988
Duff, Jr.
Apr. 15, 2003


7,245,100
Duff, Jr.
Jul. 17, 2007


7,205,822
Torres et al.
Apr. 17, 2007


7,091,559
Fragapane et al.
Aug. 15, 2006


6,724,043
Ekkanath Madathil
Apr. 20, 2004


6,618,031
Bohn, Jr. et al.
Sep. 09, 2003


6,411,155
Pezzani
Jun. 25, 2002


5,559,685
Lauw et al.
Sep. 24, 1996


6,055,171
Ishii et al.
Apr. 25, 2000


7,355,865
Royak et al
Apr. 08, 2008


7,123,491
Kusumi
Oct. 17, 2006


6,650,554
Darshan
Nov. 18, 2003


5,946,203
Jiang et al.
Aug. 31, 1999


5,936,855
Salmon
Aug. 10, 1999


5,600,549
Cross
Feb. 04, 1997


4,679,133
Moscovici
Jul. 07, 1987


2008/0043502
Billig et al.
Feb. 21, 2008









SUMMARY OF THE INVENTION

The primary object of the present invention is to provide an IGBT/FET-based device, system and method wherein a predetermined amount of voltage below a nominal line voltage is saved, thereby conserving energy.


Another object of the present invention is to provide an IGBT/FET-based device, system and method wherein a predetermined amount of voltage below a nominal appliance voltage is saved, thereby conserving energy.


A further object of the present invention is to provide an IGBT/FET-based device, system and method that may be used for a variety of applications, including, but not limited to, whole house energy savings devices, motor controllers, small appliance regulators and any application wherein the measurement of AC current is required.


Another object of the present invention is to provide an IGBT/FET-based device, system and method that may be used for the following: controllers for refrigerators, freezers, air conditioners, AC electric motors and AC voltage; single, bi- and poly-phase whole house energy savings devices; commercial and industrial energy savings devices; and AC voltage regulators.


A further object of the present invention is to provide an IGBT/FET-based device, system and method that virtually eliminates brown outs caused by energy overload on a power grid.


An even further object of the present invention is to provide an IGBT/FET-based device, system and method that reduces a load on a power grid.


Another object of the present invention is to provide an IGBT/FET-based device, system and method that may be used to reduce the load imposed on a power grid during peak load times.


An even further object of the present invention is to provide an IGBT/FET-based device, system and method that permits governmental entities and/or power companies to manage power from a demand perspective as opposed to a production and/or delivery perspective.


Another object of the present invention is to provide an IGBT/FET-based device, system and method that is low in costs after the initial cost of the equipment utilized in the system is amortized.


Another object of the present invention is to provide an IGBT/FET-based device, system and method provides accurate power control and regulation.


Another object of the present invention is to provide an IGBT/FET-based device, system and method wherein the device may be programmed by a user for activation for a specific time and/or date period.


An even further object of the present invention is to provide an IGBT/FET-based device, system and method wherein a user may program individual and/or multiple energy savings percentage reductions.


A further object of the present invention is to provide an IGBT/FET-based device, system and method that is adaptable to a plurality of powers and/or frequencies.


A further object of the present invention is to provide an IGBT/FET-based device, system and method that may be small in size.


Another object of the present invention is to provide an IGBT/FET-based device, system and method that is preferably affordable to an end user.


An even further object of the present invention is to provide an IGBT/FET-based device, system and method that allows a user to manage peak demand at point of consumption rather than at point of generation.


Another object of the present invention is to provide an IGBT/FET-based device, system and method that provides galvanic isolation of a central processing unit (if utilized) from an AC power source.


An even further object of the present invention is to provide an IGBT/FET-based device, system and method that may include synchronous or random pulse width modulation.


Another object of the present invention is to provide an IGBT/FET-based device, system and method that reduces hamionics resulting from currently utilized energy savings devices.


The present invention fulfills the above and other objects by providing an IGBT/FET-based device, system and method wherein a predetermined amount of voltage below a nominal line voltage and/or below a nominal appliance voltage is saved, thereby conserving energy. Phase input connections are provided for inputting analog signals into the device and system. A magnetic flux concentrator senses the incoming analog signal and a volts zero crossing point detector determines the zero volts crossing point of the signal. The positive half cycle and negative half cycle of the signal is identified and routed to a digital signal processor for processing the signal. The signal is reduced by a driver control via pulse width modulation and the reduced amount of energy is outputted, thereby yielding an energy savings for an end user.


The above and other objects, features and advantages of the present invention should become even more readily apparent to those skilled in the art upon a reading of the following detailed description in conjunction with the drawings wherein there is shown and described illustrative embodiments of the invention.





BRIEF DESCRIPTION OF THE DRAWINGS

In the following detailed description, reference will be made to the attached drawings in which:



FIG. 1 is a block diagram of an IGBT/FET-based device and system of the present invention for use in a three-phase electrical system;



FIG. 2 is perspective plan view of a sensing means of the present invention;



FIG. 3 is a circuit diagram of a sensing means of the present invention;



FIG. 4 is a circuit diagram of a signal conditioning means of the present invention;



FIG. 5 is an oscillogram for a volts zero crossing point determining means of the present invention;



FIG. 6 is a circuit diagram for a volts zero crossing point determining means of the present invention;



FIG. 7 is circuit diagram of a loss detecting means and phase rotation determination and rotating means of the present invention;



FIG. 8 is show a circuit diagram of a half cycle identifying means of the present invention;



FIG. 9 is show an oscillogram of a half cycle identifying means of the present invention;



FIG. 10 is show an oscillogram of a half cycle identifying means of the present invention;



FIG. 11A is a circuit diagram of the routing means of the present invention;



FIG. 11B is a continuation of the circuit diagram of FIG. 11A;



FIG. 11C is a circuit diagram of a ports programmer of FIGS. 11A and 11B;



FIG. 11D is a circuit diagram of a resistor support of FIGS. 11A and 11B;



FIG. 11E is a circuit diagram of a connector of FIGS. 11A and 11B;



FIG. 12A is an oscillogram of a voltage reducing means of the present invention;



FIG. 12B is an oscillogram of a voltage reducing means of the IGBT-based present invention;



FIG. 12C is a circuit diagram of an IGBT-based voltage reducing means of the present invention;



FIG. 12D is a circuit diagram of a drive circuitry for the IGBT-based voltage reducing means of FIG. 12C;



FIG. 12E is a oscillogram of a voltage reducing means of the FET-based present invention;



FIG. 12F is a circuit diagram of a FET-based voltage reducing means of the present invention;



FIG. 12G is a circuit diagram of a drive circuitry for the FET-based voltage reducing means of FIG. 12F;



FIG. 13 a circuit diagram of a combined resetting means and indicator means of the present invention;



FIG. 14 is a circuit diagram of a power supply unit of a powering means of the present invention;



FIG. 15A is a circuit diagram a communication means of the present invention;



FIG. 15B is a circuit diagram of a USB interface of a communications means of FIG. 15A;



FIG. 15C is a circuit diagram of an isolator block of a communications means of FIG. 15A;



FIG. 15D is a circuit diagram of a first connector of a communications means of FIG. 15A into a digital signal processor;



FIG. 15E is a circuit diagram of a second connector of a communications means of FIG. 15A;



FIG. 16 is a screen shot of a windows interface of the present invention; and



FIG. 17 is a screen shot of a windows interface of the present invention.





DESCRIPTION OF THE PREFERRED EMBODIMENTS

For purposes of describing the preferred embodiment, the terminology used in reference to the numbered components in the drawings is as follows:















1.
IGBT/FET-based energy savings device and system, generally


2.
phase input connection


3.
magnetic flux concentrator


4.
analog signal conditioning device


5.
volts zero crossing point detector


6.
lost phase detection device


7.
phase rotation device


8.
half cycle identifier


9.
logic device


10.
digital signal processor


11.
A/D converter


12.
power supply unit


13.
reset switch


14.
light emitting diode


15.
IGBT/FET drive control


16.
computing device


17.
phase output connection


18.
neutral


19.
incoming energy


20.
analog signal


21.
volts zero crossing point


22.
positive half cycle


23.
negative half cycle


24.
reduced energy


25.
USB communications interface


26.
circuit board


27.
housing


28.
conductor


29.
housing top half


30.
housing bottom half


31.
hinge


32.
first filter


33.
second filter


34.
comparator


35.
Schmidt buffer


36.
absolute zero cross signal


37.
magnetic flux concentrator chip


38.
aperture


39.
incoming sine wave


40.
windows interface


41.
main monitoring screen


42.
field, generally


43.
operational mode field


44.
phase field


45.
startup field


46.
calibration field


47.
setpoints field


48.
indicators


49.
real time clock


50.
digital electricity meter


51.
Schmidt-triggered inverting buffer


52.
transorb device


53.
diode


54.
positive half cycle control transistor


55.
FET


56.
capacitor


57.
transformer


58.
negative half cycle control transistor


59.
IGBT first shunt control transistor


60.
IGBT second shunt control transistor


61.
shunt device


62.
integrated circuit


63.
resistor


64.
split rail generator


65.
optical isolator


66.
optically-coupled driver


67.
FET first shunt control transistor


68.
FET second shunt control transistor


69.
square wave


70.
operational amplifier


71.
isolator


72.
rectifier


73.
transistor


74.
USB port


75.
Zener diode


76.
first connector


77.
second connector


78.
inductor


79.
resistor support


80.
logic device connector


81.
linear voltage regulator


82.
positive half cycle drive signal applied to positive half cycle



control transistor


83.
negative half cycle drive signal applied to negative half cycle



control transistor


84.
drive signal applied to positive half cycle control transistor during



negative half cycle


85.
drive signal applied to negative half cycle control transistor during



positive half cycle


86.
drive signal applied to IGBT first shunt control transistor during



negative half cycle


87.
drive signal applied to IGBT second shunt control transistor during



positive half cycle


88.
drive signal applied to FET first shunt control transistor during



negative half cycle


89.
drive signal applied to FET second shunt control transistor during



positive half cycle


90.
switching regulator









With reference to FIG. 1, a block diagram of an energy savings device and system 1 of the present invention for use in a three-phase electrical system is shown. The energy savings device and system 1 includes various components and means for reducing the amount of energy inputted wherein the reduced energy yields a virtually non-existent or minimal effect on the performance of an electronically-operated device.


A predetermined amount of incoming energy 19 having at least one analog signal 20 therein is inputted into the device and system 1 via an inputting means, which is preferably at least one phase input connection 2. A neutral 18 line is also provided in the device and system 1. As shown in FIG. 1, the system and device 1 is utilized in a three-phase electrical system having an A-B-C phase plus neutral for use as a reference point and as a sink for a clamped back-EMF that is produced when the current in a lagging power factor load is interrupted. However, the energy savings system 1 of the present invention may be utilized in a single phase system and/or a bi-phase system as well, wherein the only difference in structure is the amount of phase input connections 2 (e.g., in a single phase system, only one phase input connection 2 is utilized in addition to a neutral connection (A) and in a bi-phase system, two phase input connections 2 are utilized (A & B) in addition to a neutral connection).


At least one phase input connection 2 is connected to at least one sensing means, which is preferably at least one magnetic flux concentrator 3, that senses the predetermined amount of incoming energy 19. The magnetic flux concentrator 3 galvanically isolates the current of the incoming energy 19 and reports any over-current conditions to a routing means, which is preferably at least one logic device 9. If there are any over-current conditions, then the over-current conditions are simultaneously reported to the logic device 9 and a processing means, which is preferably a digital signal processor 10, wherein the digital signal processor 10 immediately shuts down the device and system 1. This electronic breaker action is intended to safeguard the device and system 1 itself, as well as the terminal equipment used in conjunction with the device and system 1 in the event of a short circuit or overload. Thus, the logic device 9 provides total protection of the power control devices in the event of a software/firmware glitch and/or power line glitch or surge in real-time as the reaction time of the logic device 9 and digital signal processor 10 is preferably 5 μs. The logic device 9 arbitrates between the drive signals applied to the IGBT/FET half cycle control transistors 54 and 58 and the signals applied to the IGBT/FET shunt control transistors 59, 60, 67 and 68. Therefore, it avoids the IGBT/FET half cycle control transistors 54 and 58 and IGBT/FET shunt control transistors 59, 60, 67 and 68 from being simultaneously driven to an on-condition that could lead to the failure of the power control and/or shunt elements. The digital signal processor 10 preferably includes at least one A/D converter 11.


Prior to reporting the analog value of the phase current from the phase input connection 2 to the digital signal processor 10, the magnetic flux concentrator 3 first transmits the incoming energy 19 through at least one signal conditioning means, which is preferably at least one analog signal conditioning device 4. After the signal(s) have been conditioned, a method which is described below, the conditioned signals are then sent to a volts zero crossing point determining means, which is preferably at least one volts zero crossing point detector 5, for detecting the point where the AC voltage goes through zero volts relative to neutral 18, which is commonly referred to as a zero crossing point.


After the zero crossing point is detected and if using a three-phase electrical system, the conditioned signal then enters at least one loss detecting means, which is preferably at least one lost phase detection device 6 and at least one phase rotation determination and rotating means, which is preferably at least one phase rotation device 7, so as to prepare the signal for proper inputting into at least one half cycle identifying means, which is preferably at lest one half cycle identifier 8, and then the logic device 9 and digital signal processor 10. Details of the half cycle identifier 8 are discussed below.


The power control is executed via at least one voltage reducing means, which preferably includes at least one IGBT/FET drive control 15, in electrical connection with the digital signal processor 10 to reduce the energy a predetermined amount. Prior to the processed signals entering the reducing means, however, the signals may once again be conditioned through at least one analog signal conditioning device 4 so as to clean a signal to remove any spurious signals or transient signals. The command signals to exercise control of the IGBT/FET drive control 15 of the voltage reducing means are determined by the digital signal processor 10 and mitigated by the logic device 9.


The reduced energy 24 then enters at least one magnetic flux concentrator 3 and then enters at least one outputting means, which is preferably at least one phase output connection 17, and is outputted to an electrically-operated device for consumption.


The system and device 1 is powered via a powering means, which is preferably a power supply unit 12 in electrical connection with the digital signal processor 10. A resetting means, which is preferably a reset switch 13, is preferably provided to permit a user to reset the device and system 1 as desired. In addition, an indicator means, such as a light emitting diode 14, may be in electrical connection withe reset switch 13 so as to alert a user if the device and system 1 needs to be reset.


The device and system 1 may optionally include at least one digital electricity meter 50 and at least one communication means, such as a USB communications interface 25, capable of interfacing with at least one computing device 16 having at least one USB port 74 and at least one window interface 40, via wired or wireless transmission. The USB communications interface 25 permits a user to monitor, display and/or configure the device and system 1 via his/her computing device 16. However, inclusion of the USB communications interface 25 is not necessary in the implementation of the device and system 1. In addition, a real time clock 49 may optionally be incorporated within the digital signal processor 10 of or otherwise connected to the energy savings device and system 1.


A user may determine the operational manner in which to use the energy savings device and system 1 of the present invention, e.g., a user may select how he/she would like to save energy by either inputting the desired RMS value, inputting the desired percentage voltage or inputting the desired percentage savings reduction into a computing device 16. For example, if a user chooses to reduce the incoming voltage by a fixed percentage, the energy savings device and system 1 permits such voltage percentage reduction and automatically lowers the voltage so as to be consistent with a maximum allowed harmonic content by establishing a lower voltage threshold. The lower voltage threshold assures that in lower or brown-out conditions, the system and device 1 does not continue to attempt to reduce the available voltage by the percentage reduction specified.



FIG. 2 is perspective plan view of a sensing means of the present invention is shown. The sensing means, which is preferably at least one magnetic flux concentrator 3, measures AC current galvanically when connected to active circuitry of the device and system 1 of the present invention. A housing 27, which preferably is made of plastic, includes a housing top half 29 and a housing bottom half 30 and a hinge 30 connecting the two halves 29 and 30, carries a circuit board 26 having a magnetic flux concentrator chip 37 mounted on the bottom side of the housing top half 29. Each half 29 and 30 includes at least one notched portion wherein when the halves 29 and 30 are joined together, at least one aperture 38 is formed for permitting a conductor 28 to extend therethrough. The utilization of said housing 27 accurately defines the distance between the magnetic flux concentrator chip 37 and the core center of the conductor 28. A window detector associated with the magnetic flux concentrator chip 37 accurately determines when current, within the negative or positive half cycles, is out of a normal ranges. In addition, the magnetic flux concentrator 3 uses an open collector Schmidt buffer to allow multiple concentrators 3 to be connected to both the analog signal conditioning device 4 and the logic device 9.


The housing 27 snaps together and bears on the conductor 28, which is preferably a cable, to ensure that the conductor 28 is held firmly against the housing 27. The housing top half 29 may be formed in various sizes so as to accommodate differing wire gauges. A plurality of apertures 38 of various sizes may be formed when the halves 29 and 30 are snapped together so as to accommodate conductors 28 of various widths. The magnetic flux concentrator 3 provides galvanic isolation of the incoming energy 19, performs accurate current measurement, is adaptable to any range of currents through multiple cable passages located within the housing 27, provides high voltage galvanic isolation, has zero harmonic distortion and superb linearity. In addition, since the current measurement range is determined by mechanical means, no changes are necessary to the printed circuit board 26. The following equation determines the approximate sensitivity:

Vout=0.06*I/(D+0.3 mm)


where I=current in the conductor 28 and D=the distance in mm from the top surface of the magnetic flux concentrator chip 37 to the center of the conductor 28.


Since no electrical connection is made to the measurement target, full galvanic isolation is achieved. Moreover, there is zero insertion loss and, therefore, no heat is dissipated nor energy lost as there is no electrical connection made nor is a shunt or a transformer used.



FIG. 3 is a circuit diagram of the sensing means of the present invention. The magnetic flux concentrator 3 measures the magnetic flux generated when an alternating electric current flows within the conductor 28. Over-current is accomplished by comparators 34 that form a window comparator. When the thresholds set by resistors 63 are exceeded by an output of the magnetic flux concentrator 3, which may yield a “Current_Hi” signal, open collector outputs of comparators 34 go low and pass to the logic device 9 and a microprocessor non-maskable input to shut-down the device and system 1. To avoid ground loop problems, the magnetic flux concentrator 3 preferably includes an integrated circuit 62 that regulates the operational voltage of the magnetic flux concentrator 3 to 5 VDC.


With reference to FIG. 4, a circuit diagram of a signal conditioning means of the present invention is shown. The signal conditioning means, which is preferably at least one analog signal conditioning device 4, cleans or conditions a 50/60 Hz sine wave analog signal so as to remove any spurious signals or transient signals prior to its transmittal to the half cycle identifier 8. If the sine wave has any noise or distortion of sufficient amplitude, this can, under certain circumstances, give rise to false zero cross detections. Thus, the inclusion of such analog signal conditioning device 4 is of importance.


To properly condition the sine wave signal, operational amplifiers 70 are utilized. An operational amplifier 70 is configured as an active, second order, low pass filter to remove or reduce harmonics and any transients or interfering signals that may be present. When utilizing such filter, however, group delay occurs wherein the group delay offsets, in time, the zero crossing of the filtered signal from the actual zero crossing point of the incoming AC sine wave. To remedy the delay, operational amplifiers 70 are provided to allow the phase change necessary to correct the zero crossing point accurately in time as required. The output of the operational amplifiers 70 is the fully conditioned 50/60 Hz sine wave signal that is connected to the A/D converter 11 of the digital signal processor 10 (see FIG. 1) for root-mean-square (RMS) value measurement. This signal is exactly half the supply rail which is necessary to enable measurement of both positive and negative half cycles. The A/D converter 11 performs the well-known 2s compliment math to enable same and requires the AC signal to deviate both positively and negatively with respect to the center or split rail voltage. The signal also enters the half cycle identifier 8.



FIGS. 5 and 6 show an oscillogram and circuitry diagram, respectively, for a volts zero crossing point determining means of the present invention. The volts zero crossing point determining means, which is preferably at least one volts zero crossing point detector 5 wherein the zero crossing point 21 is accurately determined. An operational amplifier 70 is configured as a comparator 34 with its reference at exactly half the supply voltage using half the supply rail. A comparator 34 operates at a very high gain and, as a result, switches within a few millivolts of the split rail voltage.


Additional conditioning of the zero cross signal is further performed by a Schmidt buffer 35. Subsequent to the additional signal processing, a very accurate square wave 69 accurate to a few millivolts of the actual volts zero crossing point 21 of the sine wave is produced.



FIG. 7 shows a circuit diagram of a loss detecting means and phase rotation determination and rotating means of the present invention. The loss detecting means, which is preferably at least one lost phase detection device 6, and the phase rotation determination and rotating means, which is preferably at least one phase rotation device 7, work together so as to properly prepare the signal for transmittal into the logic device 9 and digital signal processor 10 when utilizing a three-phase electrical system. The lost phase detection device 6 circuitry includes operational amplifiers 70 configured as comparators 34 where each utilizes a high value of series resistors, comprising two 0.5 Meg Ohm resistors in series, which is necessary for achieving the required working voltage of the resistors 63, and two diodes 53 connected in inverse parallel. The diodes 53 are centered around the volts zero crossing point 21 of the incoming sine wave 39 at approximately the voltage forward drop of the diodes 53, which is in turn applied to the comparator 34 that further conditions the signal suitable for passing to the logic device 9 and digital signal processor 10, resulting in the system being shut down in the absence of any of the signals.


In a three-phase electrical system, the phase rotation may be either A-B-C or A-C-B. To enable the digital signal processor 10 to properly function, the phase rotation must first be ascertained. The comparators 34 are used to detect the volts zero crossing point(s) 21 and report the point(s) 21 to the digital signal processor 10. The digital signal processor 10, in turn, makes the rotational timing through timing logic. Each of the operational amplifiers 70 act as a simple comparator 34 with the input signal, in each case provided by the inverse parallel pairs of diodes 53 in conjunction with the series resistors 63.



FIGS. 8, 9 and 10 show a circuit diagram and oscillograms, respectively, of a half cycle identifying means of the present invention. The half cycle identifying means, which is preferably at least one half cycle identifier 8, provides additional data to the logic device 9 and digital signal processor 10 by identifying whether the half cycle of the analog signal is positive or negative. This is of great importance to avoid a situation where if the IGBT/FET half cycle control transistors 54 and 58 and the IGBT/FET shunt control transistors 59, 60, 67 and 68 are simultaneously on, a short circuit would occur across the input power.


The operational amplifiers 70, which are configured as window comparators 34, have separate switching thresholds determined by at least one resistor 63. As shown in FIG. 9, there are three signals, an absolute zero cross signal 36 and two co-incident signals wherein one co-incident signal has a positive half cycle 22 and one co-incident signal has a negative half cycle 23 of an incoming sine wave 39. The design allows the window to be adjusted to provide, when required, the “dead band.”


With reference to FIGS. 11A, 11B, 11C, 11D and 11E, circuit diagrams of the routing means of the present invention are shown. The routing means, which is preferably at least one logic device 9, works in real time, outside the digital signal processor 10, to arbitrate between the on-times of the IGBT/FET half cycle control transistors 54 and 58 and the IGBT/FET shunt control transistors 59, 60, 67 and 68.


The logic device 9 performs the routing function to assure that all signals are appropriate to the instantaneous requirement and polarity of the incoming sine wave 39 and performs the pulse width modulation function so as to assure the safe operation of the energy savings device and system 1, regardless of the state of the digital signal processor 10, presence of noise, interference or transients. The circuitry of the isolator 71, as shown in FIG. 11C, permits programming of the logic device 9. The circuitry of the resistor support 79 of the logic device 9, as shown in FIG. 11D, is necessary to operate the logic device 9. As shown in FIG. 11E, the circuitry of the logic device connector 80 enables activation and deactivation of certain aspects of the logic device 9.


Dealing with a resistive load is much less demanding than dealing with a reactive load, in particular, an inductively reactive load. Currently, pulse width modulation (PWM) is defined as modulation of a pulse carrier wherein the value of each instantaneous sample of a modulating wave produces a pulse of proportional duration by varying the leading, trailing, or both edges of a pulse and which is also known as pulse-duration modulation. However, for purposes of this invention and application, PWM is defined as the modulation of a pulse carrier wherein at least one slice is removed from an area under the curve of a modulating wave. When PWM is applied directly to the incoming power, the inductive component reacts when power is removed and attempts to keep the current going and will raise its self-generated voltage until the current finds a discharge path. This circumstance, without the shunt circuitry, would destroy the half cycle control transistors.


Therefore, the logic device 9 is a “supervisor” wherein it takes the appropriate action should the digital signal processor 10 “hang-up”, if there is an over-current condition or if there is a phase loss. In any of these situations, the logic device 9 responds immediately, in real time, to safeguard the half cycle control transistors and shunt devices and the equipment connected to it.


Additionally, the logic device 9 mitigates the complex drive requirements of the IGBT/FET half cycle control transistors 54 and 58 and the IGBT/FET shunt control transistors 59, 60, 67 and 68 and, to an extent, unloads the digital signal processor 10 of this task. Since the logic device 9 controls this function, it may be performed in real time and, therefore, the timing control of the drive requirements can be held to much stricter limits than would be achieved by the digital signal processor 10. The ability to respond in real time is important to the safe, reliable operation of the energy savings device and system 1 of the present invention.



FIGS. 12A, 12B, 12C, 12D, 12E, 12F and 12g show oscillograms and circuit diagrams of a voltage reducing means of the present invention. The voltage reducing means, which preferably includes at least one IGBT/FET drive control 15, reduces the analog signals of the incoming sine wave 39, which is the amount of energy inputted into the energy savings device and system 1, by pulse width modulation wherein at least one slice is removed from an area under the curve of the modulating sine wave 39, thereby reducing energy and without the attendant harmonics previously associated with such voltage control. This technique, as shown in FIG. 12A, works in conjunction with the inherent characteristics of the IGBT/FET devices that allows the on and off triggering point to be controlled. All of the potential energy is contained in each half cycle and, in the case of a complete half cycle, has the greatest area under the curve. If each half cycle is modulated on a mark space ratio of 90%, the area under the curve is reduced by 10% and, as a result, the energy is reduced proportionally as seen in FIG. 12A.


The original shape of the input sine wave is retained and, since modulation can be made high, possibly 10's of KHz, filtering of the output is possible due to the smaller size of the wound components becoming a practical proposition. The overall effect is realized when the root-mean-square value (RMS), which is the square root of the time average of the square of a quantity or, for a periodic quantity, the average is taken over one complete cycle and which is also referred to as the effective value, is correctly measured and the output voltage is seen to be reduced by a percentage similar to the mark space ratio employed. Reduced voltage results in reduced current, thereby resulting in reduced power consumed by an end user.


Since IGBT and FET devices are unipolar in nature, in the case of AC control, it is necessary to provide at least one IGBT/FET drive control 15 to control each half cycle. Furthermore, to avoid reverse biasing, steering diodes are used to route each half cycle to the appropriate device. Additionally, many IGBT and FET devices have a parasitic diode shunting main element wherein connecting two IGBT or FET devices in inverse parallel would result in having two of the parasitic diodes in inverse parallel, thereby rendering the arrangement inoperative as a controlling element.


The diodes 53 are connected across the positive half cycle transistor 54 and the negative half cycle control transistor 58 and works ideally for a purely resistive load or a current-leading reactive load. However, when driving a load with a current lagging power factor, when the current in an inductively reactive component is suddenly removed, as is the case when the modulation occurs, the collapsing magnetic field attempts to keep the current going, similar to an electronic fly-wheel, and produces an EMF that will rise in voltage until it finds a discharge path that will enable release of the energy. With this arrangement, this “back EMF” would cause active components of the half cycle control element to fail. To prevent this from occurring, additional IGBT/FET shunt control transistors 59, 60, 67 and 68 are placed in a shunt configuration.


During the positive half cycle, the positive half cycle control transistor 54 modulates and a diode 53 is active during the complete positive half cycle. The IGBT second shunt control transistor 60 is turned fully on and a diode 53 is active. Therefore, any opposite polarity voltages resulting from the back EMF of the load are automatically clamped.


During the negative half cycle, the other devices comprised in series and shunt networks are activated in a similar manner.


During the switching transitions, a spike may be present which may last for a very short period of time. The spike is clamped by the transorb devices 52, which are capable of absorbing large amounts of energy for a very short period of time and enables vary fast response time. The transorb devices 52 also clamp any mains bourn transient signals due to lightning strikes or other sources that could otherwise damage the active components of the half cycle transistors or shunt transistors. Further, while each half cycle transistor is pulse width modulating, the other half cycle transistor is turned fully on for the precise duration of the half cycle. The duties of these half cycle transistors reverse during the next half cycle. This process provides complete protection against the back EMF signals discussed above. This arrangement is necessary, especially near the zero crossing time when both shunt elements are in transition.


Each of the IGBT/FET half cycle control transistors 54 and 58 and the IGBT/FET shunt control transistors 59, 60, 67 and 68 have insulated gate characteristics that require the devices to be enhanced to enable them to turn on. This enhancement voltage is preferably 12 Volts in magnitude and is preferably supplied by a floating power supply, preferably one for each pair. This is only possible since the IBGT/FET devices are operated in the common emitter mode in the case of the IGBT's and in the common source mode in the case of the FET's; otherwise, four isolated power supplies would be required for each phase. Each of the pairs requires a separate drive signal that is provided by the isolated, optically-coupled drivers 66. These drivers 66 make use of the isolated supplies and serve to very rapidly turn-on and turn-off each power device. These drivers 66 are active in both directions, which is necessary since the input capacitance of the power devices are high and have to be actively discharged rapidly at the turn-off point and charged rapidly at the turn-on point.


The problem with direct pulse width modulation is when driving an inductively reactive load as when the IGBT modulates off, there is a back EMF that needs to be clamped. Referring to FIG. 12B, an incoming sine wave 39 that is applied to the positive half cycle control transistor 54 and the negative half cycle control transistor 58 is shown. Normally, these half cycle control transistors 54 and 58 are in the “off” condition and need to be driven on. During the positive half cycle, the positive half cycle control transistor 54 is modulated and works in conjunction with a diode 53 to pass the modulated positive half cycle to a line output terminal. The IGBT second shunt control transistor 60 is on for the duration of the half cycle and operates in conjunction with a diode 53 so as to clamp the back EMF to ground. During the positive half cycle, the negative half cycle control transistor 58 is turned on fully and its on condition is supported by a diode 53. These diodes 53 perform the appropriate steering of the signals.


Due to modulation of the positive half cycle, a back EMF signal occurs. Since the negative half cycle control transistor 58 is on during this time, the negative back EMF is passed through a diode 53 to be clamped at the simultaneous AC positive half cycle voltage.


Although no modulation is applied to the IGBT first shunt control transistor 59 and the IGBT second shunt control transistor 60, these transistors 59 and 60 work in conjunction with diodes 53 in a similar manner as set forth above.


As shown in FIG. 12B, which is an oscillogram of the voltage reducing means of the IGBT-based present invention, during the positive half cycle 22, a drive signal is applied to the negative half cycle control transistor 85 and a drive signal is applied to the IGBT second shunt control transistor 87. During the negative half cycle 23, a drive signal is applied to the positive half cycle control transistor 84 and a drive signal is applied to the IGBT first shunt control transistor 86. The positive half cycle drive signal 82 applied to the positive half cycle control transistor 54 and the negative half cycle drive signal 83 applied to the negative half cycle control transistor 58 are also shown.


Similarly, as shown in FIG. 12E, which is an oscillogram of the voltage reducing means of the FET-based present invention, during the positive half cycle 22, a drive signal is applied to the negative half cycle control transistor 85 and a drive signal is applied to the FET second shunt control transistor 89. During the negative half cycle 23, a drive signal is applied to the positive half cycle control transistor 84 and a drive signal is applied to the FET first shunt control transistor 88. The positive half cycle drive signal 82 applied to the positive half cycle control transistor 54 and the negative half cycle drive signal 83 applied to the negative half cycle control transistor 58 are also shown.


In summary, there are two clamping strategem used, the first for the positive half cycle and the second for the negative half cycle. During the positive half cycle, when the positive half cycle control transistor 54 is modulated, the negative half cycle control transistor 58 and the second shunt control transistor 60 are on. During the negative half cycle, when the negative half cycle control transistor 58 is modulated, the positive half cycle control transistor 54 and the IGBT first shunt control transistor 59 are on.


The hardware utilized in the IGBT-based and FET-based energy savings device and method 1 of the present invention is identical with the only difference being the IGBT/FET half cycle control transistors 54 and 58 and the IGBT/FET shunt control transistors 59, 60, 67 and 68. The circuitry diagrams of the IGBT-based circuitry FIG. 12C and the IGBT based driver FIG. 12D and the FET-based circuitry FIG. 12E and the FET-based driver FIG. 12F are shown for comparison purposes.


With reference to FIG. 13, a circuit diagram of a combined resetting means and indicator means of the present invention is shown. The resetting means, which is preferably at least one reset switch 13, and indicator means, which is preferably at least one light emitting diode 14, work together so as to indicate when the IGBT/FET-based energy savings device and system 1 is not properly working and to permit a user to reset the device and system 1 as needed. Preferably, the light emitting diode 14 will indicate that the device and system 1 is working properly by flashing on/off. When in a fault condition, the light emitting diode 14 preferably changes to an uneven pattern that is immediately obvious and recognizable as a fault condition.



FIG. 14 is a circuit diagram of a power supply unit 12 of a powering means of the present invention. The powering means, which is preferably at least one power supply unit 12, accepts a variety of inputs, including, but not limited to, single phase 80 Vrms to 265Vrms, bi-phase 80Vrms to 600Vrms, three-phase 80Vrms to 600Vrms and 48 Hz to 62 Hz operation.


The power supply unit 12 is fully-isolated and double-regulated in design. At the input, a rectifier 72 composed of diodes 53 accepts single, bi- and three-phase power. The power is applied to a switching regulator 90 and integrated circuit 62 via a transformer 57. In view of the large voltages existing across the DC terminals, the switching regulator 90 and integrated circuit 62 is supplemented by a FET transistor 73 employed in a StackFET configuration in order to raise its working voltage. The secondary of transformer 57 has a diode 53 and a reservoir capacitor 56. The DC voltage across capacitor 56 is passed via the network resistors 63 and a Zener diode 75 to an optical isolator 65 and finally to the feedback terminals. Use of the optical isolator 65 guarantees galvanic isolation between the input and the supply output (6.4V DC). Finally, the output of the linear voltage regulators 81 (3.3 VA DC) is passed to a operational amplifier 70, which is configured as a unity gain buffer with two resistors 63 that set the split rail voltage. The main neutral is connected to this split rail point and also a zero Ohm resistor. An inductor 78 isolates the supply rail digital (+3.3V) from the analog (3.3 VA) and reduce noise.


Next, FIGS. 15A, 15B, 15C, 15D and 15E show the circuitry of a communication means of the present invention. The communication means, which is preferably at least one USB communications interface 25, permits a user to monitor and set the parameters of the energy savings device and system 1 of the present invention as desired.


The circuitry of a USB communications interface 25 is shown in FIG. 15B, an isolator block 71 utilized in isolating the USB communications interface 25 from the digital signal processor 10 is shown in FIG. 15C and first and second connectors 76 and 77 for connecting the communications means to the digital signal processor 10 are shown in FIGS. 15D and 15E.


Since the main printed circuit board is not isolated from neutral, it is necessary to galvanically isolate the USB communications interface 25. Use is made of the built-in serial communications feature of the digital signal processor 10 to serially communicate with the communication means 46. Signals, on the user side of the isolation barrier, are applied to an integrated circuit 62, which is a device that takes serial data and translates it to USB data for direct connection to a computing device 16 via a host USB port 74. The host USB 5V power is used to power the communication means 46 and voids the necessity of providing isolated power from the unit. Preferably, there are two activity light emitting diodes 14, that indicate activity on the TX (transmit) and RX (receive) channels. Communications preferably operates at 9600 Baud, which is adequate in view of the small amount of data passed.


Although the inclusion of a communications means is not necessary in the performance of the energy savings device and system 1, it is a feature that permits easier use of the device and system 1.


Finally, with reference to FIGS. 16 and 17, screen shots of a windows interface 40 of the present invention are shown. The windows interface 40 is displayed on the computing device 16 and permits a user to monitor and configure the energy savings device and system 1 as desired. A main monitoring screen 41 having a plurality of fields 42 in which an end user may adjust the energy savings device and system 1 are provided. For example, the fields 42 may include an operational mode field 43, a phase field 44, a startup field 45, a calibration field 46 and a setpoints field 47.


In the operational field 43, a user may select the manner in which he/she/it desires to conserve energy. The manners include voltage reduction percentage wherein the output Volts is adjusted by a fixed percentage, savings reduction percentage wherein the output Volts is aimed at achieving a savings percentage and voltage regulation wherein the root mean squared Volts output is a pre-set value.


The phase field 44 permits a user to select the phase type used in connection with the energy savings device and system 1, i.e., single phase, bi-phase or three phase.


The startup field 45 permits a user to configure the system and device 1 to randomly start and/or to have a delayed or “soft start” wherein the user input the delay time in seconds in which the system and device will start.


The calibration field 46 permits a user to input the precise calibrations desired and/or to rotate the phases.


The setpoints field 47 displays the settings selected by the user and shows the amount of energy saved by utilizing the energy savings device and system 1 as voltage regulation, voltage reduction percentage or power savings reduction percentage. With respect to percentage voltage reduction, the lower limit RMS is set below the incoming voltage passed therethrough to permit the incoming voltage to be passed through when it is less than or equal to the lower limit voltage. With respect to the percentage savings reduction, the lower limit RMS is set below the incoming voltage passed therethrough.


Indicators 48 are provided on the windows interface 40 display operating current, operating voltage, line frequency, calculated power savings and phase rotation.


A real time clock 49 may be incorporated into the windows interface 40 to allow programming of additional voltage reduction for a predetermined time and a predetermined operational time, e.g., for seasons, days of the week, hours of the day, for a predetermined operational time. In addition, a user may program the energy savings device and system 1 to operate during various times of the day. The real time clock 49 is set through a communications port or fixed to allow the selection of defined seasonal dates and time when, through experience, are known to exhibit power grid overload. During these times, the system allows further reduction of the regulated AC voltage, thereby reducing the load on the grid. Multiple time can be defined each with its own additional percentage reduction or voltage drop.


The digital electricity meter 50 provides a means to log statistical data on power usage, power factor and surges. The digital electricity meter 50 also provides the ability to include capacitors for power factor correction, operates on single, bi and three-phase systems and operates on all world wide voltages. It may be used remotely or locally to disable or enable the user's power supply at will by the provider. In addition, the digital electricity meter 50 may detect when the energy savings device and system 1 has been bridged by an end user attempting to avoid paying for energy consumption wherein the provider is alerted to such abuse. Finally, use of the real time clock 49 permits a user and/or provider to reduce the consumption of power at selected times of a day or for a selected time period, thereby relieving and/or eliminating brown-out conditions.


It is to be understood that while a preferred embodiment of the invention is illustrated, it is not to be limited to the specific form or arrangement of parts herein described and shown. It will be apparent to those skilled in the art that various changes may be made without departing from the scope of the invention and the invention is not be considered limited to what is shown and described in the specification and drawings.

Claims
  • 1. An energy savings device comprising: at least one phase input connection configured to input a predetermined amount of energy having at least one analog signal;at least one volts zero crossing point detector configured to determine at least one zero crossing point of said at least one analog signal;at least one half cycle identifier configured to identify at least one positive half cycle of said at least one analog signal and at least one negative half cycle of said at least one analog signal;at least one logic device configured to route said at least one positive half cycle of said at least one analog signal and said at least one negative half cycle of said at least one analog signal to at least one digital signal processor configured to process said at least one analog signal;at least one drive control configured to reduce said predetermined amount of energy by providing pulse width modulation to said at least one analog signal to yield a reduced amount of energy, wherein said at least one drive control is in electrical connection with said at least one digital signal processor; andat least one phase output connection configured to output said reduced amount of energy, wherein said at least one drive control comprises a positive half cycle control transistor configured to provide pulse width modulation to said at least one positive half cycle of said at least one analog signal, a negative half cycle control transistor configured to provide pulse width modulation to said at least one negative half cycle of said at least one analog signal, a first shunt control transistor and a second shunt control transistor configured as routing switches to clamp a back electromotive force.
  • 2. The energy savings device of claim 1 further comprising: at least one sensing means for sensing said predetermined amount of energy.
  • 3. The energy savings device of claim 2, wherein said at least one sensing means measures said predetermined amount of incoming energy via galvanic isolation.
  • 4. The energy savings device of claim 1 further comprising: at least one lost phase detection device configured to prepare said at least one analog signal for inputting into said at least one half cycle identifier.
  • 5. The energy savings device of claim 4, wherein said at least one logic device is in electrical connection with said at least one lost phase detection device.
  • 6. The energy savings device of claim 1 further comprising: at least one power supply unit in electrical connection with said energy savings device configured to power said energy savings device.
  • 7. The energy savings device of claim 1 further comprising: at least one floating power supply in electrical connection with said at least one drive control.
  • 8. The energy savings device of claim 1 further comprising: at least one computing device in electrical connection with said energy savings device.
  • 9. The energy savings device of claim 1 further comprising: at least one communications interface in electrical connection with said at least one digital signal processor.
  • 10. The energy savings device of claim 9, wherein said at least one communications interface is at least one USB communications interface.
  • 11. The energy savings device of claim 9, wherein said at least one communications interface permits a user to monitor said predetermined amount of energy inputted into said energy savings device and said reduced amount of energy outputted from said energy savings device.
  • 12. The energy savings device of claim 1 further comprising: at least one digital electricity meter in electrical connection with said at least one digital signal processor.
  • 13. The energy savings device of claim 1, wherein said positive half cycle control transistor and said negative half cycle control transistor are IGBT devices.
  • 14. The energy savings device of claim 1, wherein said positive half cycle control transistor and said negative half cycle control transistor are FET devices.
  • 15. The energy savings device of claim 1, wherein said first shunt control transistor and said second shunt control transistor are IGBT devices.
  • 16. The energy savings device of claim 1, wherein said first shunt control transistor and said second shunt control transistor are FET devices.
  • 17. The energy savings device of claim 1, wherein said at least one digital signal processor comprises at least one real-time clock.
  • 18. The energy savings device of claim 1, wherein said at least one digital signal processor comprises at least one analog-to-digital converter.
  • 19. The energy savings device of claim 1, wherein said at least one digital signal processor is in electrical connection with said at least one logic device.
  • 20. The energy savings device of claim 1, wherein said at least one logic device is in electrical connection with said at least one half cycle identifier.
  • 21. The energy savings device of claim 1, wherein said at least one logic device is in electrical connection with said at least one volts zero crossing point detector.
  • 22. The energy savings device of claim 1, wherein said at least one logic device is in electrical connection with said at least one drive control.
  • 23. The energy savings device of claim 1 further comprising: at least one analog signal conditioning device configured to condition said at least one analog signal for inputting into said at least one half cycle identifier.
  • 24. The energy savings device of claim 23, wherein said at least one analog signal conditioning device comprises a first filter for removing or reducing harmonics and transients or interfering signals of said at least one analog signal.
  • 25. The energy savings device of claim 24, wherein said at least one analog signal conditioning device comprises a second filter for permitting at least one phase change if necessary.
  • 26. The energy savings device of claim 1, wherein said at least one volts zero crossing point detector comprises a comparator and a Schmidt buffer.
  • 27. The energy savings device of claim 26, wherein said comparator has a reference point of approximately half a supply voltage.
  • 28. The energy savings device of claim 1 further comprising: at least one phase rotation device configured to prepare said at least one analog signal for inputting into said at least one half cycle identifier.
  • 29. The energy savings device of claim 28, wherein said at least one logic device is in electrical connection with said at least one phase rotation device.
  • 30. The energy savings device of claim 1 further comprising: at least one reset switch in electrical connection with said at least one digital signal processor.
  • 31. The energy savings device of claim 30 further comprising: at least one light emitting diode in electrical connection with said at least one reset switch.
  • 32. The energy savings device of claim 1, wherein said at least one half cycle identifier identifies an absolute zero crossing of said at least one analog signal.
  • 33. The energy savings device of claim 1, wherein said at least one logic device is programmable.
  • 34. The energy savings device of claim 1, wherein said at least one logic device operates in real-time.
  • 35. The energy savings device of claim 1, wherein said at least one phase input connection is a single phase input system.
  • 36. The energy savings device of claim 1, wherein said at least one phase output connection is a single phase output system.
  • 37. The energy savings device of claim 1, wherein said at least one phase input connection is bi-phase input system.
  • 38. The energy savings device of claim 1, wherein said at least one phase output connection is a bi-phase output system.
  • 39. The energy savings device of claim 1, wherein said at least one phase input connection is a three-phase input system.
  • 40. The energy savings device of claim 1, wherein said at least one phase output connection is a three-phase output system.
  • 41. An energy savings system comprising: an energy savings device comprising: at least one phase input connection configured to input a predetermined amount of energy having at least one analog signal;at least one volts zero crossing point detector configured to determine at least one zero crossing point of said at least one analog signal;at least one half cycle identifier configured to identify at least one positive half cycle of said at least one analog signal and at least one negative half cycle of said at least one analog signal;at least one logic device configured to route said at least one positive half cycle of said at least one analog signal and said at least one negative half cycle of said at least one analog signal to at least one digital signal processor configured to process said at least one analog signal;at least one communications interface in electrical connection with said at least one digital signal processor;at least one drive control configured to reduce said predetermined amount of energy by providing pulse width modulation to said at least one analog signal to yield a reduced amount of energy, wherein said at least one drive control is in electrical connection with said at least one digital signal processor; andat least one phase output connection configured to output said reduced amount of energy, wherein said at least one drive control comprises a positive half cycle control transistor configured to provide pulse width modulation to said at least one positive half cycle of said at least one analog signal, a negative half cycle control transistor configured to provide pulse width modulation to said at least one negative half cycle of said at least one analog signal, a first shunt control transistor and a second shunt control transistor configured as routing switches to clamp a back electromotive force;a power supply unit in electrical connection with said energy savings device configured to power said energy savings device; anda computing device comprising a window interface and a communications interface in electrical connection with said at least one communications interface of said energy savings device.
  • 42. The energy savings system of claim 41 further comprising: at least one sensing means for sensing said predetermined amount of energy.
  • 43. The energy savings system of claim 42, wherein said at least one sensing means measures said predetermined amount of incoming energy via galvanic isolation.
  • 44. The energy savings system of claim 41 further comprising: at least one reset switch in electrical connection with said at least one digital signal processor of said energy savings device.
  • 45. The energy savings system of claim 44 further comprising: at least one light emitting diode in electrical connection with said at least one reset switch.
  • 46. The energy savings system of claim 41, the energy savings device further comprising: at least one lost phase detection device configured to prepare said at least one analog signal for inputting into said at least one half cycle identifier.
  • 47. The energy savings system of claim 46, wherein said at least one logic device is in electrical connection to said at least one lost phase detection device.
  • 48. The energy savings system of claim 41, the energy savings device further comprising: at least one floating power supply in electrical connection with said at least one drive control.
  • 49. The energy savings system of claim 41, the energy savings device further comprising: at least one digital electricity meter in electrical connection with said at least one digital signal processor.
  • 50. The energy savings system of claim 41, wherein the positive half cycle control transistor and the negative half cycle control transistor are IGBT devices.
  • 51. The energy savings system of claim 41, wherein the positive half cycle control transistor and the negative half cycle control transistor are FET devices.
  • 52. The energy savings system of claim 41, wherein the first shunt control transistor and the second shunt control transistor are IGBT devices.
  • 53. The energy savings system of claim 41, wherein the first shunt control transistor and the second shunt control transistor are FET devices.
  • 54. The energy savings system of claim 41, wherein said at least one digital signal processor comprises at least one real-time clock.
  • 55. The energy savings system of claim 41, wherein said at least one digital signal processor comprises at least one analog-to-digital converter.
  • 56. The energy savings system of claim 41, wherein said at least one digital signal processor is in electrical connection with said at least one logic device.
  • 57. The energy savings system of claim 41, wherein said at least one logic device is in electrical connection with said at least one half cycle identifier.
  • 58. The energy savings system of claim 41, wherein said at least one logic device is in electrical connection with said at least one volts zero crossing point detector.
  • 59. The energy savings system of claim 41, wherein said at least one logic device is in electrical connection with said at least one drive control.
  • 60. The energy savings system of claim 41, the energy savings device further comprising: at least one analog signal conditioning device configured to condition said at least one analog signal for inputting into said at least one half cycle identifier.
  • 61. The energy savings system of claim 60, wherein said at least one analog signal conditioning device comprises a first filter for removing or reducing harmonics and transients or interfering signals of said at least one analog signal.
  • 62. The energy savings system of claim 61, wherein said at least one analog signal conditioning device has a second filter for permitting at least one phase change if necessary.
  • 63. The energy savings system of claim 41, wherein said at least one volts zero crossing point detector comprises a comparator and a Schmidt buffer.
  • 64. The energy savings system of claim 63, wherein said comparator has a reference point of approximately half a supply voltage.
  • 65. The energy savings system of claim 41, the energy savings device further comprising: at least one phase rotation device configured to prepare said at least one analog signal for inputting into said at least one half cycle identifier.
  • 66. The energy savings system of claim 65, wherein said at least one logic device is in electrical connection to said at least one phase rotation device.
  • 67. The energy savings system of claim 41, wherein said at least one communications interface is at least one USB communications interface.
  • 68. The energy savings system of claim 41, wherein said at least one communications interface permits a user to monitor said predetermined amount of energy inputted into said energy savings system and said reduced energy outputted from said energy savings system.
  • 69. The energy savings systems of claim 41, wherein said at least one half cycle identifier identifies an absolute zero crossing of said at least one analog signal.
  • 70. The energy savings systems of claim 41, wherein said at least one logic device is programmable.
  • 71. The energy savings systems of claim 41, wherein said at least one logic device operates in real-time.
  • 72. The energy savings systems of claim 41, wherein said at least one phase input connection is a single phase input system.
  • 73. The energy savings systems of claim 41, wherein said at least one phase output connection is a single phase output system.
  • 74. The energy savings systems of claim 41, wherein said at least one phase input connection is a bi-phase power system.
  • 75. The energy savings systems of claim 41, wherein said at least one phase output connection is a bi-phase output system.
  • 76. The energy savings systems of claim 41, wherein said at least one phase input connection is a three-phase power system.
  • 77. The energy savings systems of claim 41, wherein said at least one phase output connection is a three-phase output system.
  • 78. An energy savings system comprising: means for inputting a predetermined amount of incoming energy having at least one analog signal, the at least one analog signal comprising a plurality of slices;means for determining at least one zero crossing point of said at least one analog signal;means for identifying at least one positive half cycle and at least one negative half cycle of said at least one analog signal;means for routing said at least one positive half cycle of said at least one analog signal and said at least one negative half cycle of said at least one analog signal to at least one processing means for processing said at least one analog signal;means for reducing said at least one analog signal of said predetermined amount of energy to yield a reduced amount of energy, wherein the means for reducing is configured to remove at least one of the plurality of slices from the at least one analog signal; andmeans for outputting said reduced energy.
  • 79. The energy savings system of claim 78 further comprising: means for sensing said predetermined amount of incoming energy.
  • 80. The energy savings system of claim 78 further comprising: means for conditioning said at least one analog signal.
  • 81. The energy savings system of claim 78 further comprising: means for lost phase detection of said at least one analog signal.
  • 82. The energy savings system of claim 78 further comprising: means for phase rotation of said at least one analog signal.
  • 83. The energy savings system of claim 78 further comprising: means for communicating with at least one computing device.
  • 84. The energy savings system of claim 78 further comprising: means for resetting said energy savings system.
  • 85. The energy savings system of claim 78, wherein said means for reducing comprises a positive half cycle control transistor configured for providing pulse width modulation to said at least one positive half cycle of said at least one analog signal, a negative half cycle control transistor configured for providing pulse width modulation to said at least one negative half cycle of said at least one analog signal, and a first shunt control transistor and a second shunt control transistor configured as routing switches to clamp a back electromotive force.
  • 86. The energy savings system of claim 85, wherein the positive half cycle control transistor and the negative half cycle control transistor are IGBT devices.
  • 87. The energy savings system of claim 85, wherein the positive half cycle control transistor and the negative half cycle control transistor are FET devices.
  • 88. The energy savings system of claim 85, wherein the first shunt control transistor and the second shunt control transistor are IGBT devices.
  • 89. The energy savings system of claim 85, wherein the first shunt control transistor and the second shunt control transistor are FET devices.
  • 90. A method of reducing energy consumption by an energy savings device comprising: inputting a predetermined amount of energy having at least one analog signal, the at least one analog signal comprising a plurality of slices;determining at least one zero crossing point of said at least one analog signal;identifying at least one positive half cycle of said at least one analog signal and at least one negative half cycle of said at least one analog signal;processing said at least one analog signal;reducing said predetermined amount of energy by removing at least one of the plurality of slices from the at least one analog signal using pulse width modulation; andoutputting a reduced amount of energy.
  • 91. The method of claim 90 further comprising: sensing said predetermined amount of energy.
  • 92. The method of claim 90 further comprising: conditioning said at least one analog signal.
  • 93. The method of claim 90 further comprising: detecting lost phase of said at least one analog signal.
  • 94. The method of claim 90 further comprising: determining phase rotation of said at least one analog signal.
  • 95. The method of claim 90 further comprising: routing said at least one positive half cycle of said at least one analog signal and said at least one negative half cycle of said at least one analog signal to processing means in advance of processing.
  • 96. The method of claim 90, wherein said reducing comprises: providing pulse width modulation to said at least one positive half cycle of said at least one analog signal;providing pulse width modulation to said at least one negative half cycle of said at least one analog signal; andproviding a plurality of routing switches to clamp a back electromotive force.
CROSS REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. application Ser. No. 12/185,442, filed Aug. 4, 2008, now U.S. Pat. No. 8,085,009 to issue on Dec. 27, 2011, which claims the benefit of U.S. Provisional Applications Nos. 60/964,587 filed Aug. 13, 2007; 60/966,124 filed Aug. 24, 2007; 61/009,844 filed Jan. 3, 2008; 61/009,846 filed Jan. 3, 2008; 61/009,845 filed Jan. 3, 2008; and 61/009,806 filed Jan. 3, 2008, all of which are incorporated by reference herein in their entirety for all purposes.

US Referenced Citations (342)
Number Name Date Kind
2276358 Vickers Mar 1942 A
2345933 Ibbotson et al. Apr 1944 A
3440512 Hubby Apr 1969 A
3470443 Nola et al. Sep 1969 A
3470446 Nola et al. Sep 1969 A
3523228 Nola et al. Aug 1970 A
3541361 Nola Nov 1970 A
3582774 Forgacs Jun 1971 A
3671849 Kingston Jun 1972 A
3718846 Bejach Feb 1973 A
3740629 Kohlhagen Jun 1973 A
3753472 Dwbwad et al. Aug 1973 A
3851995 Mills Dec 1974 A
3860858 Nola Jan 1975 A
3953777 McKee Apr 1976 A
3959719 Espelage May 1976 A
3976987 Anger Aug 1976 A
4039946 Nola Aug 1977 A
4052648 Nola Oct 1977 A
4096436 Cook et al. Jun 1978 A
4145161 Skinner Mar 1979 A
4168491 Phillips et al. Sep 1979 A
4220440 Taylor Sep 1980 A
4266177 Nola May 1981 A
4324987 Sullivan, II et al. Apr 1982 A
4333046 Lee Jun 1982 A
4346339 Lewandowski Aug 1982 A
4353025 Dobkin Oct 1982 A
4363605 Mills Dec 1982 A
4388585 Nola Jun 1983 A
4391155 Bender Jul 1983 A
4392100 Stanton Jul 1983 A
4400657 Nola Aug 1983 A
4404511 Nola Sep 1983 A
4412167 Green et al. Oct 1983 A
4413676 Kervin Nov 1983 A
4417190 Nola Nov 1983 A
4420787 Tibbits Dec 1983 A
4426614 Nola Jan 1984 A
4429269 Brown Jan 1984 A
4429578 Darrel et al. Feb 1984 A
4433276 Nola Feb 1984 A
4439718 Nola Mar 1984 A
4453260 Inagawa et al. Jun 1984 A
4454462 Spann Jun 1984 A
4456871 Stich Jun 1984 A
4469998 Nola Sep 1984 A
4489243 Nola Dec 1984 A
4490094 Gibbs Dec 1984 A
4513240 Putman Apr 1985 A
4513274 Halder Apr 1985 A
4513361 Rensink Apr 1985 A
4551812 Gurr et al. Nov 1985 A
4561299 Orlando et al. Dec 1985 A
4616174 Jorgensen Oct 1986 A
4644234 Nola Feb 1987 A
4649287 Nola Mar 1987 A
4659981 Lumsden Apr 1987 A
4679133 Moscovici Jul 1987 A
4689548 Mechlenburg Aug 1987 A
4706017 Wilson Nov 1987 A
4716357 Cooper Dec 1987 A
4819180 Hedman et al. Apr 1989 A
4841404 Marshall Jun 1989 A
4859926 Wolze Aug 1989 A
4876468 Libert Oct 1989 A
4971522 Butlin Nov 1990 A
4997346 Bohon Mar 1991 A
5003192 Beigel Mar 1991 A
5044888 Hester, II Sep 1991 A
5066896 Bertenshaw et al. Nov 1991 A
5134356 El-Sharkawl et al. Jul 1992 A
5136216 Wills et al. Aug 1992 A
5180970 Ross Jan 1993 A
5202621 Reischer Apr 1993 A
5204595 Opal et al. Apr 1993 A
5214621 Maggelet et al. May 1993 A
5222867 Walker, Sr. Jun 1993 A
5227735 Lumsden Jul 1993 A
5239255 Schanin et al. Aug 1993 A
5259034 Lumsden Nov 1993 A
5281100 Diederich Jan 1994 A
5299266 Lumsden Mar 1994 A
5332965 Wolf et al. Jul 1994 A
5350988 Le Sep 1994 A
5362206 Westerman Nov 1994 A
5425623 London Jun 1995 A
5442335 Cantin et al. Aug 1995 A
5481140 Maruyama et al. Jan 1996 A
5481225 Lumsden et al. Jan 1996 A
5506484 Munro et al. Apr 1996 A
5543667 Shavit et al. Aug 1996 A
5559685 Lauw et al. Sep 1996 A
5572438 Ehlers et al. Nov 1996 A
5600549 Cross Feb 1997 A
5602462 Stich Feb 1997 A
5614811 Sagalovich et al. Mar 1997 A
5615097 Cross Mar 1997 A
5625236 Lefebvre et al. Apr 1997 A
5635826 Sugawara Jun 1997 A
5637975 Pummer et al. Jun 1997 A
5652504 Bangerter Jul 1997 A
5699276 Roos Dec 1997 A
5732109 Takahashi Mar 1998 A
5747972 Baretich et al. May 1998 A
5754036 Walker May 1998 A
5821726 Anderson Oct 1998 A
5828200 Ligman et al. Oct 1998 A
5856916 Bennet Jan 1999 A
5880578 Oliveira et al. Mar 1999 A
5909138 Stendahl Jun 1999 A
5936855 Salmon Aug 1999 A
5942895 Popovic et al. Aug 1999 A
5945746 Tracewell et al. Aug 1999 A
5946203 Jiang et al. Aug 1999 A
5994898 DiMarzio et al. Nov 1999 A
6005367 Rohde Dec 1999 A
6013999 Howard et al. Jan 2000 A
6055171 Ishii et al. Apr 2000 A
6104737 Mahmoudi Aug 2000 A
6118239 Kadah Sep 2000 A
6178362 Woolard et al. Jan 2001 B1
6184672 Berkcan Feb 2001 B1
6191568 Poletti Feb 2001 B1
6198312 Floyd Mar 2001 B1
6225759 Bogdan et al. May 2001 B1
6259610 Karl et al. Jul 2001 B1
6265881 Meliopoulos et al. Jul 2001 B1
6274999 Fujii et al. Aug 2001 B1
6297610 Bauer et al. Oct 2001 B1
6325142 Bosley et al. Dec 2001 B1
6326773 Okuma et al. Dec 2001 B1
6346778 Mason et al. Feb 2002 B1
6351400 Lumsden Feb 2002 B1
6400098 Pun Jun 2002 B1
6411155 Pezzani Jun 2002 B2
6414455 Watson Jul 2002 B1
6414475 Dames et al. Jul 2002 B1
6426632 Clunn Jul 2002 B1
6449567 Desai et al. Sep 2002 B1
6459606 Jadric Oct 2002 B1
6483247 Edwards et al. Nov 2002 B2
6486641 Scoggins et al. Nov 2002 B2
6489742 Lumsden et al. Dec 2002 B2
6490872 Beck et al. Dec 2002 B1
6495929 Bosley et al. Dec 2002 B2
6528957 Luchaco Mar 2003 B1
6534947 Johnson et al. Mar 2003 B2
6548988 Duff, Jr. Apr 2003 B2
6548989 Duff Apr 2003 B2
6553353 Littlejohn Jul 2003 B1
6592332 Stoker Jul 2003 B1
6599095 Takada et al. Jul 2003 B1
6618031 Bohn, Jr. et al. Sep 2003 B1
6643149 Arnet et al. Nov 2003 B2
6650554 Darshan Nov 2003 B2
6657404 Clark et al. Dec 2003 B1
6662821 Jacobsen et al. Dec 2003 B2
6664771 Scoggins et al. Dec 2003 B2
6678176 Lumsden Jan 2004 B2
6690594 Amarillas et al. Feb 2004 B2
6690704 Fallon et al. Feb 2004 B2
6718213 Enberg Apr 2004 B1
6724043 Ekkanath Madathil Apr 2004 B1
6747368 Jarrett, Jr. Jun 2004 B2
6770984 Pai Aug 2004 B2
6774610 Orozco Aug 2004 B2
6781423 Knoedgen Aug 2004 B1
6801022 Fa Oct 2004 B2
6809678 Vera et al. Oct 2004 B2
6836099 Amarillas et al. Dec 2004 B1
6849834 Smolenski et al. Feb 2005 B2
6891478 Gardner May 2005 B2
6912911 Oh et al. Jul 2005 B2
6952355 Riggio et al. Oct 2005 B2
6963195 Berkcan Nov 2005 B1
6963773 Waltman et al. Nov 2005 B2
7010363 Donnelly et al. Mar 2006 B2
7019474 Rice et al. Mar 2006 B2
7019498 Pippin et al. Mar 2006 B2
7019992 Weber Mar 2006 B1
7019995 Niemand et al. Mar 2006 B2
7045913 Ebrahim et al. May 2006 B2
7049758 Weyhrauch et al. May 2006 B2
7049976 Hunt et al. May 2006 B2
7061189 Newman, Jr. et al. Jun 2006 B2
7062361 Lane Jun 2006 B1
7068184 Yee et al. Jun 2006 B2
7069161 Gristina et al. Jun 2006 B2
7081729 Chang et al. Jul 2006 B2
7091559 Fragapane et al. Aug 2006 B2
7106031 Hayakawa et al. Sep 2006 B2
7119576 Langhammer et al. Oct 2006 B1
7123491 Kusumi Oct 2006 B1
7136724 Enberg Nov 2006 B2
7136725 Paciorek et al. Nov 2006 B1
7157898 Hastings et al. Jan 2007 B2
7164238 Kazanov et al. Jan 2007 B2
7168924 Beck et al. Jan 2007 B2
7188260 Shaffer et al. Mar 2007 B1
7205822 Torres et al. Apr 2007 B2
7211982 Chang et al. May 2007 B1
7227330 Swamy et al. Jun 2007 B2
7245100 Takahashi Jul 2007 B2
7250748 Hastings et al. Jul 2007 B2
7256564 MacKay Aug 2007 B2
7259546 Hastings et al. Aug 2007 B1
7263450 Hunter Aug 2007 B2
7279860 MacKay Oct 2007 B2
7288911 MacKay Oct 2007 B2
7298132 Woolsey et al. Nov 2007 B2
7298133 Hastings et al. Nov 2007 B2
7301308 Aker et al. Nov 2007 B2
7309973 Garza Dec 2007 B2
7330366 Lee Feb 2008 B2
7336463 Russell et al. Feb 2008 B2
7336514 Amarillas et al. Feb 2008 B2
7349765 Reaume et al. Mar 2008 B2
7355865 Royak et al. Apr 2008 B2
7358724 Taylor et al. Apr 2008 B2
7378821 Simpson, III May 2008 B2
7386713 Madter et al. Jun 2008 B2
7394397 Nguyen et al. Jul 2008 B2
7397212 Turner Jul 2008 B2
7397225 Schulz Jul 2008 B2
7412185 Hall et al. Aug 2008 B2
7417410 Clark, III et al. Aug 2008 B2
7417420 Shuey et al. Aug 2008 B2
7436233 Yee et al. Oct 2008 B2
7446514 Li et al. Nov 2008 B1
7456903 Osawa et al. Nov 2008 B2
7525296 Billig et al. Apr 2009 B2
7528503 Rognli et al. May 2009 B2
7561977 Horst et al. Jul 2009 B2
7602136 Garza Oct 2009 B2
7605495 Achart Oct 2009 B2
7615989 Kojori Nov 2009 B2
7622910 Kojori Nov 2009 B2
7667411 Kim Feb 2010 B2
7693610 Ying Apr 2010 B2
7719214 Leehey May 2010 B2
7746003 Verfuerth et al. Jun 2010 B2
7768221 Boyadjieff et al. Aug 2010 B2
7788189 Budike, Jr. Aug 2010 B2
7791326 Dahlman et al. Sep 2010 B2
7797084 Miwa Sep 2010 B2
7848897 Williams, Jr. Dec 2010 B2
7882383 May et al. Feb 2011 B2
7911173 Boyadjieff Mar 2011 B2
7919958 Oettinger et al. Apr 2011 B2
7977842 Lin Jul 2011 B2
8004255 Lumsden Aug 2011 B2
8058923 Yoshimura et al. Nov 2011 B2
8064510 Babanezhad Nov 2011 B1
8085009 Lumsden Dec 2011 B2
8085010 Lumsden Dec 2011 B2
8120307 Lumsden Feb 2012 B2
8333265 Kang et al. Dec 2012 B2
8374729 Chapel et al. Feb 2013 B2
20010010032 Ehlers et al. Jul 2001 A1
20020079859 Lumsden Jun 2002 A1
20020109477 Ikezawa Aug 2002 A1
20030090362 Hardwick May 2003 A1
20030181288 Phillippe Sep 2003 A1
20040010350 Lof et al. Jan 2004 A1
20040047166 Lopez-Santillana et al. Mar 2004 A1
20040095237 Chen et al. May 2004 A1
20040153170 Santacatterina et al. Aug 2004 A1
20040181698 Williams Sep 2004 A1
20040189265 Rice et al. Sep 2004 A1
20040239335 McClelland et al. Dec 2004 A1
20050033951 Madter et al. Feb 2005 A1
20050068013 Scoggins Mar 2005 A1
20050073295 Hastings et al. Apr 2005 A1
20060038530 Holling Feb 2006 A1
20060049694 Kates Mar 2006 A1
20060103365 Ben-Yaacov May 2006 A1
20060103549 Hunt et al. May 2006 A1
20060125422 Costa Jun 2006 A1
20060175674 Taylor et al. Aug 2006 A1
20060276938 Miller Dec 2006 A1
20070024250 Simpson, III Feb 2007 A1
20070024264 Lestician Feb 2007 A1
20070037567 Ungless et al. Feb 2007 A1
20070069668 Mackay Mar 2007 A1
20070071047 Huang et al. Mar 2007 A1
20070211400 Weiher et al. Sep 2007 A1
20070213776 Brink Sep 2007 A1
20070244603 Level Oct 2007 A1
20070279053 Taylor et al. Dec 2007 A1
20070283175 Marinkovic et al. Dec 2007 A1
20070290645 Boyadjieff et al. Dec 2007 A1
20070300084 Goodrum et al. Dec 2007 A1
20070300085 Goodrum et al. Dec 2007 A1
20080005044 Benya et al. Jan 2008 A1
20080043506 Ozaki et al. Feb 2008 A1
20080049452 Van Bodegraven Feb 2008 A1
20080104430 Malone et al. May 2008 A1
20080116825 Descarries et al. May 2008 A1
20080121448 Betz et al. May 2008 A1
20080177678 Di Martini et al. Jul 2008 A1
20080221737 Josephson et al. Sep 2008 A1
20080272934 Wang et al. Nov 2008 A1
20080281473 Pitt Nov 2008 A1
20080290731 Cassidy Nov 2008 A1
20080291607 Braunstein et al. Nov 2008 A1
20090018706 Wittner Jan 2009 A1
20090045804 Durling et al. Feb 2009 A1
20090046490 Lumsden Feb 2009 A1
20090051344 Lumsden Feb 2009 A1
20090062970 Forbes, Jr. et al. Mar 2009 A1
20090063228 Forbes, Jr. Mar 2009 A1
20090083167 Subbloie Mar 2009 A1
20090085545 Shen et al. Apr 2009 A1
20090088907 Lewis et al. Apr 2009 A1
20090094173 Smith et al. Apr 2009 A1
20090105888 Flohr et al. Apr 2009 A1
20090154206 Fouquet et al. Jun 2009 A1
20090160267 Kates Jun 2009 A1
20090189581 Lawson et al. Jul 2009 A1
20090200981 Lumsden Aug 2009 A1
20100001704 Williams Jan 2010 A1
20100013427 Kelley Jan 2010 A1
20100014989 Tsuruta et al. Jan 2010 A1
20100033155 Lumsden Feb 2010 A1
20100054001 Dyer Mar 2010 A1
20100117588 Kelley May 2010 A9
20100138066 Kong Jun 2010 A1
20100145542 Chapel et al. Jun 2010 A1
20100148866 Lee et al. Jun 2010 A1
20100191385 Goodnow et al. Jul 2010 A1
20100228398 Powers et al. Sep 2010 A1
20100250590 Galvin Sep 2010 A1
20100277955 Duan Nov 2010 A1
20100283423 Boyadjieff Nov 2010 A1
20100305771 Rodgers Dec 2010 A1
20100320956 Lumsden et al. Dec 2010 A1
20110080130 Venkataraman Apr 2011 A1
20110121775 Garza May 2011 A1
20110182094 Lumsden Jul 2011 A1
20120086415 Lumsden Apr 2012 A1
20120213645 Lumsden et al. Aug 2012 A1
Foreign Referenced Citations (44)
Number Date Country
101207352 Jun 2008 CN
0330477 Aug 1989 EP
1650860 Aug 2008 EP
2183849 May 2010 EP
2183849 Aug 2013 EP
652558 Apr 1951 GB
1046446 Oct 1966 GB
1512407 Jun 1978 GB
2006-261594 Sep 1994 JP
6261594 Sep 1994 JP
2011-007328 Jan 1999 JP
2011-007328 Jan 1999 JP
2011-132155 May 1999 JP
11-241687 Sep 1999 JP
2011-241687 Sep 1999 JP
2000-125548 Apr 2000 JP
2001-245496 Sep 2001 JP
2001-245496 Sep 2001 JP
2002374691 Dec 2002 JP
2004-351492 Dec 2004 JP
2005-227795 Aug 2005 JP
2009535013 Sep 2009 JP
2010-502533 Jan 2010 JP
2010-502533 Jan 2010 JP
10-2001-0006838 Jan 2001 KR
10-2001-0006838 Jan 2001 KR
10-2009-0009872 Jan 2009 KR
10-2009-0009872 Jan 2009 KR
298359 Feb 2009 MX
303414 May 2010 MX
WO-8002895 Dec 1980 WO
WO-9103093 Mar 1991 WO
WO-9216041 Sep 1992 WO
WO 0066892 Nov 2000 WO
WO-00-66892 Nov 2000 WO
WO 2006021079 Mar 2006 WO
WO 2008008745 Jan 2008 WO
WO-2008-051386 May 2008 WO
WO-2008-150458 Dec 2008 WO
WO 2010114916 Oct 2010 WO
WO2011031603 Mar 2011 WO
WO 2012030403 Mar 2012 WO
WO 2012044289 Apr 2012 WO
WO 2012050635 Apr 2012 WO
Non-Patent Literature Citations (99)
Entry
PCT Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authority, or the Declaration, from the International Searching Authority Korea (ISA/KR) Korean Intellectual Property Office mailed Sep. 7, 2011; corresponding to U.S. Appl. No. 12/967,128, now Publication No. US2011/0080130 A1 (our file No. 133) (9 pages).
Extended European Search Report, European Patent Office, for Application No. 08795029.1-1242/2183849 PCT/US2008009393 dated Aug. 1, 2011; corresponding U.S. Appl. No. 12/185,442, now Publication No. US2009/0046490 A1 (our file No. 113) (10 pages).
PCT Notification of Transmittal of The International Search Report and the Written Opinion of the International Searching Authority, or the Declaration, from the International Searching Authority Korea (ISA/KR) Korean Intellectual Property Office mailed Jun. 29, 2011 corresponding to U.S. Appl. No. 12/893,539 (not yet published) (our file No. 127) (8 pages).
English language translation of Japanese Patent JP-11-007328 A above (13 pages).
English language translation of Japanese Patent JP 11241687 above (16 pages).
English language translation of Japanese Patent JP 2001-245496 above (14 pages).
English language translation of Japanese Patent JP 2010-502533 A above (16 pages).
PCT Notification of Transmittal of The International Search Report and the Written Opinion of the International Searching Authority, or the Declaration, from the International Searching Authority USA (ISA/US) mailed Oct. 6, 2008; corresponding to U.S. Appl. No. 12/185,442, now Publication No. US2009/0046490 A1 (our file No. 113) (15 pages).
Frick, Vincent, Member, IEEE; Hebrard, Luc, Member, IEEE; Poure, Phillippe; Anstotz, Freddy; Braun, Francis; “CMOS Microsystem for AC Current Measurement with Galvanic Isolation”; IEEE Sensors Journal, vol. 3, No. 6, Dec. 2003; (our file 113).
PCT Notification Concerning Transmittal of International Preliminary Report on Patentability mailed Feb. 20, 2010 from The International Bureau of WIPO; corresponding to U.S. Appl. No. 12/185,442, now Publication No. US2009/0046490 A1 (our file No. 113) (14 pages).
PCT Notification of Transmittal of The International Search Report and the Written Opinion of the International Searching Authority, or the Declaration, from the International Searching Authority USA (ISA/US) mailed Nov. 6, 2008; corresponding to U.S. Appl. No. 12/187,136, now Publication No. US2009/0051344 A1 (our file No. 114) (15 pages).
PCT Notification of Transmittal of The International Search Report and the Written Opinion of the International Searching Authority, or the Declaration, from the International Searching Authority USA (ISA/US) mailed Nov. 18, 2008; corresponding to U.S. Appl. No. 12/187,186, now Publication No. US2009/0200981 A1 (our file No. 115) (9 pages).
PCT Notification of Transmittal of The International Search Report and the Written Opinion of the International Searching Authority, or the Declaration, from the International Searching Authority USA (ISA/US) mailed Oct. 6, 2008; corresponding to U.S. Appl. No. 12/187,805, now Publication No. US2010/0033155 A1 (our file No. 116) (7 pages).
PCT Notification Concerning Transmittal of International Preliminary Report on Patentability mailed Feb. 17, 2011 from The International Bureau of WIPO; International Application No. PCT/US2008/009533 corresponding to U.S. Appl. No. 12/187,805, now Publication No. US2010/0033155 A1 (our file No. 116) (6 pages).
PCT Notification of Transmittal of The International Search Report and the Written Opinion of the International Searching Authority, or the Declaration, from the International Searching Authority USA (ISA/US) mailed Nov. 25, 2008; corresponding to International Application No. PCT/US 08/10720 and U.S. Appl. No. 12/207,913, now Publication No. US2010/0013427 A1 (our file No. 117) (8 pages).
PCT Notification Concerning Transmittal of International Preliminary Report on Patentability mailed Mar. 25, 2010 from the International Bureau of WIPO; corresponding to International Application No. PCT/US2008/1010720 and U.S. Appl. No. 12/207,913, now Publication No. US2010/0013427 A1 (our file No. 117) (7 pages).
English language translation of Official Action from the Eurasian Patent Office pertaining to Application No. 201070369/(OFE/1004/0111) and original Office Action both corresponding to PCT Application No. US 2008/010720 dated Apr. 26, 2011 and U.S. Appl. No. 12/207,913, now Publication No. US2010/0013427 A1 (our file No. 117) (2 pages).
PCT Notification of Transmittal of The International Search Report and the Written Opinion of the International Searching Authority, or the Declaration, from the International Searching Authority USA (ISA/US), mailed Oct. 15, 2010; corresponding to U.S. Appl. No. 12/873,510, now Publication No. US2010/0320956 A1 (our file No. 123) (11 pages).
International Search Report for International Application No. PCT/US2008/009393, dated Oct. 6, 2008 (our matter 113) (3 pages).
Written Opinion of the International Searching Authority for International Application No. PCT/US2008/009393, dated Oct. 6, 2008 (our matter 113) (13 pages).
Kolomoitsev, K.V.; “Voltage Control with the Aid of a Booster [Three Phase Supply Lines]”; Promyshlennaya Energetika, n 7, 38-9, Jul. 1979 (Language: Russian); ISSN: 0033-1155; Country of Publication: USSR; Abstract: Describes techniques of voltage control, or voltage maintenance, at the terminals of consumers, in 127/220 or 220/380 V supply lines. This is achieved using voltage boosters, consisting of regulating autotransformers and voltage boosting transformers, whose secondary windings are connected into the a.c. line. Voltage regulation is achieved by changing the additional e.m.f. in the windings of a boosting transformer with the aid of regulating autotransformers. Two-sided regulation at the output of a three-phse 220/380 V regulator is obtained by connecting the primary winding of the boosting transformer to the middle output and to the moving contact of the compensating regulating autotransformer.
International Search Report for International Application No. PCT/US2008/009482, dated Nov. 6, 2008 (our matter 114) (2 pages).
Written Opinion of the International Search Authority for International Application No. PCT/US2008/009482, dated Nov. 6, 2008 (our matter 114) (11 pages).
International Search Report for International Application No. PCT/US2008/009483, dated Nov. 18, 2008 (our matter 115) (2 pages).
Written Opinion of the International Search Authority for International Application No. PCT/US2008/009483, dated Nov. 18, 2008 (our matter 115) (6 pages).
International Search Report for International Application No. PCT/US2008/009533, dated Oct. 6, 2008 (our matter 116) (2 pages).
Written Opinion of the International Search Authority for International Application No. PCT/US2008/009533, dated Oct. 6, 2008 (our matter 116) (5 pages).
International Search Report for International Application No. PCT/US2008/010720, dated Nov. 25, 2008 (our matter 117) (2 pages).
Written Opinion of the International Search Authority for International Application No. PCT/US2008/010720, dated Nov. 25, 2008 (our matter 117) (4 pages).
First Non-Final Office Action mailed Feb. 3, 2011, U.S. Appl. No. 12/187,186, filed Aug. 6, 2008, (19 pages) (our matter 115).
Response and Amendment to First Non-Final Office Action mailed Apr. 8, 2011, U.S. Appl. No. 12/187,186, filed Aug. 6, 2008, (32 pages) (our matter 115).
Final Office Action mailed Jun. 13, 2011, U.S. Appl. No. 12/187,186, filed Aug. 6, 2008, (23 pages) (our matter 115).
PCT Notification of Transmittal of The International Search Report and the Written Opinion of the International Searching Authority, or the Declaration, from the International Searching Authority USA (ISA/US) mailed Jan. 2, 2012; corresponding to U.S. Appl. No. 13/026,931, now Publication No. US2011/0182094 A1 (our file No. 128) (9 pages).
Notification of the First Office Action dated Dec. 23, 2011, State Intellectual Property Office of People's Republic of China; Chinese National Phase of PCT Application No. 200880111387.0, with English translation (our matter 113) (19 pages).
Substantive Examination Report Stage I, Indonesian National Phase of PCT Application No. W-00201000702 with English translation (our matter 113) (3 pages).
Response to extended European Search Report of Aug. 1, 2011 (NPL B above) and Response to Communication pursuant to Rules 70(2) and 70A(2) EPC of Aug. 18, 2011, dated Feb. 24, 2012, European Patent Application No. 08795029.1 (our matter 113) (12 pages).
Office Action from Mexican Patent Office dated Oct. 20, 2011 for Mexican National Phase of PCT Application No. MX/a/2010/001755 (our matter 113) (2 pages).
Response dated Mar. 9, 2012 conforming Mexican claims to corresponding US Patent No. 8,085,009 B2 (our matter 113) (50 pages).
Notice of Allowance from Mexican Patent Office dated Mar. 15, 2012 resulting from Response above(our matter 113) (1 page).
Office Action from Eurasian Patent Office dated Feb. 21, 2011 signed by Official Patent for Application No. 201070276/31 filed Mar. 12, 2010 with English translation (our matter 113) (2 pages).
Response dated May 10, 2011 (our matter 113) (17 pages).
Notice of Allowance from Eurasian Patent Office dated Sep. 13, 2011 for Application No. 201070276/31 filed Mar. 12, 2010 with English translation as a result above (our matter 113) (2 pages).
Response dated Jan. 13, 2012 adding new claims of U.S. Appl. No. 13/331,757 (our matters 113 and 139) (16 pages).
Response and Amendment to Aug. 3, 2011 Non-Final Office Action filed Oct. 31, 2011, U.S. Appl. No. 12/207,913 (our matter 117) (23 pages).
Response to Mexican Office Action dated Feb. 6, 2012 for Application No. MX/a/2010/002859, distinguishing US 6,274,999 B1 to Fuji, et al. and US 5,828,200 to Ligman, et al. while conforming the Mexican claims to corresponding U.S. Appl. No. 12/207,913 (our matter 117MX) (21 pages).
Notice of Allowance from Mexican Patent Office dated Apr. 24, 2012 for Application No. MX/a/2010/002859 filed Sep. 15, 2008 (our matter 117MX) (2 pages).
Office Action from Mexican Patent Office dated Nov. 25, 2011 for Application No. MX/a/2010/002859 filed Sep. 15, 2008 (our matter 117MX) (2 pages).
Notification of the necessity to submit additional materials and arguing some claims lack of novelty in view of US 5,828,200 to Ligman et al. (Abstract, col. 3, lns. 1-65, and claims and description relating to Figs. 1 and 3B) and US 6,449,567 to Desai from Eurasian Patent Office dated Apr. 26, 2011 for Application No. 201070369/(OFE/1004/0111) filed Apr. 13, 2010 with English translation (our matter 117EA) (2 pages).
Notification of Eurasian Patent Office Readiness to Grant Patent dated Dec. 15, 2011 for Application No. 201070369/ (OFE/1004/0111) filed Apr. 13, 2010 with English translation (our matter 117EA) (2 pages).
Response dated Apr. 3, 2012 for Eurasian Application No. 201070369 (our matter 117EA) (16 pages).
Response dated Mar. 5, 2012 for Application No. W-00201000893 with English translation distinguishing US 5,828,200 to Ligman and US 6,449,567 to Desai (our matter 117ID) (15 pages).
Final Office Action in U.S. Appl. No. 12/207,913 mailed from the USPTO on Mar. 14, 2012 relying on US 6,274,999 to Fuji and US 6,489,742 to Lumsden (our matter 117) (17 pages).
Extended European Search Report from the European Patent Office in Application No. 08830045.4 dated Aug. 22, 2012 (our matter 117EP) (8 pages).
Notice of Reasons for Refusal of Patent Application No. 2010-524881 mailed from the Japanese Patent Office on Aug. 28, 2012 relying on Japanese Unexamined Patent Publication HEI6-261594 with English translation (our matter 117JP) (6 pages).
Response to final Office Action for U.S. Appl. No. 12/207,913, filed Sep. 13, 2012 (our matter 117) (32 pages).
Sul, S K and Park, M H: “A novel Technique for Optimal Efficiency Control of a Current-Source Inverter-Fed Induction Motor”, IEEE Transactions on Power Electronics, vol. 3, No. 2, Apr. 1, 1988, pp. 192-199, XP002063874, ISSN: 0885-8993, DOI: 10.1109/63.4349, p. 2, left-hand column, line 9-p. 4, left-hand column, line 29; Figs. 4-8 (8 pages); retrieved from IEEE databank attached, considered to be particularly relevant if taken alone, (our matter 117EP) (8 pages).
Flemming Abrahamsen, et al.: “On the Energy Optimized Control of Standard and High-Efficiency Induction Motors in CT and HVAC Applications”, IEEE Transactions on Industry Applications, IEEE Service Center, Piscataway, NJ, US, vol. 34, No. 4, Aug. 1, 1998, XP011022398, ISSN: 0093-9994, p. 4, right-hand column, line 11-p. 5, left-hand column, line 5; Fig. 9 (10 pages); ); retrieved from IEEE databank attached, considered to be particularly relevant if taken alone, (our matter 117EP) (10 pages).
Office Action issued by the State Intellectual Property Office (SIPO) on Apr. 28, 2012 for Chinese Application No. 200880115946 (PCT/US2008/010720) relying on US 6,274,999 B1 to Fuji, with English translation (our matter 117CN) (21 pages).
Office Action from Eurasian Patent Office dated Aug. 16, 2012 for Application No. 201070369/31 with English translation (our matter 117EA) (4 pages).
European Patent Office grant of patent dated Jun. 4, 2012, European Patent Application No. 08795029.1-1242 (our matter 113EP) (61 pages).
Response to requesting deletion of text added to claims 1 and 10 by Examiner dated Sep. 19, 2012, European Patent Application No. 08795029.1-1242 (our matter 113EP) (2 pages).
Office Action from the Eurasian Patent Office dated May 28, 2012, Eurasian Patent Application No. 201070276/31 (our matter 113EA) (English translation, 2 pages).
Response including reference numbers for 96 claims as filed in U.S. Appl. No. 13/331,757 on or between Sep. 20-27, 2012 (our matter 139EA) (12 pages).
Response dated Jul. 9, 2012 amending claims to claims 1-77 of US Patent No. 8,085,009 (our matter 113CN) (24 pages).
International Search Report and Written Opinion for International Application No. PCT/US2012/035844 dated Nov. 16, 2012 corresponding to US2012/0213645 Al (our matter 135) (8 pages).
Patent Cooperation Treaty Notification Concerning Transmittal of International Preliminary Report on Patentability (Chapter I of the Patent Cooperation Treaty) (PCT Rule 44bis.1(c) mailed Mar. 14, 2013 for PCT Application corresponding to International Application No. PCT/US2011/020326, filed on Jan. 6, 2011, and published as WO 2012/030403 on Mar. 2, 2012, corresponding to U.S. Appl. No. 12/967,128 published as US-2011/0080130 A1 (our matter 0133) (6 pages).
Office Action from the U.S. Patent and Trademark Office mailed Feb. 22, 2013 corresponding to U.S. Appl. No. 12/207,913, republished as US-2010/0117588 A1 (our matter 0117US) (48 pages).
Office Action from the State Intellectual Property Office mailed Mar. 29, 2013 for Chinese Application No. 200880115946.5 (our matter 0117CN) with English translation corresponding to U.S. Appl. No. 12/207,913, republished as US-2010/0117588 A1 (our matter 0117US) (19 pages).
Response to Office Action from the State Intellectual Property Office dated Mar. 29, 2013 for Chinese Application No. 200880115946.5 (our matter 0117CN) corresponding to U.S. Appl. No. 12/207,913, republished as US-2010/0117588 A1 (our matter 0117US) (13 pages).
Notice of Allowance form the U.S. Patent and Trademark Office mailed Jun. 11, 2013 for U.S. Appl. No. 13/451,041, published as US-2012/0213645 A1 (our matter 0135US) (49 pages).
Response to Office Action from the Colombian Patent Office dated Dec. 27, 2012 for Colombian Application No. 10.042.683 (our matter 0117CO) with English translation corresponding to U.S. Appl. No. 12/207,913, republished as US-20I0/0117588 A1 (our matter 0117US) (55 pages).
Response to Office Action from Eurasian Patent Office dated Dec. 17, 2012 for Application No. 201070369/31 (our matter 117EA) corresponding to U.S. Appl. No. 12/207,913, republished as US-2010/0117588 A1 (our matter 01I7US) (15 pages).
Notification of the necessity to Submit Additional Materials from the Eurasian Patent Office dated Apr. 1, 2013 for Application No. 201070369/31 (our matter 117EA) with English translation corresponding to U.S. Appl. No. 12/207,913, republished as US-2010/0117588 A1 (our matter 0117US) (4 pages).
Response to Supplementary European Search Report from the European Patent Office mailed on Aug. 22, 2012, filed on Mar. 18, 2013 regarding European Application No. 08830045.4 (our matter 117EP) corresponding to U.S. Appl. No. 12/207,913, republished as US-2010/0117588 A1 (our matter 0117US) (21 pages).
Notice of Reasons for Refusal of Patent Application No. 2010-524881 (our matter 117JP) mailed from the Japanese Patent Office on Aug. 28, 2012 with English translation, relying on Japanese Unexamined Patent Publication HEI6-261594; (6 pages).
Response to 2nd Office Action for Chinese Patent Application No. 200880111387.0 (our matter 0113CN) filed on Jan. 8, 2013 corresponding to U.S. Appl. No. 12/185,442, issued as US Patent No. 8085009B2 (our matter 0113US) (25 pages).
Voluntary Amendment filed on Mar. 21, 2013 for Chinese Patent Application No. 200880111387.0 (our matter 0113CN) filed on Jan. 8, 2013 corresponding to U.S. Appl. No. 12/185,442, issued as US Patent No. 8085009B2 (our matter 0113US) (22 pages).
Notification on Grant of Patent Right for Invention mailed on Apr. 9, 2013 for Chinese Patent Application No. 200880111387.0 (our matter 0113CN) filed on Jan. 8, 2013 with English translation corresponding to U.S. Appl. No. 12/185,442, issued as US Patent No. 8085009B2 (our matter 0113US) (4 pages).
Response to Office Action for Colombian Patent Application No. 10.029.658 (our matter 0113CO) filed on Feb. 20, 2013 corresponding to U.S. Appl. No. 12/185,442, issued as US Patent No. 8085009B2 (our matter 0113US) (42 pages).
Office Action from the U.S. Patent and Trademark Office mailed Mar. 13, 2013 corresponding to U.S. Appl. No. 12/873,510, published as US-2010/0320956 A1 on Dec. 23, 2010 (our matter 0123US), which is a continuation-in-part of U.S. Appl. No. 12/207,913, republished as US-2010/0117588 A1 (our matter 0117US) (15 pages).
International Search Report for International Application No. PCT/US2010/047477 (our matter 0123PCT) mailed Mar. 22, 2012 corresponding to U.S. Appl. No. 12/873,510, published as US-2010/0320956 A1 (our matter 0123US) (9 pages).
Voluntary Amendment filed on Nov. 9, 2012 for Chinese Patent Application No. 201080039849.X (our matter 0123CN) corresponding to U.S. Appl. No. 12/873,510, republished as US-2010/0320956 A1 (our matter 0123US) (8 pages).
Office Action from the U.S. Patent and Trademark Office mailed Feb. 26, 2013 corresponding to U.S. Appl. No. 12/893,539, published as US-2012/0075896 A1 (our matter 0127US) (7 pages).
International Search Report for International Application No. PCT/US2010/050714 (our matter 0127PCT) mailed Apr. 11, 2013 corresponding to U.S. Appl. No. 12/893,539, published as US-2012/0075896 A1 (our matter 0127US) (5 pages).
Office Action from the U.S. Patent and Trademark Office mailed Apr. 10, 2013 corresponding to U.S. Appl. No. 13/026,931 (our matter 0128US) (11 pages).
Notice of Allowance from the U.S. Patent and Trademark Office mailed Jun. 11, 2013 corresponding to U.S. Appl. No. 12/967,128 (our matter 0133US) (11 pages).
Office Action from the U.S. Patent and Trademark Office mailed Aug. 17, 2012 corresponding to U.S. Appl. No. 13/331,757 (our matter 0139US) (14 pages).
Response to Office Action from the U.S. Patent and Trademark Office mailed Aug. 17, 2012, filed Nov. 15, 2012 corresponding to U.S. Appl. No. 13/331,757 (our matter 0139) (26 pages).
Final Office Action from the U.S. Patent and Trademark Office mailed Feb. 27, 2013 corresponding to U.S. Appl. No. 13/331,757 (our matter 0139) (45 pages).
Response to Office Action from the Eurasian Patent Office filed on Apr. 19, 2013 corresponding to U.S. Appl. No. 13/331,757 (our matter 0139) (13 pages).
Sul, S K and Park, M H: “A novel Technique for Optimal Efficiency Control of a Current-Source Inverter-Fed Induction Motor”, IEEE Transactions on Power Electronics, vol. 3, No. 2, Apr. 1, 1988, pp. 192-199, XP002063874, ISSN: 0885-8993, DOI: 10.1109/63.4349, p. 2, left-hand column, line 9-p. 4, left-hand column, line 29; Figs. 4-8 (8 pages); retrieved from IEEE databank attached, considered to be particularly relevant if taken alone, (our matter 117EP) (16 pages).
Flemming Abrahamsen, et al.: “On the Energy Optimized Control of Standard and High-Efficiency Induction Motors in CT and HVAC Applications”, IEEE Transactions on Industry Applications, IEEE Service Center, Piscataway, NJ, US, vol. 34, No. 4, Jul./Aug. 1998, XP011022398, ISSN: 0093-9994, p. 4, right-hand column, line 11-p. 5, left-hand column, line 5; Fig. 9 (10 pages); ); retrieved from IEEE databank attached, considered to be particularly relevant if taken alone, (our matter 117EP) (20 pages).
International Search Report for International Application No. PCT/US2011/032840 (our matter 0128PCT), mailed Apr. 11, 2013 corresponding to U.S. Appl. No. 13/026,931 (our matter 0128US), published as US 2011-0182094 A1 (6 pages).
Industry and Commerce Superintendency, Republic of Colombia, Resolution No. 71361, denying the Colombian patent application corresponding to US2010/0117588 (U.S. Appl. No. 12/207,913) (our matter 117), dated Nov. 26, 2012, executed by Pablo Felipe Robledo Del Castillo (6 pages), with English translation (6 pages) (Total 12 pages).
Response to Office Action for Chinese Application No. 200880115946.5 filed on Aug. 13, 2013 with English translation of claims 1-41- corresponding to U.S. Appl. No. 12/207,913, republished as US-2010/0117588 A1 (20 pages).
Notification of Third Action for Chinese Application No. 200880115946.5 issued on Oct. 10, 2013 with English translation of Office Action—corresponding to U.S. Appl. No. 12/207,913, republished as US-2010/0117588 A1(17 pages).
Notification of Office Action for Japanese Patent Application No. 2010-520985 mailed on Jun. 25, 2013 with English translation—corresponding to U.S. Appl. No. 12/185,442, now Publication No. US2009/0046490 A1 (4 pages).
Notice of Reasons for Refusal of Japanese Patent Application No. 2010-524881 mailed on Sep. 10, 2013—corresponding to U.S. Appl. No. 12/207,913, republished as US-2010/0117588 A1 (6 pages).
Office Action No. 13454 for Colombian Patent Application No. 12.052.906 mailed on Jul. 23, 2013 with English translation—corresponding to U.S. Appl. No. 12/873,510, republished as US-2010/0320956 A1 (14 pages).
Related Publications (1)
Number Date Country
20120086415 A1 Apr 2012 US
Provisional Applications (6)
Number Date Country
60964587 Aug 2007 US
60966124 Aug 2007 US
61009844 Jan 2008 US
61009846 Jan 2008 US
61009845 Jan 2008 US
61009806 Jan 2008 US
Continuations (1)
Number Date Country
Parent 12185442 Aug 2008 US
Child 13331757 US