This application claims the priority of Korean Patent Application No. 2003-72499, filed on Oct. 17, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a III-V group GaN-based semiconductor device and a method of manufacturing the same, and more particularly, to a III-V group GaN-based semiconductor device and a method of manufacturing the same, which can protect an active layer from thermal shock during formation of a p-type semiconductor layer.
2. Description of the Related Art
During the manufacturing of a III-V group GaN-based semiconductor device, after an active layer is grown, a reaction temperature must be raised to a high temperature of about 1050° C. before the growth of a p-type compound semiconductor layer.
Applying the high temperature to an exposed top surface of the active layer damages the active layer, thus deteriorating interfacial characteristics between the active layer and the p-type compound semiconductor layer.
Techniques of preventing the damage to the active layer and the deterioration of the interfacial characteristics are necessary. For this purpose, U.S. patent application No. 20020053676 AA discloses a semiconductor device in which an InGaN protection layer having a thickness of about 200 to 500 Å is formed directly on a grown active layer to protect the active layer, a reaction temperature is raised to a high temperature of about 1100° C., and then a p-type semiconductor layer is formed.
The InGaN protection layer is formed to protect the active layer from a high-temperature atmosphere, but cannot sufficiently suppress damage to the active layer. Rather, the InGaN protection layer leads to the formation of a gradually degraded layer, which deteriorates the operating performance of the semiconductor device.
Japanese Patent Laid-open Publication No. 9-36429 proposes another method for preventing deterioration of an active layer due to a high temperature. In this case, after the active layer is grown, a low-temperature AlGaN protection layer is grown to a thickness of about 10 to 50 Å.
However, in this method, the AlGaN protection layer itself is not resistant to the high temperature enough to protect the active layer.
The present invention provides a III-V group GaN-based semiconductor device and a method of manufacturing the same, which can prevent deterioration of an active layer due to a rise in temperature.
According to an aspect of the present invention, there is provided a III-V group GaN-based semiconductor device including an n-type GaN-based compound semiconductor layer; an active layer comprising alternately stacked quantum wells and barrier layers disposed on the n-type GaN-based compound semiconductor layer; an Al GaN diffusion blocking layer disposed on the active layer; an InGaN sacrificial layer formed on the Al GaN diffusion blocking layer; and a p-type GaN-based compound semiconductor layer disposed on the InGaN sacrificial layer.
According to another aspect of the present invention, there is provided a method of manufacturing a III-V group GaN-based semiconductor device. The method includes growing an n-type GaN-based compound semiconductor layer on a substrate; growing an active layer having a multiple quantum well on the n-type GaN-based compound semiconductor layer; growing an AlxGaN diffusion blocking layer on the active layer; growing an InGaN sacrificial layer on the diffusion blocking layer; and growing a p-type GaN-based compound semiconductor layer on the InGaN sacrificial layer.
The growing of the diffusion blocking layer and the growing of the sacrificial layer may be performed immediately after the growing of the active layer at the same temperature as the temperature at which the active layer is grown.
After the sacrificial layer is grown, a reaction temperature may be raised to a temperature appropriate for growing the p-type GaN-based compound semiconductor layer.
The sacrificial layer may be formed to a thickness of about 20 to 200 Å, preferably 50 Å. Also, the sacrificial layer may be formed of 10% or less, preferably 1% or less, by weight of In.
The diffusion blocking layer may be formed with a different thickness, depending on its Al composition. For more than 10% Al composition, up to 50%, the layer thickness may be formed of 5˜100 Å, preferably 20 Å. For less than 10% Al composition of diffusion blocking layer, the thickness of diffusion blocking layer should be increased, up to 500 Å for 1% Al composition. Preferably, 300 Å thickness of diffusion blocking layer is formed at 4% Al.
The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:
The present invention will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown.
Referring to
A cap layer 16 is interposed between the active layer 15 and the p-type compound semiconductor stack. The cap layer 16 includes a single InGaN sacrificial layer 16a disposed on a single AlGaN diffusion blocking layer 16b. Alternatively, the cap layer 16 may be formed by sequentially stacking 20 or less combinations of the diffusion blocking layer 16b stacked on the sacrificial layer 16a and 20.
The diffusion blocking layer 16b prevents diffusion of indium from the active layer 15, and the sacrificial layer 16a protects the diffusion blocking layer 16b. When manufacturing the LD, the sacrificial layer 16a protects the diffusion blocking layer 16b from heat applied during the formation of the p-type semiconductor layer. As a result, the sacrificial layer 16a is partially removed with a small amount of the sacrificial layer 16a remaining on the diffusion blocking layer 16b. The diffusion blocking layer 16a is grown to a thickness of about 5 to 100 Å, preferably 20 Å. For less than 10% Al compostion of diffusion blocking layer, the thickness of diffusion blocking layer should be increased, up to 500 Å for 1% Al composition. Preferably, 300 Å thickness of diffusion blocking layer is formed at 4% Al. The sacrificial layer 16a is grown to a thickness of about 20 to 200 Å, preferably 50 Å, since approximately 30 to 70 Å of the sacrificial layer 16a is desorbed depending on growth conditions during a rise in the temperature.
Hereinafter, the structure of the LD will be described in detail with reference to
The n-GaN lower contact layer 12 is stacked on the sapphire substrate 11. A multiple semiconductor layer is disposed on the lower contact layer 12 to form a mesa structure. That is, an n-GaN/AlGaN lower clad layer 13, an n-GaN lower waveguide layer 14, the InGaN active layer 15, the cap layer 16, a p-GaN upper waveguide layer 17, and a p-GaN/AlGaN upper clad layer 18 are sequentially stacked on a top surface of the n-GaN lower contact layer 12. The n-GaN/AlGaN lower clad layer 13 and the p-GaN/AlGaN upper clad layer 18 have lower refractive indexes than the n-GaN lower waveguide layer 14 and the p-GaN upper waveguide layer 17, respectively, and the n-GaN lower waveguide layer 14 and the p-GaN upper waveguide layer 17 have lower refractive indexes than the active layer 15. In the mesa structure, a protruding ridge 18a having a predetermined width is formed in the center of a top surface of the p-GaN/AlGaN upper clad layer 18 to provide a ridge wave guide structure, and a p-GaN upper contact layer 19 is formed on top of the ridge 18a. A buried layer 20 having a contact hole 20a, which acts as a passivation layer, is disposed on the p-GaN/AlGaN upper clad layer 18. The contact hole 20a of the buried layer 20 corresponds to a top portion of the upper contact layer 19 formed on the ridge 18a, and an outer portion of the contact hole 20a overlaps an outer portion of the upper contact layer 19.
The p-type compound semiconductor layer disposed on the active layer 16 may further include an electron blocking layer (EBL), which prevents flow of electrons from the active layer 15 into the p-type compound semiconductor layer, and a phase matching layer. Since the EBL and the phase matching layer are general elements that do not limit the technical spirit of the present invention, they are not shown in
A p-type electrode 21, which is a multiple layer including a Zn-based stack layer, is formed on the buried layer 20. The p-type electrode 21 contacts the upper contact layer 19 via the contact hole 19a of the buried layer 20. An n-type electrode 22 is formed on a stepped portion disposed on one side of the lower contact layer 12. The ridge wave guide structure disposed on the upper clad layer 17 limits a current flowing to the active layer 15. Thus, the width of a resonance region is limited, thereby stabilizing a transverse mode and reducing an operating current.
To manufacture a conventional Nitride-based semiconductor laser device, a multiple GaN-based semiconductor layer is formed on a sapphire substrate, a ridge where a current is supplied is formed by dry etching, and a mesa structure is formed on an n-GaN lower contact layer to expose the n-GaN lower contact layer and form a resonance surface.
On the other hand, in the present invention, after the active layer 15 is grown with a multiple quantum well (MQW), the cap layer 16 is formed by sequentially stacking the AlGaN diffusion blocking layer 16b and the InGaN sacrificial layer 16a on the active layer 15 without varying a reaction temperature, the reaction temperature is then raised to a high temperature of, for example, 1050° C., and then the p-type semiconductor stack layer is grown on the InGaN sacrificial layer 16a. The n-type compound semiconductor stack layer disposed under the active layer 15 can be grown at a temperature of about 1050° C., and the active layer 15 is grown after the reaction temperature is lowered to 780° C.
In the present invention, deterioration of an InGaN/GaN active layer during high-temperature growth of the p-type GaN-based compound semiconductor stack layer is effectively prevented. Thus, an operating current is maintained at an appropriate level, and lifetime of the LD can be extended.
In a method of manufacturing an LD according to the present invention, after the active layer 15 is formed, the diffusion blocking layer 16b and the sacrificial layer 16a are sequentially grown at a temperature between 770˜900° C., for example at the same temperature as the temperature at which the active layer 15 is grown, for example, at 780° C. The diffusion blocking layer 16b is formed of AlxGa1−xN [0.01≦x≦0.5] or AlxInyGa1−x−yN [0.01≦x≦0.5, 0.01≦y≦0.1], and the sacrificial layer 16a is formed of InxG1−xN [0≦x≦0.1]. Thereafter, a reaction temperature is raised to a high temperature of, for example, 1050° C., and the p-type compound semiconductor stack layer is grown using AlxInyGazN [0≦x≦1, 0≦y≦1, 0≦z≦1, and x+y+z=1]. As stated above, the diffusion blocking layer 16b is grown to a thickness of about 5 to 500 Å, preferably 20 Å or less. The sacrificial layer 16a is grown to a thickness of about 20 to 200 Å, preferably 50 Å, since approximately 30 to 70 Å of the sacrificial layer 16a is desorbed depending on growth conditions when raising the temperature.
In the present invention, the diffusion blocking layer 16b stably prevents diffusion of indium from the active layer 15, having both wells and barriers, at the high temperature. The sacrificial layer 16a, which is formed of InxG1−xN [0≦x≦0.1], is sacrificially damaged to prevent deterioration of the diffusion blocking layer 16b disposed thereunder. Thus, crystallinity of the diffusion blocking layer 16b can be stabilized.
Also, to determine if the groove type defects were generated due to poor crystallinity of the protection layer, the AFM images were observed by varying the growth rates as shown in
Thus, in the present invention, not only is the deterioration of an InGaN active layer prevented, but also the generation of groove type defects that preclude techniques of growing AlGaN diffusion blocking layers from being used. In addition, as shown in the TEM image of
Referring to
Referring to
By extrapolating the results shown in
As described above, a III-V group GaN-based semiconductor device of the present invention includes an AlGaN diffusion blocking layer, which can be grown at a low temperature, and an InGaN sacrificial layer, which protects the diffusion blocking layer, interposed between an active layer grown at a low temperature and an p-type compound semiconductor stack layer grown at a high temperature. Thus, the semiconductor device can have a high-quality crystalline growth structure having good interfacial characteristics between the active layer and the p-type compound semiconductor layer.
While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.
Number | Date | Country | Kind |
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10-2003-0072499 | Oct 2003 | KR | national |