Patent Application
20090016627
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2007-180181 filed on Jul. 9, 2007; the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to an image compressor, an image expander and an image processing apparatus and, more particularly, to an image compressor, an image expander and an image processing apparatus capable of controlling the amount of code by mixing reversible compression and irreversible compression on a pixel-by-pixel basis without requiring transmission of reversibility/irreversibility information (e.g. quantization scales).
2. Description of the Related Art
Conventionally, differential pulse code modulation (DPCM) in which the difference between an input value and a predicted value (referred to as a predicted difference) is encoded is used as a method of reversible coding (referred to as lossless compression or reversible compression) or irreversible coding (referred to as lossy compression or irreversible compression).
In the case of reversible compression, the amount of code varies largely image by image. In a system requiring code amount limitation, therefore, the amount of code is controlled by changing the numerical loss level (reversibility and irreversibility) with respect to a plurality of pixel regions (see, for example, Japanese Patent Publication No. 3749752).
Because of changing the numerical loss level (reversibility and irreversibility) with respect to unit regions formed of a plurality of pixels, the art disclosed in Japanese Patent Publication No. 3749752 entails the drawback of reducing the compression rate and consuming a large amount of code with respect to a large change in luminance in a portion of a small-luminance-change region (for which a compression setting is made by selecting high-restoration low-compression-rate reversible compression because of a small predicted error) due to a coding setting close to reversible compression while allowing restoration loss and deterioration in visual quality with respect to a small change in luminance in a portion of a large-luminance-change region (for which a compression setting is made by selecting high-compression-rate irreversible compression because of a large predicted error) due to a irreversible coding setting. Moreover, coding of loss level information is also required with respect to each region and a reduction in coding efficiency therefore occurs.
According to one aspect of the present invention, there is provided an image compressor including a predicted pixel value generation unit configured to generate a predicted pixel value by referring to a past input pixel, an error level detection unit configured to detect the magnitude of the difference between the predicted pixel value and an input pixel value, a target code amount difference level detection unit configured to detect a target code amount difference level indicating the magnitude of an excess by which a generated code amount for the number of encoded pixels exceeds a target code amount corresponding to the number of pixels, an input pixel value correction unit configured to correct less significant bit data in the input pixel value according to the target code amount difference level so that the less significant bit data becomes the same as less significant bit data in the predicted pixel value when the error level is equal to or higher than a predetermined value, a predicted error computation unit configured to compute a predicted error which is the difference between a pixel value output from the input pixel value correction unit and the predicted pixel value, a predicted error coding unit configured to encode, by variable-length coding, group information indicating a group to which the magnitude of the predicted error belongs and added bit data indicating a particular predicted error value in the group, and to perform encoding by removing less significant data in the added bit data for the predicted error from an object to be encoded according to the target code amount difference level if the magnitude of the predicted error is equal to or larger than a predetermined value, and a packing unit configured to output the variable-length-coded data in a predetermined code amount unit.
According to another aspect of the present invention, there is provided an image expander including an encoded data taking-in unit configured to take in variable-length-encoded data encoded with group information indicating a group to which the magnitude of a predicted code belongs and added bit data indicating the value of the predicted error, lower significant bit data in the added bit data being removed from an object to be encoded according to the level of a difference between a target code amount and a generated code amount at the time of encoding, a target code amount difference level detection unit configured to detect a target code amount difference level indicating the magnitude of an excess by which a code amount consumed for a certain number of decoded pixels exceeds a target code amount corresponding to the number of pixels, a predicted error decoding unit configured to decode, from variable-length-encoded data output from the encoded data taking-in unit, group information indicating a group to which the magnitude of a predicted error belongs and added bit data indicating a particular predicted error value in the group, thereby reproduce the predicted error, and perform reproduction by setting less significant bit data in the added bit data for the reproduced predicted error to 0 according to the target code amount difference level when the magnitude of the predicted error is equal to or larger than a predetermined value, a predicted pixel value generation unit configured to generate a predicted pixel value by referring to a decoded pixel, and a pixel value reproduction unit configured to reproduce a pixel value by adding the reproduced predicted error to the predicted pixel value.
According to another aspect of the present invention, there is provided an image processing apparatus including an image compression processing unit having the image compressor, an image expansion processing unit having the image expander, an external memory, and an image processing unit configured to temporarily store results of intermediate processing on input image data in the external memory via the image compression processing unit, and read out a plurality of intermediate processing results stored in the external memory via the image expansion processing unit to output final results of image processing.
Embodiments of the present invention will be described with reference to the accompanying drawings.
The image compressor 10 shown in
According to the first embodiment configured as described above, an image compressor capable of controlling the amount of code by mixing reversible compression and irreversible compression on a pixel-by-pixel basis without requiring transmission of reversibility/irreversibility information can be implemented in such a manner that, in an image compressor which encodes a predicted error, an input pixel value is modified (corrected) according to a target code amount difference level when the predicted error becomes equal to or larger than a predetermined value.
In an image compressor 10A shown in
The reason for setting only less significant bit data as an object to be corrected or an object to be excluded from encoding will now be described below. More significant bits are important data, such that if an error occurs therein, the error is visually recognized as a larger error. Therefore an object to be corrected or an object to be excluded from encoding is limited within an error range in correspondence with less significant bits. The error is visually recognized easily in a small-luminance-change region. Therefore, if the magnitude of a predicted error is smaller than a predetermined value, the input pixel data is directly used without being corrected. If the magnitude of the predicted error is equal to or larger than the predetermined value, less significant bit data in the input pixel data is corrected according to the target code amount difference level so as to become the same as the predicted pixel value. That is, if the predicted error is equal to or larger than the predetermined value, the least significant bit data (the data formed of the least significant one bit) is corrected so as to become the same as the least significant bit data in the predicted pixel value. With increase in target code amount difference level, the data at the second bit position from the least significant bit and the data at the third bit position from the least significant bit are also corrected so as to become the same as the data at the corresponding bit positions in the predicted pixel value. The less significant bit data in the predicted error in the predicted error computation unit 14 can be set to zero by input pixel data correction made as described above. Encoding is performed while removing, from the object to be encoded in a predicted error coding unit 15, at the time of encoding, the less significant bit data portion of the predicted error set to zero by correcting the input pixel data as described above. That is, the data is encoded in a state where the less significant bit data zero portion of the predicted error is deleted without being encoded (in other words, the least-significant-side bit(s) in the less significant bit data is not encoded, while the other more significant bits are encoded). The encoded data is sent to the decoding side.
In a case where only one past pixel output from a DFF 12-1 which performs one-clock-cycle delay in a stage in front of the predicted pixel value generation unit 12 is referred to, the illustrated predicted pixel value generation unit 12 may be formed only of a signal line to pass the data therethrough without delaying the data. That is, the predicted pixel value generation unit 12 may be only a signal line and a signal one-clock-cycle-delayed by the DFF 12-1 (one-pixel-preceding signal) may be provided as a predicted pixel value. The arrangement may alternatively be such that, as shown in
The error level detection unit 13 has an adder 131 which takes the difference between the input pixel value from the DFF 111 and the predicted pixel value from the predicted pixel value generation unit 12, and a level detection section 132 configured to output an error level representing whether the magnitude of the difference is equal to or larger than a predetermined value.
A predicted error computation unit 14 has a DFF 141 which delays the predicted pixel data output from the predicted pixel value generation unit 12 by one clock cycle, and an adder 142 which computes the predicted error which is the difference between the input pixel value after correction processing obtained by the DFF 12-1 delaying the output from the input pixel value correction unit 111 by one clock cycle and the predicted pixel value one-clock-cycle-delayed by the DFF 141.
Table 1 shows group information (group Nos.) which is classification information indicating the magnitudes of predicted errors. Table 2 shows the relationship between added bit data corresponding to the group information indicating the magnitudes of the predicted errors and binary expressions (expressions of 2's complements) of the predicted errors. Table 3 shows an example of variable length codes in the group information indicating the magnitudes of the predicted errors and the numbers of added bits (before reducing the number of added bits). Table 4 shows an example of reductions in the numbers of added bits for the predicted error (on the less significant side).
The predicted error coding unit 15 has a bit length detection section 151 configured to detect, in correspondence with a predicted error input from the predicted error computation unit 14, predicted error group information (see Table 1) indicating a group to which the magnitude of the predicted error belongs, output the detected information to a variable length code table 152 described below, detect the number of added bits (see Table 2) related to the group information, detect a bit reduction number by which the number of added bits is to be reduced (see Table 4) according to the target code amount difference level input from the target code amount difference level detection unit 17 described below via a DFF 15-1 with respect to the predicted error group in which the magnitude of the predicted error is equal to or larger than the predetermined value, and output to a DFF 155 a total code length obtained by subtracting the bit reduction number from the sum of a variable length code length (see Table 3) received from the variable length code table 152 and the number of added bits; the variable length code table 152 configured to output to a selector (MUX) 153 described below the variable length code length and the variable length code (see Table 3) corresponding to the predicted error group information received from the bit length detection section 151, and output the variable length code length to the bit length detection section 151; and the selector (MUX) 153 configured to select the variable length code shown in Table 3 and received from the variable length code table 152 and the added bit data shown in Table 2 on the basis of the variable length code received from the variable length code table 152 and the predicted error group information received from the bit length detection section 151, and output the selected code and data as continuous data. Table 3 shows total code lengths if the target code amount difference level=0. The bit length detection section 151 of the predicted error coding unit 15 outputs a total code length reduced in the number of bits to be reduced shown in Table 4 from the original length (Table 3) according to the target code amount difference level from the target code amount difference level detection unit 17 in a case where the magnitude of the predicted error belongs to one of the group of predicted errors equal to or larger than the predetermined value. As a result, encoding is performed while treating as invalid the less significant bit data corresponding to the bit reduction number in the added bit data for the predicted error and excluding the less significant bit data from the object to be encoded.
A packing unit 16 has an adder 163 which adds together the total code length (4-bit data) input from the bit length detection section 151 via the DFF 155 and 5-bit data obtained by cumulatively adding this input total code length data and the past total code length data held in a DFF 164 each time one pixel is encoded (each clock cycle), outputs the less significant 5-bit data in the result of this addition to the DFF 164, and outputs a one-bit signal indicating the match between the addition result and a value equal to or larger than 32 (=4 bytes) as a 4-byte output signal to a DFF 165 when the addition result reaches this value; a selector (MUX) 161 which combines, according to the addition result from the DFF 164, the encoded data (output data from the selector 153) input via the DFF 154 with combined encoded data less than 32 bits obtained by combining past encoded data output from a selector (MUX) 166 so that the encoded data from the DFF 154 follows the past data, and outputs the combined data as new combined encoded data; a DFF 162 which delays the combined encoded data output from the MUX 161 by one clock cycle and outputs the delayed data; and the selector (MUX) 166 which, if the number of valid bits in the combined encoded data from the DFF 162 is 31 or less, outputs combined encoded data formed of more significant 31 bits from the DFF 162 on the basis of a 4-byte output signal from the DFF 165, and which, if the number of valid bits in the combined encoded data from the DFF 162 is 32 or more, outputs combined encoded data formed of less significant bits other than the more significant 32 bits from the DFF 162 (the number of valid bits in these less significant bits being 14 or less) and invalid data (which may have any value and may be zero). The packing unit 16 outputs the above-described combined encoded data in a predetermined code amount unit (e.g., a 4-byte unit) together with a predetermined unit output signal (e.g., a 4-byte output signal) and outputs information on the number of output bytes (e.g., a 4-byte output signal) to the target code amount difference level detection unit 17.
The target code amount difference level detection unit 17 has an adder 172 which adds together a set average code amount (e.g., a code amount of 8 bits per pixel) set in a control unit (not shown) and target code amount difference information (code amount difference cumulative addition result) held in a DFF 173 one clock cycle before, subtracts the number of output bits (e.g., 32) from the addition result when the information on the number of output byte (4-byte output signal) from the packing unit 16 is valid, and outputs the code amount difference cumulative addition result as target code amount difference information via the DFF 173, and a quantization section 174 which is supplied with the target code amount difference information output from the DFF 173 and performs quantization according to the target code amount difference information (see
In the notation in
Thus, reversible compression is performed in the target code amount difference information positive region, even when the magnitude of the predicted error is equal to or larger than the predetermined value, and irreversible compression is performed only when both the condition that the magnitude of the predicted error is equal to or larger than the predetermined value and the condition that target code amount difference information is in the negative region are satisfied.
The operation of the image compressor according to the first embodiment of the present invention will be described with reference to
The target code amount difference level detection unit 17 shown in
When input of image data is started, the target code amount difference information is positive and the target code amount difference level output from the quantization section 174 shown in
In the predicted error computation unit 14 shown in
The predicted error coding unit 15 shown in
The packing unit 16 shown in
Encoding is continued in this way. When the target code amount difference level becomes equal to or higher than 1, the error level detection unit 13 shown in
Table 1 shows group Nos. indicating the ranges of the magnitudes of predicted errors. Table 2 shows the relationship between added bit data and binary expressions (expressions of 2's complements) of the predicted errors for the group information (group Nos.). In Table 2, binary expressions are made by using character variables and an expression to represent a code bit is made by using “S”. In a predicted error binary expression column, data expressed in 2's complement form is shown, in which S represents a plus/minus sign, N represents a bit data defined by bit-inverting the plus/minus sign, and abcdefhg is bit data specifying values in the group in combination with the plus/minus sign. In an added bit data column, S represents one bit of a plus/minus sign and each character in abcdefgh represents data at the corresponding bit position in the binary expression of the predicted error. Table 3 shows a list of variable length codes corresponding to the group Nos., variable length code lengths, numbers of added bits (before reducing the number of added bits according to the target code amount error level) and a list of total code lengths for the predicted errors. At the time of encoding of the given predicted error, the variable length code and added bits corresponding to the group information (group No.) for the predicted error are serially multiplexed to be output as variable length coded data.
Target code amount difference levels 0, 1, 2, and 3 in Table 4 represent steps of the magnitudes of the above-mentioned target code amount difference levels and correspond to the number of bits to be corrected (the number of less significant bits) shown as the target code amount difference level on the ordinate of
Table 5 shows an example of group information PGRP for a predicted error one pixel before. Table 6 shows an example of variable length codes in group information each representing the magnitude of a predicted error at the time of code table change. Table 7 shows a total code length at the time of code table change in Table 6 (before reducing added bits).
In contrast with the above-described example of the configuration shown in
As the variable length coding table 152 in the example of the configuration shown in
The error level detection unit 13 and the predicted error computation unit 14 use only less significant bit data having the same number of bits as the number of input bits and detect an error level and a predicted error while ignoring code overflow to more significant bits (called degeneration in some case). Therefore, the dynamic range of differential data is not increased, reproduction to the same value as the pixel value data output from the input pixel value correction unit 11 can be performed, and the compression efficiency can also be improved.
Decoding reproduction on the decoding side will be described in the following description of a second embodiment of the present invention.
According to the first embodiment, a case where irreversible compression occurs (for example, a case where the target code amount difference information shown in
Also, a storage section in which group information for the magnitude of a predicted error one pixel before is stored is provided and a variable length code in group information indicating the group to which the magnitude of the predicted error belongs is changed according to the magnitude of the predicted error one pixel before, thereby further improving the coding efficiency.
The image expander 20 shown in
According to the second embodiment thus configured, in an image expander configured to decode a predicted error encoded as in the first embodiment, the predicted error is reproduced by setting less significant bit data in added bit data for the reproduced predicted error to 0 according to a target code amount difference level if the predicted error exceeds a predetermined value, thus implementing an image expander not requiring transmission of information on reversibility/irreversibility on a pixel by pixel basis at the time of encoding with respect to encoded data code-amount-controlled by mixing reversible compression and irreversible compression on a pixel-by-pixel basis.
In an image expander 20A shown in
The predicted error decoding unit 22 has a DFF 221 configured to delay, by one clock cycle, variable-length-encoded data output from the encoded data taking-in unit 21, the decoding table 222 (see Tables 3 and 4) which is supplied with variable-length-encoded data from the DFF 221, and which decodes group information indicating a group to which the magnitude of a predicted error belongs and the code length thereof, reproduces the number of added bits for indicating a particular predicted error value in the group on the basis of the group information, reproduces, on basis of the group information, a bit reduction number by which the number of added bits is to be reduced according to the target code amount difference level detected in the target code amount difference level detection unit 25, if the predicted error is equal to or larger than a predetermined value, and generates a total number of bits (code length) as a result of subtraction of the bit reduction number from the sum of the code length of the group information and the number of added bits, and a selector (MUX) 223 which performs code expansion processing on the basis of the code length of the group information (group No.) obtained as a result of decoding with the decoding table 222 in output data from the DFF 221, by removing the encoded data in the group information (group No.) and extracting the added bit data having the number of added bits (see Table 2), substitutes zero for less significant bit data for the bit reduction number in the added bit data (see Table 4 with respect to a condition for substitution of zero and the number of bits), and outputs the resulting data.
The target code amount difference level detection unit 25 has the DFF 251 to which the 4-byte taking-in signal generated in the encoded data taking-in unit 21 is input by a control section (not shown) during a time period other than a two-clock-cycle period for taking in initial data, delays the signal by one clock cycle, and supplies the signal as a 4-byte decoded code amount to minus input end of the adder 252, the adder 252 which is supplied through its one input terminal with a set average code amount (e.g., a code amount of 8 bits per pixel) set by the control section (not shown), and which adds the input set average code amount to the cumulative addition result one clock cycle before held by a DFF 253, subtracts a code amount of 32 bits (4 bytes) from the result of cumulative addition of the set average code amount each time one-bit signal indicating the 4-byte form is input from the DFF 251, and outputs the result of this subtraction as target code amount difference information via the DFF 253, and a quantization section 254 which is supplied with the target code amount difference information output from the DFF 253, and which performs the same predetermined quantization as that on the encoder side on the target code amount difference information (see
The pixel value reproduction unit 23 has an adder 231 which adds the predicted error reproduced in the predicted error decoding unit 22 to a predicted pixel value from the predicted pixel value generation unit 24 to reproduce a pixel value.
The predicted pixel value generation unit 24 generates a predicted pixel value by referring to a past reproduced pixel which is input thereto by one-clock-cycle-delaying by means of a DFF 24-1 a pixel value reproduced by the pixel value reproduction unit 23. The predicted pixel value generation unit 24 may be configured, for example, to directly pass therethrough the output from the DFF 24-1 in the preceding stage that produces a one-clock-cycle delay, while only referring to this output. (That is, the predicted pixel value generation unit 24 may be configured to use the one-clock-cycle-delayed signal from the DFF 24-1 as a predicted pixel value by means of a signal line only.) The predicted pixel value generation unit 24 may alternatively be configured as shown in
The operation of the image expander according to the second embodiment of the present invention will be described with reference to
The encoded data taking-in unit 21 takes in encoded data in a predetermined byte unit from the image compressor according to the code length of decoded pixels from the predicted error decoding unit 22, and supplies data including the result of cueing of data on the next pixel to the predicted error decoding unit 22. The target code amount difference level detection unit 25, if provided in a concrete form as represented by the target code amount difference level detection unit 25 shown in
In contrast with the above-described example of the configuration shown in
Also in the second embodiment, Tables 2, 3, and 6 described in the description of the first embodiment are used. However, these tables are used in a reverse direction in expansion processing in the second embodiment with respect to the correspondence between group information and variable length codes (Tables 3 and 6) and the correspondence between the binary expressions of predicted errors and the added bit data (Table 2) in comparison with compression processing in the first embodiment.
According to the second embodiment, reproducing is performed by substituting 0 for less significant bit data in added bit data corresponding to the number of bits deleted on the encoding side on the basis of a target code amount difference level computable at the time of decoding and group information indicating a group to which the magnitude of an encoded predicted error belongs, and added bits indicating a particular predicted error value in each group is decoded to reproduce the predicted error. Therefore, any reversibility/irreversibility information on a pixel-by-pixel basis at the time of encoding is not required.
Also, a storage section for storing a predicted error one pixel before is provided and a variable length code in group information indicating a group to which the magnitude of a predicted error belongs is changed according to a predicted error one pixel before. In this way, decoding without requiring any code table change information from the encoding side is enabled.
The image processing apparatus 30 shown in
According to the third embodiment, a case where irreversible compression occurs is limited to a case where the magnitude of a predicted error is equal to or larger than a predetermined value, that is, a pixel with a large change in luminance is generated, and where the target code amount difference level is 1 or higher (e.g., a case where comparatively large changes in luminance occur successively close to each other, and where the target code amount difference information shown in
Having described the embodiments of the invention referring to the accompanying drawings, it should be understood that the present invention is not limited to those precise embodiments and various changes and modifications thereof could be made by one skilled in the art without departing from the spirit or scope of the invention as defined in the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2007-180181 | Jul 2007 | JP | national |
