Patent Application
20050088384
The present invention relates to an image display apparatus that is mounted with a micro processor and that displays images on liquid crystal matter.
In recent years, communication terminal apparatuses as typified by mobile phones have evolved with the expansion of image data such as from black-and-white images to color images, from small screens to large screens, and from still images to moving images.
One common method used with respect to communication terminal apparatuses up till this point is to mount an interface in an MPU (Micro Processor Unit) that controls over the entire apparatus and transfer pixels from the MPU to liquid crystal matter directly connected on a bus. Generally, the access speed during the writing of image data from an MPU into liquid crystal matter is lower than the access speed of an apparatus that is directly connected to a bus from an MPU such as memory. For this reason, with the above method it is difficult to present large-volume images on liquid crystal matter at a high speed. Also, in a mobile phone with simpler hardware configurations than a PC (personal computer), the traffic on a bus to the MPU increases dramatically when a large-volume image is transferred, and this results in a processing overload on the MPU.
In contrast, “A MPEG4 Programmable Codec DSP with an Embedded Pre/Post-processing Engine (IEEE 1999 Custom Integrated Circuits Conference)” discloses a structure that increases the access speed of the MPU and memory and enhances computation processing capability to handle large-volume data.
Also, displaying moving images on a liquid crystal display screen and the like requires a graphic combination function, which is a function to combine moving images, characters, and still images. As one technique with respect to graphic combination function, “TECHNICAL REPORT OF IEICE, ED99-61, SMD99-35, ICD-9943 (1999-06)” discloses to perform de/coding processing and graphic image presentation processing of images and to perform combining processing on moving images and graphics.
Nevertheless, because to increase the access speed of an MPU and memory, the clock signal speed needs also to be increased, and the power consumption of battery increases and has an adverse effect on the operation of the apparatus. Furthermore, performing graphic combination requires a memory to store image data that is to be combined as well as a memory to store combined image data. However, providing a processor for the sole use for moving image processing would as a consequence upsize the apparatus, which is inadequate for mobile phones with high demand for the miniaturization of the apparatus.
An object of the present invention is to reduce the traffic on a bus to the MPU by relatively simple additions of functions without impairing display quality and to provide an image display apparatus that can present a large-volume image such as a moving image.
The above object can be achieved by disposing busses for the sole use for connecting liquid crystal matter to a buffer that temporarily stores the image data to be displayed on this liquid crystal matter, by thus making it unnecessary to use the busses to the MPU when outputting image data from a buffer to liquid crystal matter, and by using memory on liquid crystal matter for graphic combination.
One method of reducing the power consumption in a mobile phone is to provide a memory on liquid crystal matter and to read out and display image data from this memory when no image updating is required such as during waiting periods. Also, to minimize the data volume upon displaying a moving image, portions like the background that do not change from previous images are not updated, and the image data in specific areas is updated and combined with previous images. The present inventors have arrived at this invention focusing on these points.
That is to say, the gist of the present invention is to output image data from a buffer that temporarily stores the image data on liquid crystal matter, by not using the busses to the MPU but by using other routes, and to use the memory on liquid crystal matter for graphic combination.
The embodiments of the present invention will be described in detail with reference to attached drawings.
Image display section 104 comprises LCD panel 111 that displays images, driver 112 that runs LCD panel 111, and LCD controller 113 that controls over image presentation on LCD panel 111.
In the image display apparatus shown in
Image address bus 123 connects display buffer 105 and LCD controller 113, and write-signals and the like flow upon the bus. Image data bus 124 connects display buffer 105 and LCD controller 113, and image data flows upon the bus. Hereinafter image address bus 123 and image data bus 124 will be uniformly referred to as “image-only busses.”
Next, the operation of image display apparatus 100 shown in
MPU 101 outputs a read-signal to ROM 102 via address bus 121 and reads out a program from ROM 102 via data bus 122. MPU 101 then produces image data based on the read program and stores the image data in RAM 103 via data bus 122.
To display image data on LCD panel 111 in image display section 104, MPU 101 outputs a read-signal to RAM 103 via address bus 121 (ST 201) and reads out image data A from RAM 103 (ST 202).
MPU 101 then outputs a read-signal to decoder 106 via address bus 121, and decoder 106 converts the read-signal into a write-signal, selects an address, and outputs the signal to display buffer 105 (ST 203). Image data A is written via data bus 122 into the address selected by decoder 106 of display buffer 105 (ST 204).
When image data A of one or more pixels is written, display buffer 105 outputs a write-signal to LCD controller 113 via image address bus 123 at the access timing of LCD controller 113 (ST 205) and writes the image data into LCD controller 113 via image data bus 124 (ST 206). Display buffer 105 then, upon completing the writing of image data A into LCD controller 113, outputs to MPU 101 a signal that indicates the completion of writing (hereinafter “writing completion signal”) (ST 207).
After this, image display apparatus 100 repeats the operations of ST 201˜ST 207 with respect to following image data B.
By thus providing display buffer 105 that temporarily stores image data, and image-only busses that connect display buffer 105 and LCD controller 113 which is liquid crystal matter, it is possible to make the busses to MPU 101 stay open while image data is written from display buffer 105 into LCD controller 113, and to thus reduce the traffic from MPU 101 to LCD controller 113. As a result, while the busses to MPU 101 are open, MPU 101 can perform other processing such as producing subsequent image data by reading out programs from ROM 102.
Also, by integrating MPU 101, display buffer 105, and decoder 106 into a chip, it is possible to make display interface (I/F)-mounting MPU 131 and miniaturize the apparatus.
It is also possible, in case the data width in display section 104 is less than half the width of data bus 122, to divide image data into two or more in display buffer 105 and then write the image data into LCD controller 113. By this means it is possible to open up address bus 121 and data bus 122 to other processing and to write data of two or more pixels into LCD controller 113 by one access.
In comparison with image display apparatus 100 shown in
Address bus 121 connects with MPU 101, ROM 102, and RAM 103, and a signal line from address bus 121 to RAM 103 splits and connects with decoder 106. Data bus 122 connects with MPU 101, ROM 102, and RAM 103. Image data bus 124 connects data bus 122 and LCD controller 113.
Next, the operation of image display apparatus 300 shown in
MPU 101 outputs a read-signal to ROM 102 via address bus 121 and reads out a program from ROM 102 via data bus 122. MPU 101 then produces image data based on the read program and stores the image data in RAM 103 via data bus 122.
To display image data on LCD panel 111 in image display section 104, MPU 101 outputs a read-signal to RAM 103 and to decoder 301 via address bus 121 and then reads out image data A from RAM 103 (ST 401, ST 402). Decoder 301 converts the read-signal into a write-signal and outputs the signal to LCD controller 113 (ST 403).
Image data A read out from RAM 103 is written via image data bus 124 into an address selected by decoder 301 of LCD controller 113 (ST 404).
After this, image display apparatus 300 repeats the operations of ST 401˜ST 404 with respect to following image data B.
By thus reading from RAM 103 and writing into LCD controller 113 simultaneously it is possible to implement image presentation by half the number of accesses compared to the past, and to thus reduce the traffic from MPU 101 to LCD controller 113.
Also, by integrating MPU 101, display buffer 105, and decoder 106 into a chip it is possible to make display interface(I/F)-mounting MPU 131 and miniaturize the apparatus.
Embodiment 3 is acombination of the above Embodiment 1 and Embodiment 2.
In comparison with image display apparatus 100 shown in
Next, the operation of image display apparatus 500 shown in
MPU 101 outputs a read-signal to ROM 102 via address bus 121 and reads out a program from ROM 102 via data bus 122. MPU 101 then produces image data based on the read program and stores the image data in RAM 103 via data bus 122.
To display image data on LCD panel 111 in image display section 104, MPU 101 outputs a read-signal to RAM 103 and to decoder 301 via address bus 121 (ST 601). At the same time, decoder 301 converts the read-signal into a write-signal and outputs the signal to display buffer 105 (ST 602). Image data A is written via data bus 122 into an address selected by decoder 301 of display buffer 105 (ST 603).
When one or more pixel units of image data A is written, display buffer 105 outputs a write-signal to LCD controller 113 at the access timing of LCD controller 113 (ST 604), and writes the image data into LCD controller 113 via image data bus 124 (ST 605).
After this, image display apparatus 500 repeats the operations of ST 601˜ST 605 with respect to following image data B.
By this means it is possible to make address bus 121 and data bus 122 open to other processing while image data is written from display buffer 105 into LCD controller 113, and to implement image presentation by half the number of accesses compared to the past, and to thus reduce the traffic from MPU 101 to LCD controller 113.
Also by integrating MPU 101, display buffer 105, and decoder 301 into a chip, it is possible to make display interface(I/F)-mounting MPU 511 and miniaturize the apparatus.
In comparison with image display apparatus 100 shown in
Address bus 121 connects with MPU 101, ROM 102, and RAM 103, and data bus 122 connects with MPU 101, ROM 102, and RAM 103. Image data bus 124 connects RAM 103 and LCD controller 113.
MPU 101 outputs a signal that instructs to start writing image data (hereinafter “start-writing-instruction signal”) to display control section 701.
Upon receiving a start-writing-instruction signal, display control section 701 outputs a read-signal to RAM 103 and a write-signal to LCD controller 113. Display control section 701 then, when a predetermined volume such as one screen of data is read out from RAM 103 and written into LCD controller 113, outputs a writing-completion signal to MPU 101.
By thus providing display control section 701 and controlling data from the point of reading out data from RAM 103 to the point of writing the data into LCD controller 113 without involving MPU 101, it is possible to reduce the traffic on the busses involved in image presentation by MPU 101, and to thus reduce the processing load on MPU 101 in image presentation processing.
In comparison with image display apparatus 100 shown in
Address bus 121 connects with MPU 101, ROM 102, and RAM 103, and memory control section 811, while data bus 122 connects with MPU 101, ROM 102, and RAM 103, and memory control section 811.
Furthermore, image address bus 121 and image data bus 124 connect memory control section 811 and LCD controller 113.
MPU 101 outputs a signal that instructs to start decoding processing (hereinafter “start-decoding-instruction signal”) to memory control section 811 via address bus 121.
Memory control section 811 has frame memory inside and temporarily stores the image data coded in JPEG or M-PEG4 or the like, and, for example upon storing one screen of image data, outputs the image data to image de/coding section 812 in accordance with a start-writing-instruction signal. Also, memory control section 811 outputs image data stored in frame RAM 813 to LCD controller 113 in synch with the access timing of LCD controller 113 via image data bus 124.
Image de/coding section 812 decodes image data coded in JPEG or M-PEG4 or the like and writes the data into frame RAM 813. Frame RAM 813 stores the image data decoded in image de/coding section 812 and outputs the image data to memory control section 811.
By thus providing image de/coding unit 801 and writing decoded image data into LCD controller 113 via image data bus 124, it is possible to present data, in particular coded data such as moving images, on image display section 104 without monopolizing data bus 121, and to thus reduce the processing load on the overall apparatus.
Incidentally, it is possible to arrange image de/coding unit 801 with a DSP (Digital Signal Processor) and thus miniaturize the apparatus.
It is also possible that memory control section 811 synchronizes a screen of data with vertical synchronization signals and outputs each pixel to image display section 104 in synch with write-signals, and image display section 901 presents images on LCD panel 111 in synch with vertical synchronization signals, horizontal synchronization signals, and with write-signals. By this means, the display operates in synch with continuously-output images like moving images and the like, which makes it possible to perform image presentation whereby the re-writing on the display screen is invisible, and to thus offer high-quality images.
In comparison with image display apparatus 800 shown in
In comparison with image display section 104, image display section 901 employs a configuration in which LCD controller 113 is removed and command control section 911, R/W section 912, writing section 913, frame memory 914, and reading section 915 are added. Incidentally, frame memory 914 is a preexisting circuit used to store the image data displayed during the memory-waiting periods.
Image de/coding unit 801 discerns a specified area that MPU 101 specifies for updating, and stores in frame 813 the image data which is in the specified areas and which is smaller in the number of pixels compared to image display section 901. Memory control section 811 also outputs a command/data selection signal that determines whether the data to be written into a liquid crystal module is a command to control liquid crystal matter or image data to be displayed on liquid crystal matter.
Command control section 911 interprets an input command and sets a control signal that meets the command in R/W control section 912. For instance, when a command to specify a particular area is transmitted, command control section 911 interprets the command and informs R/W section 912 of the area on a display screen for next presentation.
R/W control section 912, based on the image presentation area specified for instance by command control section 911, recognizes that data transmitted from data bus 122 is for the specified area, and controls over writing section 913 and reading section 915. Furthermore, R/W control section 912 performs functions such as adjusting the timing for reading and writing from/in frame memory.
Writing section 913 writes into frame memory 914 the image data input from image data bus 124 in accordance with a write-signal input from image address bus 123.
Frame memory 914 temporarily stores image data to be written into a liquid crystal module. Normally, in a liquid crystal module, it is required to output image data to liquid crystal matter at predetermined intervals to refresh data on a liquid crystal panel. On the other hand, image data from MPU 101 is written on an irregular basis, and so frame memory 914 performs a function whereby the written data is temporarily stored in frame memory 914 and then read out on a regular basis from frame memory 914 to liquid crystal matter.
Reading section 915 performs reading control to read out image data from frame memory 914, as well as writing control to write the read-out image data into a liquid crystal module.
By thus storing image data in preexisting circuit frame memory 914 and superposing images for specific areas produced in image de/coding unit 801, and previously produced images, that is to say, by using memory on liquid crystal matter for graphic combination, it is possible to present a large-volume image such as a moving image at a high-speed by relatively simple additions of functions, and to thus reduce the cost. Similarly, with the data flowing on data bus 122 decreasing in volume, it is possible to reduce the traffic on the busses involved in image presentation by MPU 101. Furthermore, it is possible to miniaturize the apparatus by reducing the memory size of frame RAM 813.
It is also possible that memory control section 811 synchronizes a screen of data with vertical synchronization signals and outputs individual pixels to image display section 104 in synch with write-signals, and image display section 901 presents images on LCD panel 111 in synch with vertical synchronization signals, horizontal synchronization signals, and with write-signals. By this means, the display operates in synch with continuously-output images like moving images and the like, which makes it possible to perform image presentation whereby the re-writing on the display screen is invisible, and to thus offer high-quality images.
In comparison with image display apparatus 900 shown in
Following the instructions from MPU 101, prohibition bit generating section 1101 outputs to image display section 901 a prohibition bit that prohibits the update of the areas that do not update the display.
Assuming that in
By thus outputting prohibition bits from memory control section 811 to image display section 901, it is possible, in addition to that memory on liquid crystal matter can be used for graphic combination, that in image display section 901, images can be updated only in certain areas, while full-display output is in progress. Similarly, with the data flowing on data bus 122 decreasing in volume, it is possible to reduce the traffic on the busses involved in image presentation by MPU 101.
It is also possible that memory control section 811 synchronizes a screen of data with vertical synchronization signals and outputs individual pixels to image display section 104 in synch with write-signals, and image display section 901 presents images on LCD panel 111 in synch with vertical synchronization signals, horizontal synchronization signals, and with write-signals. By this means, the display operates in synch with continuously-output images like moving images and the like, which makes it possible to perform image presentation whereby the re-writing on the display screen is invisible, and to thus offer high-quality images.
In comparison with image display apparatus 1100 shown in
Following the instructions from MPU 101, update allowing bit generating section 1411 outputs to image display section 901 an update allowing bit that indicates as to whether or not the updating of prohibition bits should be allowed. When an update allowing bit that instructs to the effect of disallowing the updating of a prohibition bit is input, image display section 901 displays previously displayed image data with respect to the area that is specified by the prohibition bit held by prohibition bit holding memory 1401.
In
With image display section 901 thus holding prohibition bits, it is possible to reduce the number of times to generate prohibition bits, and to thus reduce the power consumption, in addition to the effect by Embodiment 7.
It is also possible that memory control section 811 synchronizes a screen of data with vertical synchronization signals and outputs individual pixels to image display section 104 in synch with write-signals, and image display section 901 presents images on LCD panel 111 in synch with vertical synchronization signals, horizontal synchronization signals, and with write-signals. By this means, the display operates in synch with continuously-output images like moving images and the like, which makes it possible to perform image presentation whereby the re-writing on the display screen is invisible, and to thus offer high-quality images.
In comparison with image display apparatus 900 shown in
With this embodiment, update prohibiting image data is defined with, for instance, 12-bit image data “000000000000,” instead of using prohibition bits as described with Embodiment 7, and prohibition bit generating decoder 1701 generates prohibition bits when update prohibiting image data is input and outputs the prohibition bits to R/W control section 912.
By this means the same effect as Embodiment 7 can be achieved. It is also possible to achieve the same effect as Embodiment 8 by additionally introducing holding memory 1401 shown in
It is also possible that memory control section 811 synchronizes a screen of data with vertical synchronization signals and outputs individual pixels to image display section 104 in synch with write-signals, and image display section 901 presents images on LCD panel 111 in synch with vertical synchronization signals, horizontal synchronization signals, and with write-signals. By this means, the display operates in synch with continuously-output images like moving images and the like, which makes it possible to perform image presentation whereby the re-writing on the display screen is invisible, and to thus offer high-quality images.
Embodiment 10 has a structure that combines above Embodiment 1 and Embodiment 5 to switch paths for writing into an LCD controller depending on non-coded image data and coded image data.
In comparison with image display apparatus 100 shown in
By controlling tri-state buffers 1802-1 to 1802-5, image switching section 1801 displays non-coded data on image display section 104 via display buffer 105, and coded image data on image display section 104 via image de/coding unit 801.
By thus switching writing paths by image data switching section 1801, it is possible to present both coded image data and non-coded image data on image display section 104 without monopolizing data bus 121, and to thus reduce the processing load on the overall image display apparatus.
Image display apparatus 1800 may mount image data switching section 1801 inside memory control section 811.
Also, by integrating MPU 101, display buffer 105, and decoder 106 into a chip, it is possible to make display interface(I/F)-mounting MPU 131, as in Embodiment 1.
It is also possible to divide image data into two or more in display buffer 105 and write the data into LCD controller 113, in case the data width in display section 104 is less than half of the width of data bus 122.
By employing a configuration in which display buffer 105 and decoder 106 are removed and decoder 3 shown in
By employing a configuration in which a signal line from address bus 121 to RAM 103 splits and connects with decoder 106 as shown in
Furthermore, by employing a configuration in which display buffer 105 and decoder 106 are removed and display control section 701 is added as shown in
Also, by halting the power and clock signal supplied to image de/coding unit 801 while no image data is output from image de/coding unit 801, it is possible to reduce the power consumption. One of the methods to implement this halting of a power supply and clock signal is to halt the power and clock signal supplied to the LSI from outside in case image de/coding unit 801 is a single LSI, or to provide a gate mechanism that halts a power supply and clock signal within the LSI.
Embodiment 11 is a structure that combines above Embodiment 6 and Embodiment 10 to switch paths for writing into an LCD controller depending on non-coded image data and coded image data, and that furthermore updates specified areas only.
In comparison with image display apparatus 1800 shown in
By thus switching writing paths with image data switching section 1801, it is possible to present both coded image data and non-coded image data on image display section 104 without monopolizing data bus 121, and to thus reduce the processing load on the overall image display apparatus. Also by thus storing image data in frame memory 914, which is a preexisting circuit, and by superposing the image which is in a special area and which is produced in image de/coding unit 801, and a previously produced image, it is possible to thus use memory on liquid crystal matter for graphic combination. Accordingly, it is possible to present an image obtained by combining both coded image data and non-coded image data at a high-speed by relatively simple additions of functions, which also makes possible a reduction in the cost.
It is also possible that memory control section 811 synchronizes a screen of data with vertical synchronization signals and outputs individual pixels to image display section 104 in synch with write-signals, and image display section 901 presents images on LCD panel 111 in synch with vertical synchronization signals, horizontal synchronization signals, and with write-signals. By this means, the display operates in synch with continuously-output images like moving images and the like, which makes it possible to perform image presentation whereby the re-writing on the display screen is invisible, and to thus offer high-quality images.
By additionally introducing prohibition bit generating section 1101 shown in
By additionally introducing holding memory 1401 and update allowing bit generating section 1411 shown in
By additionally introducing prohibition bit generating decoder 1701 shown in
In comparison with image display apparatus 100 shown in
Address bus 121 connects with MPU 101, ROM 102, RAM 103, decoder 106, and memory control section 2111. Data bus 122 connects with MPU 101, ROM 102, RAM 103, display buffer 105, and memory control section 2111.
Memory control section 2111 temporarily stores the image data coded in JPEG or M-PEG4 in internal memory to output to image de/coding section 2112, and further temporarily stores the image data output from color subtracting section 2113 to output to MPU 101 via data bus 122 in accordance with a read-signal.
Image de/coding section 2112 decodes the image data coded in JPEG or in M-PEG4 and outputs the image data to color subtracting section 2113.
Color subtracting section 2113 performs color subtracting processing on the data output from image de/coding section 2112 to give the image data a bit width required to be displayed on image display section 104, and outputs the image data to memory controlling section 2111.
For instance, provided that the original number of bits per pixel in decoded image data is 8 for red, green, and blue each, and is 24 in total (full-color) and that the bit number in image display section 104 is 8 bits, image de/coding section 2101 subtracts color from decoded 24-bit image down to 8-bit image immediately after decoding, and stores the image in the internal memory of memory control section 2111. Thereafter, image de/coding unit 2101 writes two pixels of data into display buffer 105 via data bus 122 using a 16-bit bus.
By thus subtracting color from decoded image data, the traffic on the MPU busses can be reduced by large.
In comparison with image display apparatus 100 shown in
Address bus 121 and data bus 122 each connect with MPU 101, ROM 102, RAM 103, display buffer 105, and DMAC 2202.
In image display apparatus 2200 shown in
Upon obtaining the bus-use right from bus arbiter 2201, DMAC 2202 autonomously controls over address bus 121 and data bus 122, reads out image data from RAM 103 and writes the image data into image display buffer 105.
Thus with DMAC 2202, it is possible to exchange data between an input/output apparatus and memory without the MPU, and to thus increase the data transmission speed and reduce the load on the MPU.
In comparison with image display apparatus 2200 shown in
Address bus 121 and data bus 122 each connect with MPU 101, ROM 102, RAM 103, and display buffer 105.
DMAC 2301 is included in display buffer 105 and, upon obtaining the bus-use right from bus arbiter 2201, autonomously controls over address bus 121 and data bus 122 and reads out image data from RAM 103.
Next, the operation of image display apparatus 2300 shown in
MPU 101 outputs a read-signal to ROM 102 via address bus 121 and reads out a program from ROM 102 via data bus 122. MPU 101 then produces image data based on the read program and stores the image data in RAM 103 via data bus 122.
To display image data on LCD panel 111 in image display section 104, DMAC 2301 outputs a read-signal to RAM 103 via address bus 121 and reads out image data A from RAM 103 (ST 2401, ST 2402).
Image data A read out from RAM 103 is written into an address selected by DMAC 2301 in display buffer 105 via image data bus 124 (ST 2403, ST 2404).
After this, image display apparatus 2300 repeats the operations of ST 2401˜ST 2404 with following image data B.
By thus including DMAC 2301 in display buffer 105 it is possible to read out from RAM 103 and write into display buffer 105 in one step, and to thus perform data transmission at a higher speed than Embodiment 13 that requires two steps of reading out from RAM 103 and writing into buffer 105.
With respect to liquid crystal matter in a mobile phone and the like, there are cases where it is unnecessary to update the full-screen but where it suffices to update the screen only partially.
A screen of image data is displayed from the upper left to lower right in
By thus prescribing (setting) a start address Z, VRAM horizontal direction dot number XX, rectangular transfer area horizontal dot number X, and rectangular area line number Y, it is possible to autonomously calculate a memory address corresponding to the rectangular display to be updated, and to thus reduce the processing load on MPU 101.
In comparison with image display apparatus 2300 shown in
FIFO section 2701 temporarily stores the image data read out from RAM 103 and outputs the image data to LCD controller 113 on an FIFO (First-In-First-out) basis.
Next, the operation of image display apparatus 2700 shown in
MPU 101 outputs a read-signal to ROM 102 via address bus 121 and reads out a program from ROM 102 via data bus 122. MPU 101 then produces image data based on the read program and stores the image data in RAM 103 via data bus 122.
To display image data on LCD panel 111 in image display section 104, DMAC 2301 outputs a read-signal to RAM 103 via address bus 121 and reads out image data A from RAM 103 on a t1 time cycle basis (ST 2801, ST 2802).
Image data A read out from RAM 103 is written into FIFO section 2701 in display buffer 105 via image data bus 124 (ST 2803).
Display buffer 105 writes the image data written into FIFO section 2701 into LCD controller 113 on a t2 time cycle basis (ST 2804, ST2805).
After this, image display apparatus 2700 repeats the operations of ST 2801˜ST 2805 with following image data B˜F.
By thus including FIFO section 2701 in display buffer 105, it is possible to absorb in FIFO 2701 the time differential between the time cycle by which the MPU busses read out image data from RAM 103 and the time cycle by which display buffer 105 writes into LCD controller 113, and this makes it possible to read out from RAM 103 to display buffer 105 without modifying the access speed of the MPU busses. Therefore, while the MPU busses read out image data to display buffer 105 at a high speed and display buffer 105 writes into LCD controller 113 at a low speed, MPU 101 is open to other processing, so that the processing load on MPU 101 can be reduced.
Generally speaking (in general), the access time of image data bus 124 lags compared to the access time of data bus 122. However, in
In comparison with image display apparatus 2300 shown in
Bus arbiter 2201 controls over bus switch 2901 and bus switch 2902 and separate the busses. Hereinafter, drawing a line with bus switch 2901 and with bus switch 2902, the left half in
By thus separating the busses it is possible to operate display buffer 105 and display on LCD panel 111 without halting the operation of MPU 101, and to thus enhance the processing performance of MPU 101.
Now in a general TFT(Thin Film Transistor)-LCD, the writing of data into LCD controller 113 is performed in synch with the image update cycle of an LCD (50˜70 Hz). In contrast to this, image presentation on an LCD panel is performed out of synch with the image update cycle of an LCD, that is, at a random timing.
In comparison with image display apparatus 2300 shown in
Timer 3101 outputs a pulse signal to DMAC 2301 and LCD controller 113 by the image update cycle of the LCD. DMAC 2301 activates at the timing of this pulse signal, and LCD controller 113 updates the image on LCD panel 111 by the image update cycle of the LCD.
Next, the operation of image display apparatus 3100 shown in
Upon receiving the pulse signal Vsync, DMAC 2301 transfers one screen of image data to LCD controller 113. The broken line in
By thus transferring image data from display buffer 105 to LCD controller 113 in synch with the image update cycle of the LCD, it is possible to prevent a cross point from occurring, so that a flicker on the screen can be prevented. Also, with the present embodiment, timer 3101 is disposed inside display buffer 105, and LCD controller 113 in image display section 104 receives a pulse signal. However, a configuration in which a timer is disposed in image display section 104 and DMAC 2301 inside display buffer 105 receives a pulse signal may be good as well.
In comparison with image display apparatus 2300 shown in
When the bus width of data bus 122 and the bus width of image data bus 124 differ, bus width modifying section 3301 modifies the alignment of the image data that arrives through data bus 122 and outputs the image data to image data bus 124.
By this means it is possible to make the bus width of data bus 122 bigger than the bus width of image data bus 124, and transfer a number of pixels of image data at one time, and to thus reduce the processing load on MPU 101.
Generally, the bit width in the internal memory in MPU 101 is 8×2n−1bit (n is a natural number), such as 8 bits, 16 bits, and 32 bits, and by thus carrying image data in these bit-width units, memory can be used with efficiency. However, if an LCD is capable of displaying 18 bits (RGB=666), the bit width in the internal memory in MPU needs to be 32 bits, and 14 bits out of these 32 bits are of no use. Embodiment 19 will describe a case that copes with this problem.
In comparison with image display apparatus 2300 shown in
Color number expanding section 3501 performs bit expansion processing on the image data transferred to display buffer 105 in accordance with the display capacity of the LCD.
By this means, for instance when the LCD is capable of displaying 18 bits, one pixel of data can be produced by expanding 16-bit data. As a result, it becomes unnecessary to expand the image data range of the MPU to 32 bits or the like, and the volume of the internal memory in MPU 101 can be reduced. Furthermore, mounting a display buffer according to the present invention may result in heightening the versatility of the apparatus for the LCDs of various color numbers.
In comparison with image display apparatus 2300 shown in
Here, as described with Embodiment 19, generally the bit width in the internal memory in MPU 101 is 8×2n−1bit (n is a natural number), such as 8 bits, 16 bits, and 32 bits. For instance, in image data with one pixel being 16 bits, if the complete 16 bits are used for color presentation, 65536 colors can be presented. However, if one bit is used as a prohibition bit, only 15 bits become available for color presentation with 32768 colors to be presented.
To avoid this, prohibition bit generating section 3701 sets one specific color available as a prohibition bit (hereinafter “specified color”). LCD controller 113 performs the processing that converts a detected specified color into a prohibition bit, and does not update the specified areas on the display screen.
By thus using only one color as a specified color it is possible to present nearly the same number of colors as when the complete bits are used for color presentation, besides generating prohibition bits. For instance, with image data with each pixel being 16 bits, 65535 colors can be presented, which is minus one color from 65536 colors as in the case that the complete 16 bits are used for color presentation. It is thus made possible to reduce the volume of the internal memory in MPU 101 without impairing the quality on the display screen.
In comparison with image display apparatus 2300 shown in
By making the image display apparatus bus-connectable to an external display apparatus, it is possible to add to image display section 104 a number of blocks that transfer image data. As a result, it is possible, for instance, to connect the blocks that process or display moving images in parallel and heighten the expandability of the apparatus.
However, there are cases where either the display image from display buffer 105 or the display image from an external display apparatus drops when the two images superpose. To solve this problem, upon receiving an image output request signal from display buffer 105 or from an external display apparatus, bus control section 3801 determines the presence/absence of a valid signal that indicates that data transmission is in progress, and in case there is no valid signal, that is to say, only in case no image data is transferred to image display section 104 from other sources, allows to open up the display busses.
As apparent from the above description, according to the present invention, it is possible to output image data from a buffer that stores the image data on liquid crystal matter on a temporary basis to a liquid crystal matter using routes other than the MPU busses, and to thus reduce the traffic from the MPU to liquid crystal matter by relatively simple additions of functions such as a buffer, decoder, and the like. In addition, according to the present invention, by using the memory on liquid crystal matter for graphic combination, it is possible to present a large-volume of image data such as moving images by relatively simple additions of functions.
This application is based on the Japanese Patent Application No. 2000-327261 filed on Oct. 26, 2000, and Japanese patent application No. 2001-188725 filed on Jun. 21, 2001, entire content of which is expressly incorporated by reference herein.
The present invention is suited for use in radio communication terminal apparatus and cellular phones that display images on liquid crystal matter.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2000-327261 | Oct 2000 | JP | national |
| 2001-188725 | Jun 2001 | JP | national |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 10168962 | Jun 2002 | US |
| Child | 11010364 | Dec 2004 | US |
