Patent Grant
9741297
The present disclosure relates to an image display apparatus which performs image display by driving display elements with analog voltage obtained by digital-analog conversion (hereinafter, referred to as DA conversion) for digital video signal using ramp signal or the like.
Image display apparatuses that have made a considerable progress in recent years are display panel apparatuses using liquid crystals (liquid crystal display apparatuses). The liquid crystal display apparatuses are widely used in view finders and liquid crystal display panels of video cameras, televisions for automobiles, display panels of navigation systems, displays of notebook personal computers, and the like.
The liquid crystal display apparatuses are originally configured to display analog video signal. The driver circuit of a liquid crystal display apparatus with a high resolution and a high image quality is very large in scale and requires a lot of chips. Moreover, the driver circuit needs to be highly accurate. The cost restriction of the display panel is one of major factors to determine the display quality.
In recent years, peripheral circuits are being increasingly digitalized. It is therefore convenient for the entire system that the video signal is inputted to liquid crystal elements in the form of digital data. In order to implement high image quality without increasing the circuit scale for satisfying the cost restriction, an image display apparatus is proposed, which includes a DA converter to convert digital video signal to analog video signal (refer to Japanese Unexamined Patent Application Publication No. 6-178238 (PTL 1)).
In the conventional image display apparatus described in PTL 1, the same number of video switches (analog switches) as the number of pixels per line are turned on simultaneously at the beginning of every horizontal scanning period, and a simple ramp signal with the same period as the horizontal scanning period including all video signal components from black to white is supplied to data lines through the respective analog switches.
A counter counts based on a clock with a predetermined frequency and outputs the counter value sequentially, changing from the minimum to maximum value in each horizontal scanning period.
Comparators compare digital data of the video signal displayed in each horizontal scanning period with the counter value of the counter on a pixel-by-pixel basis, and output a matching pulse when the digital data matches the counter value. The analog switches provided, corresponding to the comparators remain turned off after the matching pulse is outputted.
The level of the ramp signal, just before each analog switch is turned off, is sampled and held to be supplied to the corresponding pixel. The digital video signal is thereby converted to the analog video signal.
The liquid crystal display apparatus described in PTL 1 is configured to sample and hold predetermined voltages corresponding to digital data based on the referential ramp signal.
The liquid crystal display apparatus described in PTL 1 has an advantage of implementing high image quality without increasing in circuit scale.
However, in some pictures to be displayed, the same voltage is sampled and held at the same time for plural pixels, or some voltages are not sampled and held at all. The load on the ramp signal therefore significantly changes in many cases. Such changing load causes tonality degradation called streaking in the displayed image.
When digital data of the original image is inputted to the liquid crystal display apparatus, the liquid crystal display apparatus displays the image illustrated in
The liquid crystal display apparatus displays the display image as illustrated in
The cause thereof is described using
Herein, the n analog switches correspond to the number of pixels arranged in the horizontal direction of the screen and are turned on at the beginning of every horizontal scanning period.
Pixel values of the digital video signal are compared with respective counter values of n counters (not illustrated) which count up from the minimum to the maximum value in each horizontal scanning period. Each counter is configured to output a matching pulse when the pixel value matches the counter value. By the matching pulse, the analog switch at the position of the pixel corresponding to the counter whose counter value matches the pixel value is turned off until the beginning of the next horizontal scanning period.
When turned off, the analog switch samples the ramp signal, which starts from the minimum gray level at the beginning of each horizontal scanning period and reaches the maximum gray level just before the end of the horizontal scanning period, and outputs the sampled ramp signal voltage to the corresponding pixel circuit.
In
Herein, the input voltage V1(s) of the analog switches is expressed by Equation (1) below. In Equation (1), s is the number of analog switches which are simultaneously turned off at a certain time, and 0<=s<=n.
V1(s)=[Z1/{(n−s)Z0+Z1}]V0 (1)
In the black background (image 1b) illustrated in
Herein, it is assumed that Z0=1, Z1=100, and n=256. The horizontal width of the 50% gray image 2b illustrated in
The number s of analog switches turned off is also referred to as the number of off analog switches.
It is assumed that the original buffer output voltage V0 is 0.5 in displaying a 50% gray image.
Based on Equation (1), the input voltage V1(192) of the analog switches in displaying image 2b is 0.305, and the input voltage V1(128) of the analog switches in displaying image 3b is 0.219.
The images 2b and 3b, which originally must be displayed with an identical gray level, are different in horizontal width and are therefore different in number s of analog switches simultaneously turned off. This results in the difference in gray level as described above.
Moreover, in the processes of displaying images 2b and 3b, the input voltage V1 must be 0.5 (50%) but is lower than 0.5. Accordingly, images 2b and 3b have lower gray levels.
It is therefore revealed that the changes in buffer load, depending on the number s of off analog switches in each line display period (each horizontal scanning period) causes tonality degradation.
In order to solve the aforementioned problem, an image display apparatus described in Japanese Unexamined Patent Application Publication No. 2011-53644 (PTL 2) is configured as follows. The image display apparatus described in PTL 2 includes the same number of dummy pixels as the number of pixels in a row of the pixel section. To a signal line connected to the dummy pixels, current to charge the parasitic capacitance of the signal line due to ramp signal supplied through a ramp signal line is flown.
The image display apparatus described in PTL 2 includes at least one current detector to detect the charging current, a wire having an end connected to the point of connection between each of plural analog switches (video switches), and a ramp signal line. In the image display apparatus, plural dummy loads are provided for the respective wires, and the charging current detected by the current detectors is applied to the dummy loads.
In the image display apparatus described in PTL 2, current having the same value as the charging current flowing through the data lines connected to the analog switches turned off is flown to the dummy loads corresponding to the analog switches turned off, so that changes in current in the ramp signal line can be compensated accurately. In the image display apparatus described in PTL 2, therefore, changes in voltage in the ramp signal line can be reduced accurately.
However, in the liquid crystal display apparatus of PTL 2, it is necessary to provide the dummy pixels for the liquid crystal display elements. When the dummy pixels are provided, the increase in scale of the internal circuit section of each liquid crystal display element prevents high-density arrangement of pixels. Moreover, the increase in circuit scale reduces the yield and increases the cost.
In addition, the dummy pixels cannot reduce tonality degradation precisely because of variation in the dummy pixels in some cases. Once the liquid crystal display elements are designed, the variation in dummy pixels cannot be controlled. The liquid crystal display apparatus therefore cannot display a high quality image excellent in tonality.
An aspect of the embodiments provides an image display apparatus, including: a pixel section including a plurality of pixels arranged at intersections of a plurality of data lines and a plurality of gate lines; a vertical direction driver configured to sequentially supply a pixel selection signal to the plurality of gate lines and sequentially select each pixel of the pixel section on the basis of pixels of each line; a plurality of analog switches connected to the plurality of data lines one to one; a holding section configured to hold image data of pixels of a line of a display digital video signal; a conversion analog signal generator configured to generate a ramp signal composed of a sawtooth wave, to commonly supply the generated ramp signal to the plurality of analog switches, and to supply image data of the pixels of the line to the holding section in synchronization with the ramp signal, the ramp signal changing in level with time at such a slope that the level of the ramp signal starts with one of black and white levels at the beginning of each horizontal scanning period and reaches the other level right before the end of the horizontal scanning period and the slope is variably-controlled in accordance with the number of analog switches turned off among the plurality of analog switches to be non-linear; and a controller configured to simultaneously turn the plurality of analog switches on at the beginning of each horizontal scanning period to supply the ramp signal to the plurality of data lines through the plurality of analog switches, to compare on a pixel-by-pixel basis, the image data of the pixels of the line held by the holding section with a first counter value sequentially changing from one of minimum and maximum gray levels to the other in each horizontal scanning period, to turn off only the analog switches provided corresponding to the pixels having pixel data matching the first counter value until the beginning of the next horizontal scanning period, and through the data lines connected to the analog switches turned off, to cause the pixels to sample and hold the potential of the ramp signal just before the analog switches are turned off.
The conversion analog signal generator includes: a histogram value output section configured to detect histogram values of respective gray levels included by image data of the pixels of the line and outputs histogram value data at each horizontal scanning period; an accumulator configured to accumulate the histogram value data to calculate a cumulative sum representing the number of analog switches turned off among the plurality of analog switches; a ramp signal data generator configured to generate ramp signal data having a non-linear slope variably-controlled in accordance with the cumulative sum so as to reduce voltage fluctuation of the ramp signal due to load variation caused and depending on the number of analog switches turned off; a DA converter configured to convert the ramp signal data to the ramp signal as an analog signal and supply the ramp signal to the plurality of analog switches; and a delay section configured to delay the image data of the pixels of the one line and supply the delayed image data to the holding section in synchronization with the ramp signal outputted from the DA converter.
A description is given of an embodiment with reference to the drawings.
An image display apparatus 100 according to the embodiment is a liquid crystal display apparatus used in a reflective liquid crystal projector or the like.
The image display apparatus 100 includes a conversion analog signal generator 101, a driving pulse generator 102, a shift resistor circuit 103, a one-line latch circuit 104, a gray-level counter 105, comparators 1061 to 106n, analog switches 1071 to 107n, a pixel section 108, and a vertical driving circuit 109.
The conversion analog signal generator 101 receives a digital video signal ID to be displayed, a vertical synchronization signal VD, a horizontal synchronization signal HD, and a clock CLK.
The conversion analog signal generator 101 performs predetermined processing described below to generate a display digital video signal SVD and a ramp signal VREF which are in synchronization.
The display digital video signal SVD is supplied to the shift resistor circuit 103, and the ramp signal VREF is supplied through a ramp signal line Ls to input terminals of the analog switches 1071 to 107n.
The ramp signal VREF is a sawtooth wave which gradually changes in level in the same period as one horizontal scanning period so as to start with one of either black or white levels and reach the other level just before the end of the horizontal scanning period.
The driving pulse generator 102 receives the vertical synchronization signal VD, horizontal synchronization signal HD, and clock CLK. The driving pulse generator 102 generates a driving signal synchronized with the display digital video signal SVD and ramp signal VREF and supplies the generated driving signal to the vertical driving circuit 109.
The shift resistor circuit 103 sequentially shifts the supplied display digital video signal SVD on a pixel-by-pixel basis. The one-line latch circuit 104 temporarily holds the digital video signal (hereinafter, also referred to as pixel data) outputted in parallel from the shift resistor circuit 103, on a line-by-line basis.
The shift resistor circuit 103 and one-line latch circuit 104 constitute a holding section to hold image data of pixels of a line in the display digital video signal SVD.
The gray-level counter 105 counts pulses of the clock CK with a predetermined frequency synchronized with the synchronization signal of the digital video signal ID and outputs counter value QD (referential gray-level data) which changes from the minimum to the maximum gray-level to be displayed and comes to the same value again in a one-line period.
The n comparators 1061 to 106n are provided corresponding to the n pixels arrayed in the horizontal direction of the pixel section 108. The n comparators 1061 to 106n compare the counter value QD of the gray-level counter 105 with respective n pieces of pixel data of each line from the one-line latch circuit 104 and output a matching pulse when the counter value QD matches the pixel data.
The analog switches 1071 to 107n are provided corresponding to the comparators 1061 to 106n and n pixels arrayed in the horizontal direction of the pixel section 108, respectively. At every horizontal scanning period, the analog switches 1071 to 107n are controlled and turned on simultaneously at the beginning of the horizontal scanning period, and each analog switch 1071 to 107n supplies the ramp signal VREF through corresponding data line D1 to Dn to m pixels arrayed in the vertical direction in the pixel section 108.
The pixel section 108 is composed of pixels arrayed in a two-dimensional matrix (n pixels in the horizontal direction of the screen by m pixels in the vertical direction: m rows by n columns).
In the pixel section 108, m pixels of each column (in the vertical direction) are connected to one of the n data lines D1 to Dn, and n pixels arrayed in each row (in the horizontal direction) are coupled to one of the m gate lines G1 to Gm.
That is, the pixel section 108 is composed of n×m pixels provided at intersections of the n data lines D1 to Dn and the m gate lines G1 to Gm.
Each pixel can be a pixel 110 configured as illustrated in
The data line D is any one of the data lines D1 to Dn of
In the pixel selection transistor Q, the gate is connected to the gate line G, the drain is connected to the data line D, and the source is connected to an ungrounded terminal of the signal holding capacitance Cs and a pixel driving electrode PE of the liquid crystal element 111.
The pixel 110 is selected when the pixel selection transistor Q is turned on by a pixel selection signal (a gate signal) inputted through the gate line G. The pixel 110 receives the ramp signal through the data line D connected to the corresponding one of the analog switches 1071 to 107n.
The pixel 110 is configured so that the ramp signal (or a DA-converted analog video signal) sampled when the analog switch is turned off is written and held in the signal holding capacitance Cs through the pixel selection transistor Q and is then applied to the pixel driving electrode PE of the liquid crystal element 111.
The liquid crystal element 111 as an example of the display elements has a structure in which a liquid crystal layer LCM is sandwiched between the pixel driving electrode PE and a common electrode (a transparent electrode) CE facing each other. To the common electrode CE, common voltage Vcom is applied.
The pixel driving electrode PE is driven with voltage corresponding to analog video signal voltage (the sampled ramp signal voltage herein) to control the light transmittance of the liquid crystal layer LCM. The liquid crystal element 111 thus displays video.
The vertical driving circuit 109 constitutes a vertical direction driver and receives the driving signal. The vertical driving circuit 109 supplies the pixel selection signal sequentially to the m gate lines, one gate line (G1 to Gm) per horizontal scanning period (1H), which is synchronized with the horizontal synchronization signal HD, to repeatedly select n pixels arrayed in the same row of the pixel section 108 at the same time. The vertical driving circuit 109 thereby selects all the pixels in one frame period.
Next, a description is given of the schematic operation of the image display apparatus 100 illustrated in
The conversion analog signal generator 101 generates the display digital video signal SVD illustrated in (b) of
The shift resistor circuit 103 sequentially shifts and loads the inputted display digital video signal SVD line by line based on shift clock SCLK illustrated in (c) of
When the shift resistor circuit 103 finishes loading part of the display digital video signal SVD corresponding to a line, the one-line latch circuit 104 temporarily holds n pieces of pixel data of the line which are outputted from the shift resistor circuit 103 in parallel as schematically illustrated in (d) of
The gray level counter 105 counts the pulses of the clock CK illustrated in (e) of
The comparators 1061 to 106n independently compare the pixel data supplied to the first data input terminals on a pixel-by-pixel basis with the counter value QD commonly supplied to the second data input terminals. When the pixel data matches the counter value QD, the comparator 1061 to 106n outputs a matching pulse.
The comparator 1061 to 106n supplies a matching pulse to the corresponding one of the analog switches 1071 to 107n to turn off the same.
The gray level counter 105 and comparators 1061 to 106n constitute an analog switch controller.
The analog switches 1071 to 107n receive switch start pulses illustrated in (g) of
The switch start pulses, clock CK, shift clock SCLK, ramp signal VREF are all synchronized with the horizontal synchronization signal HD.
Some of the analog switches 1071 to 107n are then turned off upon the matching pulses outputted from the comparators 1061 to 106n provided corresponding thereto.
(h) of
(h) of
As for the analog switch with the opening and closing timings illustrated in (h) of
The potentials of the data lines connected to the analog switches 1071 to 107n gradually increase with the inputted ramp signal VREF while the analog switches 1071 to 107n are on.
Once each analog switch is turned off, the analog switch remains turned off until the beginning of the next horizontal scanning period. Accordingly, the potential of the ramp signal VREF (indicated by white circles in (i) of
The sampled and held potential is held by the signal holding capacitance Cs of a pixel which is selected by the gate lines G1 to Gm among the m pixels arrayed in the vertical direction in the pixel section 108 and connected via the data line of interest.
The voltage of the ramp signal VREF held at this time corresponds to the pixel value (the gray level) of the pixel of interest in the digital video signal. That is, the pixel data of the inputted display digital video signal SVD is converted to the analog video signal, which is then stored in the signal holding capacitance Cs of the pixel of interest.
As described above, in each pixel, the voltage of the ramp signal VREF just before the corresponding one of the analog switches 1071 to 107n is turned off, is held by the signal holding capacitance Cs of the pixel until the next frame to drive the liquid crystal element of the pixel.
In the image display apparatus 100, the time when the analog switches 1071 to 107n are turned off, that is, the time when the voltage of the ramp signal is sampled and held, depends on the picture design of the video signal to be displayed. The analog switches 1071 and 107n are all turned off at the same time in some cases, or are turned off at different times in other cases.
The order that the analog switches 1071 to 107n are turned off is also not fixed. When the level of the inputted ramp signal VREF gradually changes from the black level (corresponding to 0% light transmittance of the liquid crystal layer) to the white level (corresponding to 100% light transmittance of the liquid crystal layer), the analog switches are turned off in ascending order of gray levels to be displayed by the pixels connected to the respective analog switches. The order of turning off the analog switches depends on each picture.
The image display apparatus 100 has features including good linearity due to the operation of the DA conversion using the ramp signal. The image display apparatus 100 includes the conversion analog signal generator 101 in order to reduce tonality degradation (waveform interference) due to voltage fluctuation of the ramp signal, which is caused by a load variation of the ramp signal data generator that dynamically changes on the basis of lines in the digital video signal for the display.
Next, a description is given of the configuration and operation of the conversion analog signal generator 101 in detail.
As illustrated in
The conversion analog signal generator 101 includes an odd-numbered line ramp signal data generator 201A, an even-numbered line ramp signal data generator 201B, a one-bit line counter 202, an address counter 203, a NOT circuit 204, an image data selector 211, a histogram value selector 212, a ramp signal data generator 213, and a DA converter 214.
The conversion analog signal generator 101 generates and outputs the display digital video signal SVD and ramp signal VREF.
The odd-numbered line ramp signal data generator 201A includes an odd-numbered one-line data memory 205a (hereinafter, referred to as a data memory 205a), an odd-numbered line histogram memory 206a (hereinafter, referred to as a histogram memory 206a), an AND circuit 207a, an adder 208a, a switch 209a, and an odd-numbered line accumulator 210a.
The histogram memory 206a is a histogram value output section configured to detect histogram values of respective gray levels of the image data of pixels in each odd-numbered line every horizontal scanning period and outputs histogram value data.
The even-numbered line ramp signal data generator 201B has the same configuration as that of the odd-numbered line ramp signal data generator 201A.
The even-numbered line ramp signal data generator 201B includes an even-numbered one-line data memory 205b (hereinafter, referred to as a data memory 205b), an even-numbered line histogram memory 206b (hereinafter, referred to as a histogram memory 206b), an AND circuit 207b, an adder 208b, a switch 209b, and an even-numbered line accumulator 210b.
The histogram memory 206b is a histogram value output section configured to detect histogram values of respective gray levels of the image data of pixels in each even-numbered line every horizontal scanning period and outputs histogram value data.
The data memories 205a and 205b and histogram memories 206a and 206b are dual port memories which independently enable reading and writing.
The processing is separately performed for odd-numbered lines and even-numbered lines because a one line period is required to generate a histogram. The histogram is not fixed during this period.
Specifically, while the histogram values are generated in one of the odd-numbered and even-numbered line processes, the histogram values are read in another process. These processes are alternated line by line.
The data memories 205a and 205b are used to accommodate the time delay corresponding to one line which is produced at the histogram generation.
The one-bit line counter 202 is supplied with the vertical synchronization signal VD illustrated in (b) of
As illustrated in (d) and (h) of
The one-bit line counter 202 supplies the determination signal LINE as a write enable signal to write enable terminals WE of the data memory 205a and histogram memory 206a.
The NOT circuit 204 reverses the polarity of the determination signal LINE, and supplies the obtained signal as a write enable signal to the write enable terminals WE of the data memory 205b and histogram memory 206b.
The AND circuit 207a supplies the AND of the determination signal LINE and the horizontal synchronization signal HD to clear terminals CLR of the histogram memory 206a and the odd-numbered line accumulator 210a as a clear signal.
The AND circuit 207b supplies the AND of the horizontal synchronization signal HD and the signal obtained by reversing the polarity of the determination signal LINE through the NOT circuit 204 to clear terminals CLR of the histogram memory 206b and the even-numbered line accumulator 210b as a clear signal.
The address counter 203 generates a counter value AC (schematically illustrated in (i) of
The address counter 203 supplies the generated counter value AC to write address terminals WADRS and read address terminals RADRS of the data memories 205a and 205b.
When the write enable signal is 1, the image data ID inputted to terminals WDATA is written in the data memories 205a and 205b. When the write enable signal is 0, the data memories 205a and 205b output the written image data ID from terminals RDATA.
The write enable signals supplied to the data memories 205a and 205b have polarities opposite to each other as described above and are set to 1 and 0 for odd-numbered and even-numbered lines, respectively.
The image data of a certain odd-numbered line is written in the data memory 205a and is then outputted from the data memory 205a during the input period of the next even-numbered line as schematically illustrated in (j) of
The image data of a certain even-numbered line is written in the data memory 205b and is then outputted from the data memory 205b during the next period to input an odd-numbered line as schematically illustrated in (n) of
When the determination signal LINE supplied to a select terminal SEL is 0, the image data selector 211 selects and outputs odd-numbered line image data ID_ODD which is read from the data memory 205a and supplied to a terminal A.
When the determination signal LINE is 1, the image data selector 211 selects and outputs even-numbered line image data ID_EVEN which is outputted from the data memory 205b and supplied to a terminal B.
The image data selector 211 thereby selects image data of an even-numbered line during each odd-numbered line input period of the input image data ID and selects image data of an odd-numbered line during each even-numbered line input period as schematically illustrated in (q).
The image data selector 211 supplies the selected image data to the shift resistor circuit 103 (
The data memories 205a and 205b and image data selector 211 constitute a one-line delay circuit (a delay section) and has a function of selectively outputting one of odd-numbered and even-numbered lines.
In synchronization with the ramp signal VREF outputted from the DA converter 214, the delay section composed of the data memories 205a and 205b and image data selector 211 delays image data of pixels of each line and supplies the same to the holding section composed of the shift resistor circuit 103 and one-line latch circuit 104.
In the histogram memory 206a, the histogram for a certain line is written during the period when the image data of an odd-numbered line is written in the data memory 205a. In the histogram memory 206b, the histogram for a certain line is written during the period when the image data of an even-numbered line is written in the data memory 205b.
The adders 208a and 208b add 1 to read data outputted from terminals RDATA of the histogram memories 206a and 206b and supplies the results to terminals WDATA of the same, respectively.
Specifically, the histogram memories 206a and 206b generate histogram values in the following manner: the input image data ID is supplied to the write address terminals WADRS; and the values obtained by adding 1 to the read data from the histogram memories 206a and 206b through the adders 208a and 208b are written in the histogram memories 206a and 206b.
The read data from the histogram memories 206a and 206b are values stored at addresses corresponding to the gray levels of pixels in the input image data ID which are supplied to the write address terminals WADRS.
Before histogram values for a certain line are written in the histogram memories 206a and 206b, all of the histogram values of another line previously stored in the histogram memories 206a and 206b are cleared by clear signals.
The read address terminals RADRS of the histogram memories 206a and 206b are supplied with read address signals having opposite truth values through switches 209a and 209b, and reading operation for the histogram memories 206a and 206b is performed for each line which is not subjected to writing operation.
The odd-numbered line accumulator 210a accumulates plural histogram values HISTD_ODD of each odd-numbered line as schematically illustrated in (k) of
The odd-numbered line accumulator 210a outputs a calculated cumulative sum HISTADD_ODD as schematically illustrated in (m) of
The even-numbered line accumulator 210b accumulates plural histogram values HISTD_EVEN of each even-numbered line as schematically illustrated in (o) of
The even-numbered accumulator 210b outputs a calculated cumulative value HISTADD_EVEN as schematically illustrated in (p) of
When the determination signal LINE supplied to a select terminal SEL of the histogram value selector 212 is 0, the histogram value selector 212 selects and outputs the cumulative value HISTADD_ODD for each odd-numbered line which is read from the odd-numbered line accumulator 210a and is supplied to a terminal A (illustrated (m) of
When the determination signal LINE is 1, the histogram value selector 212 selects and outputs the cumulative value HISTADD_EVEN for even-numbered lines which is read from the even-numbered line accumulator 210b and is supplied to a terminal B (illustrated (p) of
The histogram value selector 212 outputs histogram value data HISTD that represents histogram values for the same line as the line the image data of which is outputted from the image data selector 211 as schematically illustrated in (r) of
In (r) of
Next, a description is given of the operations of the histogram memories 206a and 206b, and odd-numbered and even-numbered line accumulators 210a and 210b in more detail with reference to the timing diagram of
The input image data ID illustrated in (a) of
(d) of
As illustrated in (e) of
During each odd-numbered line image data input period when the determination signal LINE is 1, the histogram memory 206a generates a histogram of an odd-numbered line.
During the above input period, the determination signal LINE of 1 is inputted to the write enable terminal WE of the histogram memory 206a as the write enable signal as illustrated in (h) of
To the read address terminal RADRS of the histogram memory 206a, as schematically illustrated in (j) of
To the write address terminal WADRS of the histogram memory 206a, the pixel values of the input image data ID(11) as schematically illustrated in (i) of
The data read from the terminal RDATA of the histogram memory 206a represents the number of times that the write address inputted to the write address terminal WADRS is selected before the data is read as illustrated in (k) of
The write data written in the histogram memory 206a is the value obtained by adding 1 through the adder 208a to data which is read from the terminal RDATA and represents the number of times that the write address is selected.
Specifically, in the input image data ID(11), eight pixels carry pixel values (gray levels) of 2, 5, 3, 2, 7, 2, 5, and 3 as illustrated in (a) of
In the histogram memory 206a, the value obtained by adding 1 to the number of times written in the selected read and write addresses is written.
To the clear terminal CLR of the histogram memory 206a, the horizontal synchronization signal HD is inputted from the AND circuit 207a as the clear signal.
The data values (histogram values) written in the addresses 0 to 7 in the histogram memory 206a are cleared to 0 by the clear signal at each rising edge of the horizontal synchronization signal HD as illustrated in (g) of
The data values written in the addresses 0 to 7 in the histogram memory 206a are therefore 0 at first.
As illustrated in (k) of
As illustrated in (m) of
The data value read from the read address 2 corresponding to the subsequent fourth pixel value is “1” previously written and is then added with “1”. The result of addition “2” is overwritten to the address 2.
After data of all the pixels of the line is inputted, therefore, the data value written to the address 2 is “3”, the data values written to the addresses 3 and 5 are “2”, the data value written to the address 7 is “1”, and the data values written to the other addresses 0, 1, 4, and 6 are “0” as illustrated in (n) of
The histogram memory 206a therefore stores histogram values HISTD_Q which are frequencies of respective gray levels of eight pixels of each odd-numbered line. In the histogram memory 206a, the addresses represent the gray levels, and the data values written to the addresses are frequencies of the respective gray levels.
The histogram memory 206a thus generates the histogram values HISTD_ODD of respective gray levels of the input image data of each odd-numbered line when the determination signal LINE is 1.
Subsequently, during each even-numbered line image data input period when the determination signal L is 0, by the same operation as that of the histogram memory 206a described above, the histogram memory 206b generates the histogram values HISTD_EVEN of respective gray levels of the input image data of an even-numbered line.
At the same time, since the histogram memory 206a is not supplied with the write enable signal of 1, the histogram memory 206a performs only reading operation and correct load variation using the histogram values HISTD_ODD stored in the previous odd-numbered line image data input period.
During each even-numbered line image data input period, the switch 209a is switched and connected to a terminal 0. Accordingly, the terminal RADRS of the histogram memory 206a is supplied with the counter value AC illustrated in (e) of
The histogram memory 206a thereby uses the counter value AC, which counts in increments of 1, as the read address and the horizontal synchronization signal as the reset. As illustrated in (k) of
The histogram values HISTD_ODD of the gray levels “2”, “3”, “5”, and “7” read from the addresses 2, 3, 5, and 7 are 3, 2, 2, and 1, respectively. Moreover, the histogram values HISTD_ODD of the other gray levels “0”, “1”, “4”, and “6” are 0.
The histogram values are delayed by one line. Accordingly, the image data of the odd-numbered line corresponding to the above period is delayed by one line and outputted from the data memory 205a as ID_ODD.
To the terminal INDATA of the odd-numbered line accumulator 210a, the histogram values HISTD_ODD of the gray levels of each odd-numbered line read from the histogram memory 206a (illustrated in (k) of
Each cumulative sum HISTADD_ODD is the number s of analog switches which are turned off at the current time.
The gray levels (data levels) of input image data ID(11) during the odd-numbered line image data input period, histogram values HISTD_ODD, and cumulative sums HISTADD_ODD which are described above are summarized as illustrated in
During the image data input period of each even-numbered line, the same operation as that during each odd-numbered line image data input period is performed by the even-numbered line ramp signal data generator 201B. This operation is only shifted from the operation for the odd-numbered lines by the period 1H and can be easily known. The detailed description thereof is omitted.
The histogram memory 206b outputs the even-numbered line histogram values HISTD_EVEN, and the even-numbered line accumulator 210b outputs cumulative sums HISTADD_EVEN which indicate the number s of analog switches turned off at the process for each even-numbered line.
When the ramp signal is configured to change in level from the value corresponding to the lowest gray level to the value corresponding to the highest gray level value in each period 1H, the histogram memories 206a and 206b output histogram values in ascending order of gray levels in synchronization with the horizontal synchronization signal.
On the contrary, when the ramp signal has a waveform changing in level from the value corresponding to the highest gray level to the value corresponding to the lowest gray level value in the period 1H, the histogram memories 206a and 206b output histogram values in descending order of gray levels in synchronization with the horizontal synchronization signal.
In the following description, the ramp signal has the former waveform.
When the determination signal LINE supplied to a select terminal SEL is 0, the histogram value selector 212 illustrated in
During this period, the image data selector 211 outputs image data ID_ODD of the same odd-numbered line as schematically illustrated in (q) of
When the determination signal LINE supplied to the select terminal SEL is 1, the histogram value selector 212 selects the even-numbered line cumulative sums HISTADD_EVEN which are outputted from the even-numbered line accumulator 210b and are supplied to a terminal B and outputs the same as the histogram value data HISTD.
The ramp signal data generator 213 illustrated in
The ramp signal data generator 213 generates ramp signal data VREFD of digital values. The ramp signal is a sawtooth wave changing in level from the value corresponding to the minimum gray level at the beginning of the period ID to the maximum gray level right before the end of the period 1H. Moreover, the ramp wave has a non-linear slope variably controlled in accordance with the cumulative sums.
The DA converter 214 includes a buffer and converts the ramp signal data VREFD (digital signal) to the ramp signal VREF (analog signal) based on the clock CLK. The DA converter 214 supplies the ramp signal VREF to the analog switches 1071 to 107n through the ramp signal line Ls illustrated in
The ramp signal data generator 213 generates the digital ramp signal data VREFD having a non-linear slope variably controlled in accordance with the cumulative sums. The conversion analog signal generator 101 thereby reduces voltage fluctuation of the ramp signal due to load variation dynamically caused by the output impedance of the DA converter 214 and the input impedance represented by the analog switches 1071 to 107n.
The reduction of the changes in voltage of the ramp signal is concretely described below. The equivalent circuit of the circuit section including the DA converter 214 and analog switches 1071 to 107n is illustrated in
Load variation rate=V1(s)/V0=Z1/{(n−s)Z0+Z1} (2)
where Z1 is the input impedance of each analog switch 1071 to 107n illustrated in
In Equation (2), 0<=s<=n, and V0 is output voltage of the buffer of the DA converter 214. V1(s) is ramp signal voltage supplied from the DA converter 214 through the ramp signal line Ls to the n analog switches.
The smaller the number s of off analog switches, the lower the load variation rate. The aforementioned parameters are set for easy visual understanding and may be different from the actual parameters.
The load variation rate illustrated in
The ramp signal data generator 213 in the image display apparatus 100 generates the ramp signal data VREFD by multiplying the ramp signal by load variation correction data corresponding to the load variation rate (illustrated in
The ramp signal data VREFD is digital data, and when the ramp signal data VREFD is converted into the ramp signal VREF having an analog waveform, the ramp signal VREF is variably controlled in accordance with the histogram values and has a non-linear slope.
The load variation correction data illustrated in
Load Variation Correction Data={(n−s)Z0+Z1}/Z1 (3)
The load variation correction data is the reciprocal of the load variation rate expressed by Equation (2). The load variation correction data only needs to include data values allowing correction based on the load variation and is not limited to Equation (3).
In accordance with the image display apparatus 100 according to the embodiment, the aforementioned operation reduces grayscale degradation due to voltage fluctuation of the ramp signal VREF which is caused by load variation of the ramp signal data generator 213 that dynamically changes depending on the number of pixels carrying each gray level in each line of the display digital video signal.
Next, a description is given of the operation to generate the ramp signal data VREFD with the load variation of the ramp signal data generator 213 corrected more specifically in more detail with reference to
As illustrated in
In
The counter value QD represented by the horizontal axes in
In the case of not performing load variation correction, the ramp signal data generator 213 generates a ramp signal having a triangle waveform with the 1H period. The ramp signal linearly changes with time from 0 V representing the black level as the minimum gray level (corresponding to 0% light transmittance of the liquid crystal layer) to 1 V representing the white level as the maximum gray level (corresponding to 100% light transmittance of the liquid crystal layer) in the period 1H, and the waveform thereof has a linear slope.
In Equations (2) and (3), Z0=1, and Z1=100.
In the process of displaying any one line of the image 1c as the black background, all of the 256 pixels horizontally arranged have a gray level of 0, and all of the 256 analog switches corresponding to all the pixels horizontally arranged are simultaneously turned off when the counter value QD is 0.
The 256 analog switches then remain turned off during the period 1H in which the counter value QD changes to 255. The load variation rate F(255) in this process is 1 as illustrated in
Herein, the load variation rate F(255) is expressed by 100/{256−256}×1+100}. In the process of displaying any one line of the image 1C, there is no load variation, and the ramp signal data generator 213 generates the ramp signal data VREFD of a triangular waveform with the level linearly changing from 0 V to 1 V as the counter value QD changes as illustrated in
Next, in the process of displaying a line of the 50% gray image 2c having a shorter horizontal width, among 256 pixels in the line, 64 pixels are 50% gray, and the remaining 192 pixels are of the same gray level as the black background.
Accordingly, when the counter value QD is 0 just after the beginning of the horizontal scanning period, the 192 analog switches corresponding to the 192 pixels of the same gray level as the black background are simultaneously turned off, and the 64 analog switches corresponding to the 64 pixels remain turned on.
When the counter value QD becomes 128 indicating the gray level of 50%, the counter value QD matches pixel values of 50%. Upon the matching pulses outputted from the comparators 1061 to 106n, the remaining 64 analog switches are turned off, and 0.5 V of the ramp signal (the triangular waveform), that indicates the gray level of 50%, is sampled just before the analog switches are turned off. All the 256 analog switches are turned off at this time.
Accordingly, in the process of displaying the image 2c, as illustrated in
In
Accordingly, the ramp signal data generator 213 generates a load variation correction value H for correcting the load variation rate F(192) using Equation (3) and generates the ramp signal data VREFD having a slope changing as indicated by I in
When the counter value QD is from 128 to 255, the load variation rate F(255) is 1. Accordingly, the slope of the ramp signal data VREFD is 1 as indicated by II in
The ramp signal data generator 213 thus generates the ramp signal data VREFD having a non-liner slope illustrated in
Next, in the process of displaying each line of the 50% gray image 3c having a larger horizontal width, among 256 pixels in the line, 128 pixels are 50% gray, and the remaining 128 pixels are of the same gray level as the black background.
Accordingly, when the counter value QD is 0 just after the beginning of the horizontal scanning period, the 128 analog switches corresponding to the 128 pixels of the same gray level as the black background are simultaneously turned off, and the 128 analog switches corresponding to the other 128 pixels remain turned on.
When the counter value QD becomes 128 corresponding to a gray level of 50%, the counter value QD matches pixel values of 50%. Upon the matching pulses outputted from the comparators 1061 to 106n, the remaining 128 analog switches are turned off, and 0.5 V of the ramp signal (the triangular waveform) that indicates a gray level of 50%, is sampled just before the analog switches are turned off. All the 256 analog switches are turned off at this time.
Accordingly, in the process of displaying the image 3c, as illustrated in
In
Accordingly, the ramp signal data generator 213 generates the load variation correction value H for correcting the load variation rate F(192) using Equation (3) and generates the ramp signal data VREFD having a slope changing as indicated by III in
When the counter value QD is from 128 to 255, the load variation rate F(255) is 1. Accordingly, the ramp signal data VREFD has a slope of 1 as indicated by IV in
The ramp signal data generator 213 thus generates the ramp signal data VREFD having a non-liner slope illustrated in
In the embodiment, the ramp signal is generated based on the ramp signal data VREFD by correcting the load variation. Accordingly, compared with the conventional images 2b and 3b in the display image of
Next, a description is given of specific configuration examples of the ramp signal data generator 213 illustrated in
(First Configuration Example of Ramp Signal Generating Section)
The clock CLK is the clock illustrated in (e) of
The data generator 302 receives the histogram value data HISTD outputted from the histogram value selector 212 illustrated in
The data generator 302 can be composed of a look-up table (LUT). The histogram value data HISTD inputted as an address represents the number s of off analog switches for each value of the counter value QD. The data generator 302 can therefore generate the ramp signal data VREFD of a triangle wave having slope characteristics with the load variation corrected.
The data generator 302 stores ramp signal data (LUT data) including at least one of the following features: correction of the triangle waveform represented by the counter value QD; execution of de-gamma for display digital video signal; and to correction of the voltage-transmittance characteristics (VT characteristics) of liquid crystal elements.
The data generator 302 supplies the generated ramp signal data VREFD to the DA converter 214 illustrated in
When the load variation rate illustrated in
The ramp signal data generator 213A of the first configuration example is optimal for the case where the ramp signal needs to have non-linearity for degamma of the display digital video signal among monotonically increasing functions instead of using the gray level data constituting a simple triangle wave and the case where the VT characteristics of liquid crystal elements need to be corrected all at once.
Even when the analog switches 1071 to 107n vary in impedance and serve as a buffer load non-linear to the histogram values, the ramp signal data generator 213A of the first configuration example is adaptable to various cases by designing the LUT data to fit to the load characteristics of the analog switches 1071 to 107n.
The ramp signal data generator 213A can effectively prevent tonality degradation.
(Second Configuration Example of Ramp Signal Generating Section)
The load variation correction data generator 303 is composed of an LUT, for example. The load variation correction data generator 303 receives the histogram value data HISTD as an address. The load variation correction data generator 303 generates the load variation correction data having the characteristics illustrated in
The LUT constituting the load variation correction data generator 303 outputs the load variation correction data having data values corresponding to the number s of off analog switches indicated by the histogram value data HISTD inputted as the address.
The multiplier 304 multiplies the counter value QD from the counter 301 (the multiplied value) by the load variation correction data (the multiplying value) and supplies the result of multiplication to the DA converter 214 (
The ramp signal data VREFD represents a digital ramp signal of a sawtooth wave changing in level from a value corresponding to the minimum gray level at the beginning of each period 1H and having a value corresponding to the maximum gray level just before the end of the period 1H and has a non-linear slope variably controlled in accordance with the histogram value data HISTD.
The ramp signal data generator 213B of the second configuration example is effective when the number n of pixels horizontally arranged is not large and when the output impedance Z0 of the buffer within the DA converter 214 is small enough compared with the input impedance Z1 of the analog switches 107k to 107n (Z0<<Z1).
Moreover, since the ramp signal data generator 213B generates the ramp signal data VREFD using the multiplier 304 instead of the LUT, the ramp signal data generator 213B has a simple configuration and can provide the effect of reducing the load variation at a low cost.
(Third Configuration Example of Ramp Signal Generating Section)
A ramp signal data generator 213C illustrated in
The data generator 305 is composed of an LUT. The data generator 305 receives the counter value QD from the counter 301 as an address. The data generator 305 stores LUT data (correction data) for performing degamma processing for display digital video signal or correcting the VT characteristics of liquid crystal elements.
The multiplier 306 multiplies the LUT data from the data generator 305 (multiplied value) by the load variation correction data (multiplying value) and supplies the result of multiplication to the DA converter 214 (
The ramp signal data generator 213C is effective for the case of correcting the VT characteristic of liquid crystal elements, the case of performing degamma, and the case where the load variation is considered to be substantially linear to the number s of off analog switches.
The correction of the VT characteristic of liquid crystal elements and correction by degamma processing are generally non-linear to the grayscale. The ramp signal data generator 213C is effective in the case of requiring correction parameters and the case of properly changing the correction value (the degamma characteristic) for cancelling the signal gamma value that varies on video contents, such as 2.2, 1.8, and 2.6. An example of the correction parameters is a correction parameter concerning variation in liquid crystal film thickness in the manufacturing process. The liquid crystal film thickness varies between display elements.
The ramp signal data generator 213C performs the aforementioned correction in the data generator 305 and multiplies the LUT data outputted from the data generator 305 by the load variation correction data through the subsequent multiplier 306, thereby reducing the load variation.
According to the aforementioned configuration of the ramp signal data generator 213C, the memory size for the LUT can be significantly reduced, thereby reducing the cost and size of the image display apparatus.
According to the image display apparatus 100 of the embodiment described above, in an image display apparatus using a ramp signal for DA conversion, it is possible to precisely reduce the tonality degradation (waveform interference) due to voltage fluctuation in the ramp signal VREF which is caused by the load variation of the ramp signal data generator 213 dynamically changing in each line of the digital video signal for the display.
According to the image display apparatus 100 of the embodiment, by controlling the effect of reducing the tonality degradation in accordance with variation in analog switch characteristics of display elements, it is possible to implement high quality display excellent in tonality.
According to the image display apparatus 100 of the embodiment, it is not necessary to provide dummy pixels in the pixels. It is therefore possible to avoid yield reduction due to an increase in circuit scale and suppress an increase in cost.
The present invention is not limited to the above-described embodiment and can be modified in various ways. For example, the ramp signal may be composed of a sawtooth wave changing in level from the value corresponding to the maximum gray level to the value corresponding to the minimum gray level in each horizontal scanning period.
In this case, the counter value needs to be counted down from the value corresponding to the maximum gray level to the value corresponding to the minimum gray level.
As described above, according to the image display apparatus of the embodiment, it is possible to prevent tonality degradation (waveform interference) without providing dummy pixels and implement high-quality display with excellent tonality.
The present invention is applicable to an image display apparatus using other display elements similar to the liquid crystal display elements. The present invention is applicable to every image display apparatus that performs image display using DA conversion.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2013-193580 | Sep 2013 | JP | national |
This application is a Continuation of PCT Application No. PCT/JP2014/070724 filed on Aug. 6, 2014, and claims the priority of Japanese Patent Application No. 2013-193580 filed on Sep. 18, 2013; the entire contents of both of which are incorporated herein by reference.
| Number | Name | Date | Kind |
|---|---|---|---|
| 6950114 | Honda | Sep 2005 | B2 |
| 8212764 | Song | Jul 2012 | B2 |
| 20020145581 | Kudo | Oct 2002 | A1 |
| Number | Date | Country |
|---|---|---|
| 06-178238 | Jun 1994 | JP |
| H6-178238 | Jun 1994 | JP |
| 2011-013517 | Jan 2011 | JP |
| 2011-53644 | Mar 2011 | JP |
| 2013-525825 | Jun 2013 | JP |
| 2008056462 | May 2008 | WO |
| Entry |
|---|
| Official Action issued in corresponding Japanese application No. 2015-537597 dated Dec. 6, 2016. |
| Number | Date | Country | |
|---|---|---|---|
| 20160189643 A1 | Jun 2016 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/JP2014/007072 | Aug 2014 | US |
| Child | 15059724 | US |
