Patent Application
20060007211
1. Technical Field of the Invention
The present invention relates to an image display method and an apparatus therefore of a television image signal or the like. More particularly, the invention relates to an image display method and an apparatus therefore having a driving circuit permitting industrialization of a matrix image display panel at a low cost.
2. Description of the Related Art
Two kinds of electron emission element including a hot cathode element and a cold cathode element have conventionally known. Within the category of cold cathode element, for example, there are known an electric field emitting element (hereinafter referred to as the “FE type”), a metal/insulating layer/metal type emitting element (hereinafter referred to as the “MIM type”), and a surface conduction type emitting element.
Known examples of the FE type element include W. P. Dyke & W. W. Dolan, “Field emission”, Advance in Electron Physics, 8, 89 (1956), C. A. Spindt, “Physical properties of thin-film field emission cathodes with molybdenum cones”, J. Appl. Physics, 47, 5248 (1976).
Among MIM-type elements, C. A. Mead, “Operation of tunnel-emission devices, J. Appl. Phys., 32, 646 (1961) is known.
In the category of surface conduction type emission elements, for example, M. I. Elinson, Radio Eng. Electron Phys., 10, 1290 (1965) and other examples described later are known.
The surface conduction type emission element is based on the utilization of a phenomenon in which electron emission occurs by supplying current to a small-area thin film formed on a substrate in parallel with the film surface. Reported examples of surface conduction type emission element include one using an SnO2 thin film proposed by Elinson described above, one based on an Au thin film [G. Dittmer: “Thin Solid Films”, 9, 317 (1972)] one based on an In2O3/SnO2 [M. Hartwell], and C. G. Fonstad: “IEEE Trans. ED Conf.” 519 (1975)] and one based on a carbon thin film [H. Araki: Vacuum, vol. 26, no. 1, 22 (1983)].
As a typical element configuration of these surface conduction type emission elements, the plan view of the element proposed by M. Hartwell et al. described above is illustrated in
In the above-mentioned surface conduction type emission elements including that proposed by M. Hartwell and others, it is a common practice to form an electron emitting section 3005 by applying an energizing processing known as the energizing forming to the conductive thin film 3004 prior to electron emission. More specifically, energizing forming is defined as energizing the conductive thin film 3004 by applying a certain DC voltage or a DC voltage very slowly increasing at a rate of about 1 V/minute to the both ends of the film, causing a local breakage, deformation or deterioration of the conductive thin film 3004, thereby forming an electron emitting section 3005 in an electrically highly resistant state. Cracks occur partially in the locally broken, deformed or deteriorated conductive thin film 3004. When applying an appropriate voltage to the conductive thin film 3004 after the energizing forming, electrons are emitted near the cracks.
The above-mentioned surface conduction type emission elements have a simple structure, providing an advantage of permitting formation of many elements over a wide area. Thus, as disclosed by the present inventor in Japanese Patent Laid-Open No. 64-31332, a method for driving many elements by arrangement is studied.
Regarding applications of surface conduction type emission elements, research efforts have been made on image forming apparatuses such as image display apparatuses and image recording apparatuses, and charged beam sources.
Particularly, in the area of application to image display apparatuses, studies are made on image display apparatuses using a combination of the surface conduction type emission element and a fluorescent member emitting light by irradiation of electro beam, as is disclosed in U.S. Pat. No. 5,066,883 and Japanese Patent Laid-Open No. 2-257551 by the present inventor. The image display apparatus based on the combination of a surface conduction type emission element and a fluorescent member is expected to provide properties more excellent that those of the conventional image display apparatuses based on the other principles. For example, as compared with the liquid crystal display apparatuses having become more popular recently, it is more excellent in that it does not require backlight since it is of the spontaneous emitting type, and has a wider viewing angle.
3. Problems to be Solved by the Invention
The present inventor and others have tried surface conduction type emission elements of various materials, manufacturing processes and constructions including those described above as the prior art. In addition, the inventor and others have studied a multi-electron beam source in which a number of surface conduction type emission elements are arranged, and an image display apparatus based on the application of this multi-beam source.
The present inventor and others have tried, for example, a multi-electron beam source based on an electric wiring method shown in
In the drawing, reference numeral 4001 schematically represents a surface conduction type emission element as shown in
For the convenience of illustration, a 6×6 matrix is shown, but the scale of the matrix is not of course limited to this. For example, in the case of a multi-electron beam source for an image display apparatus, elements in a number sufficient to perform a desired image display are arranged and wired.
In a multi-electron beam source in which surface conduction type emission elements are simple-matrix-wired, an appropriate electric signal is applied to the row-direction wiring line 4002 and the column-direction wiring line 4003 to ensure desired electron beams. For example, in order to drive surface conduction type emission elements for an arbitrary line in the matrix, a selected voltage Vs is applied to the row-direction wiring line 4002 of the selected line, and simultaneously, a non-selected voltage Vns is applied to the non-selected row wiring line 4002. In synchronization with this, a driving voltage Ve for output of electron beams to the column-direction wiring line 4003 is applied. According to this method, when ignoring the voltage drop caused by the distribution resistances 4004 and 4005, a voltage Ve-Vs is applied to the surface conduction type emission elements of the selected line, and a voltage Ve-Vns is applied to the surface conduction type emission elements of the non-selected line. By selecting appropriate values for the individual voltages Ve, Vs and Vns, electron beams of a desired intensity should be outputted only from the surface conduction type emission elements of the selected line. By applying different driving voltages Ve to the different column-direction wiring lines, electron beams of different intensities should be outputted from each of the elements of the selected line. Since the response speed of the surface conduction type emission element is very high, it should be possible to change the length of time during which the electron beams are outputted by changing the length of time of application of the driving voltage Ve.
The multi-electron beam source in which surface conduction type emission elements are simple-matrix-wired is therefore widely applicable. For example, it is suitably applicable as an electron source for an image display apparatus by appropriately applying an electric signal corresponding to the image information.
However, problems described below have actually been encountered in the multi-electron beam source having simple-matrix-wired surface conduction type emission elements.
When using a multi-electron beam source having simple-matrix-wired surface conduction type emission elements as a large-area image display panel, many driving circuits are required and this has prevented smooth commercialization at low costs. Particularly, the display panel is long in the transverse direction, and RGB stripe arrangement is necessary, leading to the necessity of numerous driving circuits of column wiring line as compared with the number of driving circuits for the row wiring lines, this having also prevented low-cost commercialization.
In view of the above-mentioned problems, it is an object of the present invention to achieve a driving circuit of an image display apparatus with a modulated electron beam source, by low-cost and small-scaled hardware, particularly by a circuit configuration suitable for the tendency toward IC.
4. Means for Solving the Problems
The present invention provides an image display apparatus having a matrix image display panel, wherein the matrix image display panel comprises column wiring lines and row wiring lines, and a column wiring line driver and a row wiring line driver for driving electron emitting elements connected to these column wiring line and row wiring lines; the row wiring driver selectively and sequentially drives the row wiring lines at a horizontal synchronization timing; and the column wiring line driver has a shift register, a latch circuit, a pulse modulating circuit and a column wiring line driving circuit; wherein the shift register transfers image information sequentially, during the horizontal synchronization period, and after the completion of transfer, transfers the same in parallel with the latch circuit; the pulse width modulating circuit outputs modulation signals on the basis of the image information transferred in parallel; the column wiring driving circuit receives output modulated by the pulse width modulating circuit, and drives the electron emission elements connected to the column wiring lines; wherein an output circuit of the column wiring driving circuit comprises a complementary switching circuit (CMOS circuit) and has means for adjusting output impedance to the electron emission elements.
The present invention also provides an image display method which drives a matrix image display panel, wherein the matrix display panel has a row wiring line and a column wiring line, and a row wiring line driver and a column wiring line driver which drive electron emission elements connected to the column wiring line and the row wiring line; selects and drives the row wiring lines sequentially at horizontal synchronization timings by means of the row wiring line driver; sequentially transfers pieces of image information by means of the column wiring line driver within the horizontal synchronization period; transfers all the pieces of image information in parallel to a latch circuit after the completion of transfer; outputs a modulation signal through a pulse width modulating circuit on the basis of the image information transferred in parallel; receives the output of the signal modulated by the pulse width modulating circuit in a column wiring line driving circuit; and drives the electron emission element connected to the column wiring lines; and wherein the output circuit of the column wiring line driving circuit comprises a complementary switching circuit (CMOS circuit); and adjusts an output impedance to the electron emission element.
Embodiments of the present invention will now be described in detail with reference to the drawings.
A first embodiment will be described. The matrix image display panel used in the image display apparatus of the present invention comprises a multi-electron source having many electron sources such as cold cathode electron emission elements arranged on a substrate, and an image forming member which forms an image by irradiation of electron, arranged oppositely thereto.
Such cold cathode electron emission elements can be formed by accurately positioning on a substrate by using, for example, a manufacturing technology such as photolithographic etching. It is therefore possible to arrange many pieces at slight intervals. Furthermore, as compared with hot cathode conventionally used in CRTs, the cathode itself or surroundings thereof can be driven in a relatively low-temperature state. A multi-electron source can therefore easily be achieved with a smaller arrangement pitch.
In this embodiment of the present invention, the driving method of the matrix image display panel using surface conduction type elements as an electron source will be described.
The embodiment of the present invention will now be described with reference to the drawings.
In
In this embodiment, a case of application where a television image corresponding to a television signal NTSC (National Television System Committee) method is displayed on a display panel having a number of pixels comprising horizontally 240 (RGB trio)*vertically 240 lines is shown below. An image signal having different resolution or frame rate such as a highly precise image of a high definition (HDTV: high definition television) system, or an output signal of a computer can well be coped with, not limited to NTSC, with substantially the same configuration.
P1 represents an NTSC-RGB decoder unit which receives an NTSC-system composite video input and outputs a PGB component. Within this unit of the NTSC-RGB decoder unit P1, a synchronization (SYNC) signal superposed on the input video signal is separated and outputted. Similarly, a color burst signal superposed on the input video signal is separated, and a clock (CLK) signal (CLK1) synchronized with the color burst signal is generated and outputted.
P2 represents a timing generating unit for generating subsequent timing signals necessary for converting an analog RGB signal decoded at the NTSC-RGB decoder unit P1 into a digital graduation signal for brightness-modulating the matrix image display panel P2000.
A clamp pulse for DC-regenerating an RGB analog signal from the NTSC-RGB decoder unit P1 at the analog processing units; a blanking pulse (BLK pulse) for adding a blank period to an RGB analog signal from the NTSC-RGB decoder unit P1 at the analog processing units P3; a detection pulse for detecting the level of an RGB analog signal at the video detecting unit P4 (not shown); a sample pulse (not shown) for converting an RGB analog signal into a digital signal at the A/D unit P6; and a RAM controller control signal necessary for the RAM controller P12 (not shown) to control the RAM P8, are generated within the timing generating unit P2.
Upon entering a CLK1, a self-running CLK signal (CLK2) synchronizing with CLLK1 by the PLL circuit in the timing generating unit P2, a synchronizing signal (SYNC2) generated on the basis of CLK2 within the timing generating unit P2, and self-running CLK2 generating means are provided. Thus, even when an input video signal is not present, CLK2 and SYNC2 which are reference signals can be generated. It is therefore possible to display an image by reading out image data of the RAM means P8.
Reference numeral P3 represents an analog processing unit provided for each of the output primary colors from P1, and mainly performs the following operations. It receives a clamp pulse from the timing generating unit and conducts DC regeneration. It receives a BLK pulse from the timing generating unit P2 and adds a blanking period.
Upon receipt of a gain adjusting signal of the D/A unit P14 which is one of the control outputs of the system control unit composed centering around the MPU 11, it control the amplitude of primary color signals entered from P1.
It also receives an offset adjusting signal of the D/A unit P14 which is one of the control outputs of the system control unit composed around the MPU 11, and performs blank level control of primary color signals entered from P1.
Reference numeral LPFP5 represents prefilter means placed in the first stage of the A/D unit P6.
The A/D unit P6 receives a sample CLK from P2. It is A/D converter means which quantizes analog primary color signals having passed the LPFP5 with the necessary number of graduations.
The inverted γ table P7 is graduation converting means provided for converting an entered video signal into light emitting properties held by the display panel. When expressing a brightness graduation by the pulse width modulation as in this embodiment, a linear feature is often shown in that the amount of emitted light is substantially proportional to the magnitude of brightness data. On the other hand, a video signal processed in a TV image receiver using a CRT is subjected to a γ processing for correcting the non-liner light emitting property of the CRT. Therefore, when causing display of a TV image on a panel having linear light emitting properties as in this embodiment, it is necessary to cancel the effect of γ processing by graduation converting means such as P7.
It is also possible to change the light emitting properties into favorite ones by switching over the table data by means of the output of the I/O control unit P13 which is one of control input/output of a system control unit composed centering around the MPU P11.
Reference numeral P10 represents horizontal 1-line memory means provided for each primary color signal. It rearranges brightness data (image information) entered into the R, G and B systems in parallel into a sequence corresponding to the panel color arrangement, converts the same into a single-system serial signals, and outputs them to the X driver unit via latch means P22.
The system control unit mainly comprises an MPU P1, a serial communication I/F P16, an I/O control unit P13, a D/A unit P14, an A/D unit P15, a data memory P17, and user SW means P18.
The system control unit receives user requests from the user SW means P18 operated by the user or the serial communication I/F P16 receiving control signals operated by instruction by external communication, and achieves the request by outputting the corresponding control signal from the I/O control unit P13 or the D/A unit P14.
In this embodiment, a user request on variability of graduation, brightness, color control and other display control is achievable.
By providing a data memory P17, the amount of user adjustment can be stored.
Reference numeral P19 represents a Y-driver control timing generating unit, and P20, an X-driver control timing generating unit. Both these units generate Y-driver control and X-driver control signals upon receipt of CLK1, CLK2 and SYNC2 signals.
P21 represents a control unit for timing control of the line memory P10, and generates, upon receipt of CLK2 and SYNC2 signals, R, G and B WRT control signals for writing brightness data (image information) into the line memory, and R, G and B RD control signals for reading out brightness data (image information) in a sequence corresponding to the panel color arrangement from the line memory.
T104 shown in
P22 represents latching means. This latches an output of the line memory P10 with a slight clock, and synchronizes the data output timing with a desired time.
P1001 represents an X, Y driver timing generating unit. Upon receipt of control signals from the Y-driver control timing generating unit P19 and the X-driver control timing generating unit, it outputs the following signals for X-driver control: a shift clock which sequentially transfers brightness data trains (image information) entered into the shift register circuit P101a; an LD pulse which latches the data transferred by the shift register circuit P1101a in parallel to the latching circuit P1101b (and an LD pulse serving as a trigger for the horizontal period of the PWM generator unit P1102), a shift lock of the horizontal period for operating the Y-shift register P1002 for Y-driver control, and a trigger signal of a vertical period for giving a row scanning starting trigger and outputted.
The shift register circuit P1101a reads in parallel brightness data trains (image information) of 720 column wiring lines for each horizontal period from the latching means P22 by a shift clock in synchronization with the brightness data such as T107 shown in
The PWM generator unit P1102 provided for each column wiring line receives brightness data (image information) from the latching circuit P1101b, and generates pulse signals having a pulse width proportional to the size of brightness data (image information) for each horizontal period with a waveform as shown by T10 in
P1104 represents a column wiring line driving circuit. Upon receipt of a pulse signal having a pulse width proportional to the size of the brightness data (image data) which is an output of the PWM generator unit P1102, it drives the column wiring line. T111 shown in
Details of the PWM generator unit P1102 and the column wiring line driving circuit P1104 are shown in
The Y-shift register unit P1002 receives a horizontal period shift clock from the X, Y driver timing generating unit P1001 and a vertical period trigger signal for giving a row scanning starting trigger, and outputs sequentially a selection signal for scanning the row wiring line to the pre-driver unit P1003 provided for each row wiring line.
The output unit which drives each row wiring line comprises, for example, FET means P1006, and another FET means P1004. The pre-driver unit P1003 is provided for driving this output unit with a good response. The FET means P1004 is switching means energized upon selecting a row which applies a −Vss potential from the constant-voltage regulator P1005 to the row wiring line upon selection. For example, in the case of the present invention, it takes a value of −10 [V]. The FET means P1006 is switching means energized upon non-selection of a row which drives the row wiring line at 0 [V], becoming the grounding potential upon non-selection. T112 shown in
The row wiring lines are sequentially scanned in the above-mentioned manner, and the pulse width is modulated by means of the corresponding image information. The column wiring lines are driven with a driving current value set at an optimum value for each surface conduction type electron emitting element, thus forming an image on the display panel P2000.
The PWM generator unit P1102 and the column wiring line driving circuit P1104 will now be described in detail. Details are illustrated in
In
P1104a represents a complementary switching circuit; and P1104b, a resistor of which the resistance value is determined by the display panel.
The complementary switching circuit P1104a is shown in detail in
In
In the above-mentioned configuration, for a high-level signal of a pulse width corresponding to the size of brightness data (image information) outputted by the PWM generation unit P1102, the logic level is reversed at the NOT circuit P1104c. The signal is again reverse-outputted by P-type MOSFET P1104d and the N-type MOSFET P1104e which are output circuits, and the source voltage is outputted. In the case of the present invention, upon IC conversion, a source voltage of 5 [V] permitting expectation of a high degree of integrity was used.
The value of the resistor P1104b in the column wiring line driving circuit P1104 is set as follows. By appropriately adjusting the value of this resistor P1104b, the output impedance to the column wiring line can be effectively set.
More specifically, a short period of time is set so as to satisfy the requirement for graduation of the pulse modulation. The capacity of the column wiring line, and other parameters are selected so that driving is possible at a frequency lower than the resonance frequency caused by inductance of the flexible substrate connecting the column wiring line, the display panel P2000 not shown and the column wiring line driving circuit P1104.
When driving the column wiring line with a driving waveform having further frequency components, resonance may occur (hereinafter referred to as “ringing”). In the worst case, ringing causes the driving voltage of the cold cathode element P2001 to surpass the maximum rating value of the element, and may even break the cold cathode element P2001.
For this display panel of about 10″, a value within a range from 100 [Ω] to 1 [kΩ] is optimum for the resistor P1104b. For a large-sized panel of over 30″, a value within a range from 500 [Ω] to 5 [kΩ] was optimum.
In the present invention, the resistor P1104b is arranged in series to the output of the complementary switching circuit P1104a. This may however be replaced by the ON resistance of the P-type MOSFET P1104d and the N-type MOSFET P1104e which are output circuits of the complementary switching circuit P1104a. In this case, the resistor P1104b can of course be deleted, and in addition, the P-type MOSSFET P1104d and the N-type MOSSFET P1104e can be downsized, thus permitting further reduction of area, i.e., cost reduction upon IC conversion.
A second embodiment of the present invention will now be described. In the second embodiment, the column wiring line driving circuit P1104 is different from that in the first embodiment. Since the other configurations are the same as in the first embodiment, description of the configurations other then the column wiring line driving circuit P1104 is omitted here.
The PWM generator unit P1102 and the column wiring line driving circuit P1104 are illustrated in detail in
In
In the column wiring line driving circuit P1104, P1104a represents a complementary switching circuit as in the first embodiment. P1104b represents a resistor for which a resistance value is determined so as to prevent occurrence of winging by the display panel P2000 as in the first embodiment. P1104f represents a switch circuit which is turned on or off through control input. P1106 represents an enable control circuit, comprising a latch circuit P1106a serving as an enable generator as shown in
In
As shown in
As in the first embodiment, a pulse width high-level signal proportional to the size of the brightness data (image information) outputted by the PWM generator unit P1102 is outputted. In a high-level signal, the logic level is reversed by the NOT circuit P1104c, reversed again and outputted by the P-type MOSFET P1104d and the N-type MOSFET P1104e which are output circuits, and a source voltage is outputted.
In the present invention, a source voltage of 5 [V] permitting expectation of a high degree of integrity in IC conversion is used.
In the above-mentioned configuration, the enable control circuit P1106 time-differentiate the output of the PWM generator unit P1102. More specifically, in the latch circuit P11006a, using PCLK as a clock, the PWM generator unit P1102 latches the output. The latched reversed output is reversed and outputted after exclusive OR of the output of the PWM generator unit P1102 by the XNOR circuit P1106b. As a result, the enable control circuit P1106 low-level-outputs only rising and trailing of the output of the PWM generator unit P1102 as shown by T110a in
The value dependent on this resistor P1104b provides the following advantages in the following cases (1) and (2).
(1) Upon rising and trailing, the output of the enable control circuit P1106 is on a low level. As in the first embodiment, therefore, the resistor P1104b is placed in series between the complementary switching circuit P1104a and the column wiring line. The column wiring line can be driven without occurrence of ringing.
(2) Since the output of the enable control circuit P1106 is on a high level except upon rising and trailing, the resistor P1104b is short-circuited by the switching circuit P1104f, and the apparatus is less subjected to voltage drop or power loss. The image display panel P2000 could be driven satisfactorily without power loss more than in the first embodiment having shown a satisfactory operation.
The value of the resistor P1104b was selected so that no ringing occurs as in the first embodiment.
In a panel having a display panel of about 10″, a value within a range from 100 [Ω] to 1 [kΩ] was optimum. For a large-sized panel having a size larger than 30″, a value within a range from 500 [Ω] to 5 [kΩ] was optimum.
Ringing occurs when the driving waveform shows an abrupt change. In the second embodiment, in which the driving waveform is more gentle in correspondence only to rising and trailing, it is possible to drive the column wiring lines with a driving waveform free from ringing.
A third embodiment of the present invention will now be described. In the third embodiment, the column-direction column wiring line driving circuit P1104 for the display panel P2000 is different from that in the second embodiment. Since the other configuration is the same as in the second embodiment, description of the configuration other than that of the column wiring line driving circuit P1104 is omitted here.
The PWM generator unit P1102 and the column wiring line driving circuit P1104 of the third embodiment will be illustrated in detail in
In
In the column wiring line driving circuit P1104, P1104a represents a complementary switching circuit as in the first embodiment, and P1104b represents, as in the first embodiment, a resistor of which a resistance value depends upon the matrix display panel. P1104g represents a three-state control complementary switching circuit of which the output can be brought into a high impedance state by control input.
P1106 represents an enable control circuit which comprises a configuration as shown in
The three-state complementary switching circuit P1104g is illustrated in detail in
In
In
In the present invention, a source voltage of 5 [V] permitting expectation of a high degree of integration upon IC conversion was used.
In the above-mentioned configuration, the enable control circuit P1106 outputs a waveform resulting from the time differentiation of the output by the PWM generator unit P1102 as in the second embodiment. That is, in
The three-state complementary switching circuit P1104g is in a high-impedance state only when the output of the PWM generator unit P1102 is on a LOW level.
Since the complementary witching circuit P1104a and the three-state complementary switching circuit P1104g are connected in parallel,
(1) Upon raising and trailing, output of the enable control circuit P1106 is on a low level (because the enable input of the three-state complementary switching circuit P1104g is on a low level and the output of the three-state complementary switching circuit P1104g is of a high impedance). It is therefore possible to drive the column wiring line by means of the complementary switching circuit P1104a and the serial circuit of the resistance P1104b. It is thus possible to drive the column wiring line without occurrence of ringing.
(2) Furthermore, since at times other than rising and trailing times, the output of the enable control circuit P1106 is on a high level (as the enable input of the three-state complementary switching circuit P1104g is on a high level and the output of the three-state complementary switching circuit P1104g is valid), the column wiring lines are driven by the output impedance based on parallel connected of the complementary switching circuit P1104a and the three-state complementary switching circuit P1104g, thus leading to only slight voltage drop and power loss. These advantages are available. The image display panel P2000 could be driven more satisfactorily than in the first embodiment showing a good operation.
In a panel of about 10″, as in the first embodiment, a value of the resistor P1104b within a range from 100 [Ω]to 1 [kΩ] was optimum. For a large-sized panel larger than 30″, a value within a range from 500 [Ω] to 5 [Ω] was optimum.
In the present invention, the resistor P1104b is arranged in series with the output of the complementary switching circuit P1104a. This may be replaced by an ON resistance of the P-type MOSFET P1104d and the N-type MOSFET P1104e which are output circuits of the complementary switching circuit P1104a. In this case, it is of course possible to delete the resistor P1104b, and downsize the P-type MOSFET P11104d and the N-type MOSFET P1104e, thus permitting further reduction of area, i.e., cost reduction upon IC conversion.
A fourth embodiment of the present invention will now be described. In the fourth embodiment, column wiring line driving circuit P1104 in the column direction for the display panel P2000 is different from that in the third embodiment. Since the other configuration is the same, the description of the configuration other than the column wiring line driving circuit P1104 is omitted here.
The PWM generator unit P1102 and the column wiring line driving circuit P1104 are shown in detail in
In
In the column wiring line driving circuit P1104, reference numerals P1104g1 and P1104g2 represent three-state complementary switching circuits which can bring the output to a high impedance state by a control input. Since the details of the three-state complementary switching circuits P1104g1 and P1104g2 have the same configuration as the three-state complementary switching circuit P1104g described in
P1104b represents a resistor having a resistance value determined by the same matrix display panel as in the first embodiment.
P1106 represents an enable control circuit which comprises a configuration as shown in
The output of the enable control circuit P1106 is such that, in
In
In the present invention, a source voltage of 5 [V] permitting expectation of a high degree of integration upon IC conversion is used.
In the above-mentioned configuration, the enable control circuit P1106 time-differentiates the output of the PWM generator unit P1102. That is, PCLK is used as a clock at the latch circuit P1106a; the PWM generator unit P1102 latches the output; and after exclusive OR by the XOR circuit P1106c of the output, the latched reverse output and the PWM generator unit P1102 outputs the same (T110b). The NOT circuit P1106d reverse-outputs this output (T110a). As a result, as shown in
(1) Upon rising and trailing, the enable control circuit P1106 outputs a high-level enable signal to the three-state complementary switching circuit P1104g1, and a low-level enable signal to the three-state complementary switching circuit P1104g2, respectively. As a result, the three-state complementary switching circuit P1104g2 gives a high-impedance output and does not exert an influence on the column wiring line driving. On the other hand, the three-state complementary switching circuit P1104g1 outputs the output of the PWM generator unit P1102 as it is.
Since a resistance P1104b is connected in series between the three-state complementary switching circuit P1104g1 and the column wiring line, the column wiring line can be driven with a driving waveform free from ringing.
(2) At other times than rising and trailing, the enable control circuit P1106 outputs a low-level enable signal to the three-state complementary switching circuit P1104g1, and a high-level enable signal to the three-state complementary switching circuit P1104g2, respectively. As a result, the three-state complementary switching circuit P1104g1 gives a high-impedance output, and does not exert an influence on the column wiring line driving. On the other hand, the three-state complementary switching circuit P1104g2 outputs the output of the PWM generator unit P1102 as it is. By this output, the three-state complementary switching circuit P1104g2 drives the column wiring line at a low impedance, leading to such advantages as slight voltage drop and power loss. The image display panel P2000 could be driven satisfactorily more than the first embodiment which was satisfactory.
For a display panel of about 10″, a value of the resistor P1104b within a range from 100 [Ω] to 1 [kΩ] was optimum. For a large-sized panel larger than 30″, a value within a range from 500 [Ω] to 5 [kΩ] was optimum.
In the present invention, the resistor P1104b is arranged in series with the output of the complementary switching circuit P1104a. This may be replaced by an ON resistance of the P-type MOSFET P1104d and the N-type MOSFET P1104e which are output circuits of the complementary switching circuit P1104a. In this case, the resistor P104b can of course be deleted, and the P-type MOSFET P1104d and the N-type MOSFET P1104e can be downsized, thus permitting achievement of further reduction of the area, i.e., reduction of cost upon IC conversion.
A fifth embodiment of the present invention will now be described. In the fifth embodiment, three or more three-state complementary switching circuits are connected in parallel in the fourth embodiment.
In
In the column wiring line driving circuit P1104, reference numeral P1104a represents a complementary switching circuit as in the first embodiment, and P1104b1, a first resistor of which a resistance value is determined by the matrix display panel as in the first embodiment. P1104g1 represents a three-state complementary switching circuit of which the output can be brought into a high-impedance state by enable input. P1104b2 represents a second resistor of which the resistance value is determined by the matrix display panel, as in the first embodiment.
P1104g2 represents a three-state complementary switching circuit of which the output can be brought into a high0impedance state by enable input.
P1106 represents an enable control circuit which outputs two kinds of enable outputs including T110c and T110d shown in
The output of the enable control circuit P1106, as shown by T110c and T110d in
The low level period of T110c and T110d has a relationship T110c<T110d.
Detailed description of the complementary switching circuit P1104a, and the three-state complementary switching circuit P1104g1 and P1104g2 is omitted here, being the same as in the above-mentioned embodiments.
In the present invention, a source voltage of 5 [V] permitting expectation of a high degree of integration upon IC conversion. This embodiment provides the following advantages (1) and (2).
(1) Upon rising and trailing (i), both outputs of the enable control circuit P1106 (both T110c and T110d) are on a low-level (enable input of the three-state complementary switching circuits P1104g1 and P1104g2 are on a low level, and outputs of the three-state complementary switching circuits P1104g1 and P111104g2 show a high impedance). The column wiring line can therefore be driven by the serial circuit of the complementary switching circuit P1104a and the resistor P1104b1, thus permitting driving of the column wiring line without occurrence of ringing.
(2) Upon rising and trailing (ii), and further, after the lapse of a time, output T110c of the enable control circuit P1106 is on a low level and output 110d thereof is on a high level (since the enable input of the three-state complementary switching circuit P1104g1 is on a high level, and the output of the three-state complementary switching circuit P110g2 is valid). Therefore, the output impedance is substantially equal to the parallel-connection value of the resistor P1104b1 and the resistor P1104b2, and this is sufficient to drive the column wiring line. It is therefore possible to drive the column wiring line without occurrence of ringing without slowing down the rising (trailing) waveform too much when the potential difference between the source voltage and the column wiring line voltage is reduced.
(3) At times other than rising and trailing, outputs of the enable control circuit P1106 (T110c, T110d) are on a high level (because the enable input of the three-state complementary switching circuits P1104g1 and P1104g2 is on a high level, and the output of the three-state complementary switching circuits P1104g1 and P1104g2 is valid). The column wiring line is driven by means of a parallel-connection circuit of the complementary switching circuit P1104a and the three-state complementary switching circuits P1104g1 and P1104g2, i.e., the column wiring line is driven by the output of the three-state complementary switching circuit P1104g2, thus resulting in such advantages as reduced voltage drop and power loss. The image display panel P2000 could thus be driven more satisfactorily than in the fourth embodiment showing satisfactory operation.
For the resistor P1104b1, a value within a range from 100 [Ω] to 2 [kΩ] was optimum for a panel of about 10″ as in the first embodiment. For a large-sized panel larger than 30″, a value within a range from 500 [Ω] to 10 [kΩ] was optimum.
A value of the resistor P1104b2 within a range from 20 [Ω] to 1 [kΩ] was optimum for a display panel of about 10″. For a large-sized panel of over 30″, a value within a range from 100 [Ω] to 5 [kΩ] was optimum.
In the present invention, the resistor P1104b1 is arranged in series with the output of the complementary switching circuit P1104a. This may however be replaced by an ON resistance of the P-type MOSFET P1104d and M-type MOSFET P1104e which are output circuits of the complementary switching circuit P1104a. Moreover, the resistor P1104b2 may be replaced by an ON resistance of a P-type MOSFET P1104k and an N-type MOSFET P1104m which are output circuits of the three-state complementary switching circuit P1104g1. In this case, the resistors P1104b1 and P1104b2 can be of course deleted, and further, the P-type MOSFETs P11042 and P1104k, and the N-type MOSFETs P1104e and P1104m can be downsized, thus permitting reduction of area, hence cost reduction upon IC conversion.
In
The functions of various parts and components will now be described along the flow of image signals.
The TV signal receiving circuit 2113 is a circuit for receiving TV image signals transmitted by the use of a radio transmission system such as electromagnetic waves or space optical communication. The type of TV signals received is not limited to a particular one but may be any of various types including, for example, NTSC, PAL, and SECAM. TV signals comprising more scanning lines than those described above (including so-called high-definition TV such as MUSE method) are signal sources suitable for effective use of advantages of the above-mentioned display panel well adaptable to achievement of a larger area and increase in the number of pixels. TV signals received by the TV signal receiving circuit 2113 are outputted to the decoder 2104.
The TV signal receiving circuit 2112 is a circuit for receiving TV image signals transmitted by means of a CATV system such as a coaxial cable or an optical fiber. As in the above-mentioned TV signal receiving circuit 2113, the type of received TV signals is not limited to a particular one, and TV signals received by this circuit are also outputted to the decoder 2104.
The image input interface circuit 2111 is a circuit for incorporating image signals supplied from image input apparatuses such as a TV camera and an image reading scanner. Image signals incorporated are outputted to the decoder 2104.
The image memory interface circuit 2110 is a circuit for incorporating image signals stored in a video tape recorder (hereinafter abbreviated as a “VTR”), and the incorporated image signals are outputted to the decoder 2104.
The image memory interface circuit 2109 is a circuit for incorporating image signals stored in the video disk, and the incorporated image signals are outputted to the decoder 2104.
The image interface circuit 2108 is a circuit for incorporating image signals from the apparatus storing still image data as in a still image disk, and the incorporated still image data are outputted to the decoder 2104.
The input/output interface circuit 2105 is a circuit for connecting this display apparatus to an external computer or a computer network or an output unit such as a printer. It conducts input/output of image data or characters or graphic information and in some cases, can perform input/output control signals and numerical data between the CPU 2106 provided in this display apparatus and an external device.
The image generating circuit 2107 is a circuit for generating image data or character and graphic information entered from outside via the above-mentioned input-output interface circuit 2105, or image data and character and graphic information outputted from the CPU 2106. In this circuit, there are incorporated a rewritable memory for storing image data or character and graphic information, a read-only memory storing image patterns corresponding to character codes, and circuits necessary for generating images including processors for carrying out image processing. The image data for display generated by this circuit are outputted to the decoder 2104, and as required, can be outputted to an external computer network or a printer via the above-mentioned input/output interface circuit 2105.
The CPU 2106 carries out mainly operational control of this display apparatus and operations relating to generation, selection or edition of displayed images.
For example, the CPU outputs control signals to the multiplexer 2103, and appropriately selects or combines image signals to be displayed on the display panel. It generates control signals to the display panel controller 2102 in response to the image signals to be displayed, and appropriately controls operations of the display apparatus such as the screen display frequency, the scanning method (for example, interlace or non-interlace), or the number of scanning lines per screen. It directly outputs image or character and graphic information to the image generating circuit 2107, or accesses an external computer or a memory via the input/output interface circuit 2105 to enter image data or character or graphic information.
The CPU 2106 may if course be engaged in operation for other purposes. For example, it may directly participate in functions generating or processing information as a personal computer or a wordprocessor.
It may perform such operations as numerical calculation in cooperation with an external device through connection with an external computer network via the input/output interface 2105 as described above.
The input unit 2114 is for the user to enter an instruction, a program or data into the CPU 2106, and it is possible to use various input devices such as a joy stick, a barcode reader and voice recognizer, in addition to a keyboard and a mouse.
The decoder 2104 is a circuit for reverse-converting various image signals entered from above-mentioned 2107 to 2113 into three primary color signals, or a brightness signal and an I-signal or a Q-signal. As shown by a dotted line in this drawing, the decoder 2104 should preferably have an image memory in the interior. This is to handle TV signals requiring an image memory upon reverse-converting as in the MUSE method. By having an image memory, display of a still image becomes easier. Another advantage is that image processing or edition including thinning, interpolation, enlargement, size reduction and synthesis of images becomes easier in cooperation with the image generating circuit 2107 and the CPU 2106.
The multiplexer 2103 appropriately selects displayed images in accordance with a control signal control from the CPU 2106. More specifically, the multiplexer 2103 selects desired image signals from among reverse-converted image signals entered from the decoder, and enters the selected image signal to the driving circuit 2101. In this case, it is possible to divide a screen into a plurality of regions to display different images as in the so-called multi-screen television set by selecting while switching image signals within a screen display time.
The display panel controller 2102 is a circuit for controlling the operation of the driving circuit 2101 on the basis of control signals entered from the CPU 2106.
Regarding the basic operations of the display panel 2100, for example, it outputs signals for controlling the operating sequence of the driving power supply (not shown) of the display panel 2100 to the driving circuit 2101.
Regarding the driving method of the display panel 2100, it outputs signals for controlling the image display frequency or the scanning method (for example, interlace or non-interlace) to the driving circuit 2101.
As required, it may output control signals regarding adjustment of the image quality such as brightness of the displayed image, contrast, color tone and sharpness, to the driving circuit 2101.
The driving circuit 2101 is a circuit for generating driving signals to be applied to the display panel 2100, and operates on the basis of an image signal entered from the multiplexer 2103 and a control signal entered from the display panel controller 2102.
The functions of the parts and components have been described above. Under the effect of the typical configuration shown in
More specifically, various image signals including those of television broadcasting are reversely converted in the decoder 2104, then, appropriately selected at the multiplexer 2103, and are entered into the driving circuit 2101. On the other hand, the display controller 2102 generates control signals for controlling operations of the driving circuit 2101 in response to the image signal to be displayed. The driving circuit 2101 applies a driving signal to the display panel 2100 on the basis of the image signal and the control signal.
As a result, an image is displayed on the display panel 2100. These series of operations are comprehensively controlled by the CPU 2106.
In this display apparatus, an image selected from among a plurality of pieces of image information is displayed by the participation of the image memory built in the decoder 2104, and image generating circuit 2107 and the CPU 2106. Furthermore, it is possible to apply image processing operations including enlargement, reduction, turning, moving, edge enhancement, thinning, interpolation, color conversion, and change of aspect ratio of image, and image editing operations such as synthesis, erasure, connection, replacement, and fitting. Although it has not been specifically pointed out in the description of the embodiments, special circuits for processing or edition also for audio information may be provided.
This display apparatus can have in a single machine functions of a display device for television broadcasting, a terminal machine for TV conference, an image editing device handling still images and animations, a terminal device of a computer, a word processor and other office terminals, and a game machine, and is very widely applicable for industrial and non-industrial purposes.
The above-mentioned
In this display apparatus, it is possible to reduce the depth of the entire apparatus since the display panel having surface conduction type emission elements as an electron beam source can be made thinner. In addition, the display panel having surface conduction type emission elements as an electron beam source can easily have a larger screen, with a high brightness and excellent viewing angle properties. This display apparatus can therefore display a powerful image rich in feeling of presence with a high visual recognizability.
As described above, in the image display apparatus of the present invention, i.e., in the apparatus having a matrix image display panel having column and row wiring lines, a row wiring line driver and a column wiring line driver which drive the column wiring lines and the row wiring lines, the row wiring line driver sequentially selects and drives the row wiring lines at a horizontal synchronization timing. In this case, the column wiring line driver has a shift register, a latch circuit, a pulse width modulating circuit, and a column wiring line driving circuit. Within the horizontal synchronization period, the shift register sequentially transfers pieces of image information. After the completion of transfer, the image information is transferred in parallel with the latch circuit, and the pulse width modulating circuit outputs a modulation signal on the basis of the image information transferred in parallel. Upon receipt of output of the modulation signal modulated by the pulse width modulating circuit, the column wiring line driving circuit drives the column wiring line. The output circuit of the column wiring line driving circuit comprises a complementary switching circuit (CMOS circuit), thus having means for adjusting the output impedance. As a result, when using a multi-electron beam source in which surface conduction type emission elements are simple-matrix wired as a large-area image display panel, the column wiring line driving circuit so far prevented smooth commercialization at a low cost can drive a large-area display panel at a low cost without the risk ringing.
In the conventional display apparatus, requiring a stripe arrangement, the number of driving circuits of column wiring lines has been very large as compared with the number of row wiring line driving circuits, and this prevented smooth commercialization at a low cost. According to the present invention, it is possible to achieve a high degree of integration, particularly upon IC conversion, of the driving circuits of the image display apparatus of modulating the electron beam source.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2001-237027 | Aug 2001 | JP | national |
| 2002-118296 | Apr 2002 | JP | national |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 10211521 | Aug 2002 | US |
| Child | 11128345 | May 2005 | US |
