IMAGE DISPLAY DEVICE

Abstract

An image display device includes a liquid crystal display part, a gate line driving circuit, a source line driving circuit, and a timing controller. The source line driving circuit includes a horizontal shift register, a first latch circuit, a second latch circuit, a D/A converter circuit, and a demultiplexer capable of driving a plurality of source lines divided into a plurality of batches. The timing controller includes a pulse generating circuit, a signal transmission circuit, and a shift pulse generating circuit for generating a second latch signal and for sending a shifted start signal back to the signal transmission circuit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an image display device according to a first preferred embodiment of the present invention;

FIG. 2 is a circuit diagram of a liquid crystal display part according to the first preferred embodiment of the present invention;

FIG. 3 is a circuit diagram of a source line driving circuit according to the first preferred embodiment of the present invention;

FIG. 4 is a circuit diagram of a horizontal shift register according to the first preferred embodiment of the present invention;

FIG. 5 is a circuit diagram of a demultiplexer according to the first preferred embodiment of the present invention;

FIG. 6 is a block diagram of a timing controller according to the first preferred embodiment of the present invention;

FIG. 7 is a block diagram of an STX and second latch signal generating circuit according to the first preferred embodiment of the present invention;

FIG. 8 is a circuit diagram of the STX and second latch signal generating circuit according to the first preferred embodiment of the present invention;

FIG. 9 is a timing chart of the image display device according to the first preferred embodiment of the present invention;

FIG. 10 is a block diagram of the image display device according to a second preferred embodiment of the present invention;

FIG. 11 is a block diagram of the timing controller according to the second preferred embodiment of the present invention;

FIG. 12 is a circuit diagram of a horizontal shift register according to the second preferred embodiment of the present invention;

FIG. 13 is a circuit diagram of a delay flip-flop according to the present invention; and

FIG. 14 is a circuit diagram of a delay latch circuit according to the present invention.

Claims

1. An image display device comprising: a display part provided with a plurality of source lines arranged in a row and a plurality of gate lines arranged in a column, said display part including a pixel transistor formed near each intersection of said source lines and said gate lines;a gate line driving circuit for driving said gate lines;a source line driving circuit for driving said source lines; anda timing controller for controlling timings of said gate line driving circuit and said source line driving circuit,said source line driving circuit includinga horizontal shift register for generating a first latch signal for latching gray scale data,a plurality of first latch circuits for latching said gray scale data, based on said first latch signal from said horizontal shift register,a plurality of second latch circuits provided in corresponding relation to said plurality of first latch circuits, respectively, for latching first latch data latched by said plurality of first latch circuits simultaneously,a plurality of D/A converter circuits for converting second latch data latched by said plurality of second latch circuits into an analog gray scale voltage, anda demultiplexer for switching the supply of said analog gray scale voltage from said plurality of D/A converter circuits to said source lines so that said plurality of source lines divided into a plurality of batches are driven,said timing controller includinga pulse generating circuit for generating a start signal for said horizontal shift register from a horizontal synchronization signal,a signal transmission circuit for controlling transmission of said start signal, based on said horizontal synchronization signal, anda shift pulse generating circuit for shifting said start signal for a predetermined length of time to generate a second latch signal for controlling said plurality of second latch circuits and to send said shifted start signal back to said signal transmission circuit.

2. An image display device comprising: a display part provided with a plurality of source lines arranged in a row and a plurality of gate lines arranged in a column, said display part including a pixel transistor formed near each intersection of said source lines and said gate lines;a gate line driving circuit for driving said gate lines;a source line driving circuit for driving said source lines; anda timing controller for controlling timings of said gate line driving circuit and said source line driving circuit,said source line driving circuit includinga horizontal shift register for generating a first latch signal for latching gray scale data,a plurality of first latch circuits for latching said gray scale data, based on said first latch signal from said horizontal shift register,a plurality of second latch circuits provided in corresponding relation to said plurality of first latch circuits, respectively, for latching first latch data latched by said plurality of first latch circuits simultaneously,a plurality of D/A converter circuits for converting second latch data latched by said plurality of second latch circuits into an analog gray scale voltage, anda demultiplexer for switching the supply of said analog gray scale voltage from said plurality of D/A converter circuits to said source lines so that said plurality of source lines divided into a plurality of batches are driven,said timing controller includinga pulse generating circuit for generating a start signal for said horizontal shift register from a horizontal synchronization signal,said horizontal shift register includinga signal transmission circuit for controlling transmission of said start signal, based on said horizontal synchronization signal, anda circuit part for shifting said start signal for a predetermined length of time to generate said first latch signal for latching said gray scale data and a second latch signal for controlling said plurality of second latch circuits and to send said shifted start signal back to said signal transmission circuit.

3. The image display device according to claim 1, wherein said signal transmission circuit is a signal switching circuit having a switch function such that opening and closing thereof are controlled based on said horizontal synchronization signal.

4. The image display device according to claim 2, wherein said signal transmission circuit is a signal switching circuit having a switch function such that opening and closing thereof are controlled based on said horizontal synchronization signal.

5. The image display device according to claim 3, wherein said signal switching circuit includes a plurality of transmission gates.

6. The image display device according to claim 4, wherein said signal switching circuit includes a plurality of transmission gates.

7. The image display device according to claim 1, wherein said shift pulse generating circuit includes a plurality of delay latch circuits.

8. The image display device according to claim 2, wherein said circuit part of said horizontal shift register includes a plurality of delay latch circuits shared for generation of said first latch signal and said second latch signal.

9. The image display device according to claim 1, wherein active elements constituting said gate line driving circuit, said source line driving circuit and said timing controller are thin film transistors.

10. The image display device according to claim 2, wherein active elements constituting said gate line driving circuit, said source line driving circuit and said timing controller are thin film transistors.