The present application claims priority from Japanese Application JP 2005-256500 filed on Sep. 5, 2005, the content of which is hereby incorporated by reference into this application.
The present invention relates to an image display device including cathode spots from which electrons are emitted with application of an electric field, and a fluorescent screen that is excited with the electrons emitted from the cathode spots. More particularly, the present invention is concerned with an image display device that avoids occurrence of a display defect derived from a break of any of lines, which are formed according to a printing method, occurring during a baking process. The present invention is preferably adapted to a flat-panel image display device whose cathode from which electrons are emitted with application of a low electric field is made of a carbonic material such as carbon nanotube, fine carbon fibers, or diamond.
Emissive materials such as diamond and carbon nanotube (CNT) that exhibit satisfactory electron emission responsively to application of a feeble electric field that is feebler than an electric field required by a field emission cathode made mainly of a conventional metallic material have been exploited. Plural cathode spots made of such an emissive material is formed like a matrix in a first substrate. The first substrate is bonded to a second substrate, in which phosphor dots and an anode are formed, in order to form a vacuum container, whereby an image display device is produced as a field-emission image display device.
This type of image display device is known to have cathode spots and neighboring control electrodes arranged in the form of a matrix in a main surface that is one of the surfaces of a first substrate referred to as a back substrate or a cathode substrate. Phosphor dots arrayed in the form of a matrix in line with the matrix of cathode spots, and an anode are formed in a main surface that is one of the surfaces of a second substrate referred to as a front substrate or a phosphor substrate. Herein, electrons emitted from the cathode spots are controlled by the control electrodes, and accelerated with an acceleration voltage applied to the anode. This excites the phosphor spots. Light emitted from each of the phosphor dots is used to display an image.
Patent Documents 1 and 2 have disclosed such image display devices in which cathode spots and control electrodes are disposed on the same plane parallel to the main surface of the first substrate (in-plane-gate (IPG) structure). Patent Document 3 has disclosed an image display device in which a wide bus is adopted in consideration of the distribution of wiring resistances at cathode spots.
[Patent Document 1] Japanese Patent Laid-Open No. 2002-25478
[Patent Document 2] Japanese Patent Laid-Open No. 2004-5186219
[Patent Document 3] Japanese Patent Laid-Open No. H11-185677
For example, a paste containing a conductive material such as silver is used to print the wiring that interconnects cathode spots at which an electron emission layer is made of carbon nanotube (CNT), and the printed wiring is baked in order to form thin wiring. For example, concerning the IPG structure, a silver paste is used to print a pattern of lines, which are 30 μm in width, from the viewpoint of a driving voltage. When the printed pattern of thin lines is baked in order to complete a wiring pattern, the print layer may contract to cause a break. According to the ongoing structure including cathode spots, a cathode also serves as cathode feeder lines (cathode lines). Therefore, if a break occurs in the printed pattern, power is not fed to cathode spots succeeding the break spot. Consequently, electronic emission is not achieved any longer. This results in plural defective pixels (display defects).
The present invention is intended to provide an image display device that is free from a terrible display defect because occurrence of a break derived from adoption of a wiring pattern of thin lines is prevented.
According to the present invention, (1) each of cathode spots is composed of an electron emission layer and a cathode base bearing the electron emission layer, cathode lines are formed separately, and each of the cathode spots is electrically coupled to a cathode line over a cathode branch line. Moreover, according to the present invention, the width of the cathode lines is larger than that of the cathode bases. Furthermore, according to the present invention, each of the cathode bases is electrically coupled to a cathode line over plural paths. According to the present invention, each of the cathode bases has a portion whose tensile strength is lower and which is liable to rupture.
Since the cathode lines are included independently of the cathode spots, even if any of the cathode spots is broken, electron emission is normally achieved at pixel locations (or, simply, pixels) other than a pixel realized with the cathode spot. Consequently, occurrence of a terrible display defect is avoided. Moreover, since the width of the cathode lines is larger than that of the cathode bases, the probability of occurrence of a break of a cathode line that affects a larger number of pixels can be minimized. Furthermore, since each of the cathode bases is electrically coupled to a cathode line over plural paths, as long as the number of breaks occurring among nodes is equal to or smaller than an estimated number of breaks, the coupling to all the cathode spots can be satisfactorily sustained. Each of the cathode bases is artificially provided with a portion that is liable to break and that is formed in a region whose break is permissible. The permissible break alleviates a tensile stress and helps prevent an unexpected break from occurring in the other portion.
According to the present invention, since a pixel that becomes defective is only a pixel at which a break has occurred, deterioration in image quality derived from occurrence of the defect can be minimized. Moreover, the cross-sectional area of each cathode line can be increased without being restricted by a driving voltage affected by the width of each cathode spot. Consequently, a break hardly occurs. Moreover, an electrical resistance can be decreased. Eventually, not only reliability but also responsiveness can be improved.
According to the present invention, as long as the number of breaks that have occurred is equal to or smaller than the estimated number of breaks, electrical couplings among the cathode lines and the cathode spots are left unaffected. Occurrence of a detective pixel can be suppressed. As a result, deterioration in image quality can be prevented and a yield can be improved.
According to the present invention, since a break occurs in a portion where occurrence of a break is predicted, measures can be readily taken against occurrence of the break and a yield can be readily improved. Consequently, a cost of manufacture can be reduced. Moreover, since a break occurs in a portion where occurrence of a break is permitted, occurrence of a break in a portion where the occurrence is not permitted can be suppressed. Eventually, a yield can be improved.
Referring to the drawings, embodiments of the present invention will be described below. Noted is that dimensions presented in a description of embodiments are exemplary values.
Plural gate lines (control electrode lines) 4 insulated by an insulating layer 7 are juxtaposed while intersecting the cathode lines 2. Control electrodes (gate electrodes) 1 are coupled to each of the gate lines 4 via respective gate branch lines 5 at respective gate nodes 8. The control electrodes 1 are disposed so that they will be flush with the cathode spots 10 and every pair of control electrodes 2 will sandwich each cathode spot 10.
The electrodes and electrode lines are formed by applying and baking a silver paste. The electron emission layer 12 is formed after the cathode bases are baked. The cathode lines are wider than the cathode bases 11. Preferably, the cathode bases 11 should be as thinner as possible so that an electric field induced by each of the control electrodes 1 will efficiently act on electrons emitted from the electron emission layer 12. However, as the cathode bases 11 get thinner, the probability that the cathode bases may rupture due to contraction occurring during a baking process gets higher.
In the first embodiment, the cathode spots 10 are formed independently of the cathode lines. Consequently, a break occurring in any of the cathode spots is limited to the pixel concerned and does not affect the other pixel locations.
The second embodiment is characterized in that the cathode base 11 included in each cathode spot 10 is electrically coupled to a cathode line 2 at two cathode nodes 3. The other constituent features are identical to those of the first embodiment. FIG. 7 shows the cathode spots 10 each of which is sandwiched between the gates 1 flush with the cathode spots. In the present embodiment, each of the cathode spots 10 is coupled to a cathode line at the cathode nodes 3 via respective cathode branch lines 6 extending in the longitudinal directions from the ends of the cathode spot 10. The present invention is not limited to this structure. Alternatively, each of the cathode spots 10 may be electrically coupled to a cathode line by extending two, three, or more cathode branch lines from any points of a cathode base.
As mentioned above, according to the second embodiment, plural feeder paths is formed between each cathode spot and a cathode line. Therefore, even if some breaks occur at a cathode spot, as long as the number of breaks is equal to or smaller than an estimated number of breaks, a current can be fed to the electron emission layer through the cathode lines. A defective pixel will not ensue.
In the third embodiment, gate lines 4 are formed in the main surface of a back substrate 101, and cathode spots 10 are formed on the gate lines 4 with an insulating layer 7 between them. Each of the gate lines 4 has a gate branch line 5, which is formed in the same layer as the gate lines are formed, coupled thereto. The cathode lines 2 and cathode bases 11 are formed on the insulating layer 7. The electron emission layer 12 is formed over the surfaces of the cathode bases 11, whereby the cathode spots 10 are completed. As shown in
A pair of gates 1a and 1b is disposed by the right-hand and left-hand sides respectively of each of cathode spots 10, and thus sandwiches the cathode spot. Each of the gates 1a and 1b includes a portion parallel to the longitudinal directions of the cathode spot 10 and a gate node 9 whose area is larger than that of the parallel portion thereof. The gate node 9 has an area large enough to have a contact hole 13 which penetrates through the insulating layer 7 and through which the gate branch line 5 is electrically coupled to the gate 1a or 1b. The gates 1a and 1b are coupled to the respective gate branch lines 5, which are joined to the gate line 4, via the respective contact holes 13 at the respective gate nodes 8.
As mentioned above, according to the third embodiment, the gate lines are formed in a layer under the cathode lines so that a wide space can be preserved on the surface of the insulating layer on which a cathode structure is formed. Each of the cathode spots that are juxtaposed is coupled to two cathode lines. Consequently, even if a break occurs at any cathode spot, the break will not affect the other cathode spots.
The cathode lines 2, cathode bases 11, and cathode branch lines 6 are printed. When they are baked, contraction occurs. Consequently, tensile stresses that recede from each other as indicated with arrows A1 and A2 in
The fourth embodiment provides the same advantages as those of the third embodiment. In addition, a break at a cathode spot is suppressed. Moreover, a tensile stress induced in each cathode line is alleviated, and a break of the cathode line is prevented.
In the fifth embodiment, a cathode base 11 included in each cathode spot 10 has a rupture-prone portion 51a that is more liable to rupture due to tensile stresses than the other portion of the cathode base. The rupture-prone portion 51a has notches formed on both sides of the cathode base 11 on which the electron emission layer 12 is formed.
During baking succeeding printing of cathode bases and others, any of the cathode bases may contract. In this case, tensile stresses derived from the contraction are concentrated on the rupture-prone portion 51a including notches so that the portion will rupture first. According to the fifth embodiment, a rupture can be prevented from occurring in the other portion of the cathode base in which the rupture leads to a fatal defect in movement.
Plural spacers 301 are interposed between the substrates in order to restrict a so-called cell gap to a predetermined value. After the vacuum container is deaerated through a vent 303, the vent 303 is fused to seal the vacuum container so that the inside of the vacuum container will be retained at a predetermined degree of vacuum.
As for the face panel 200, after the black matrix 202 is patterned on the face substrate 201, the phosphor dots 203 are formed in the openings of the black matrix 202. A metallic (for example, aluminum) layer is deposited over the phosphor dots in order to form the anode 204. The main surface of the face panel that is the side of the anode 204 is opposed to the main surface of the back panel 100, and bonded with a partition 5 between them. After the internal space of the bonded panels is deaerated through the vent 303, the vent is fused in order to seal the internal space. The phosphor dots are formed at the respective pixel locations. For full-color display, one color pixel is realized with red, green, and blue pixels.
In the above description, the anode 204 is formed on the uppermost layer of the face substrate 201 (on the fluorescent screen). After the anode is formed, the black matrix and fluorescent layer may be formed. However, in this case, a transparent electrode should be adopted as the anode. Moreover, the anode need not be a solid electrode but may have electrodes arranged in the form of stripes in the direction in which scan electrodes or data electrodes are arrayed.
In an image display device including the display panel of any of the present embodiment, when a voltage of 10 kV is applied to the anode and a voltage of 0 V is applied to each of control electrodes and cathode spots, electrons are emitted. When a voltage of −50 V is applied to each of the control electrodes and a voltage of 50 V is applied to each of the cathode spots, the electron emission is ceased. In this state, if a voltage of 0 V is applied to either the control electrodes or cathode spots, the electron emission is ceased. Thus, the so-called matrix operation is accomplished.
The present invention is not limited to the structures described in relation to the respective embodiments. Needless to say, various modifications can be made without a departure from the technological idea of the present invention.
Number | Date | Country | Kind |
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2005-256500 | Sep 2005 | JP | national |