Patent Application
20100128066
The present invention relates to an image display method and image display apparatus configured to display in an intensity level for a display device in which a control electrode such as a fluorescence display tube, PDP or LCD and light-emitting point electrode group constitutes an X-Y matrix.
There is known a pulse width modulating intensity level displaying method having a plurality of light-emitting bodies disposed on a surface to constitute a plurality of pixels, and a display drive control circuit including a plurality of input terminals corresponding to the number of bits of the indicative data supplied to light the light-emitting bodies, and a plurality of parallel signal processing circuits corresponding to the input terminals, the display drive control circuit configured to drive the light-emitting bodies in a pulse width corresponding to the intensity level defined by the indicative data, and the method displaying the image having the intensity level defined by the indicative data on a fluorescence display tube. For instance, this technique is disclosed in Patent Literature 1.
According to the aforementioned pulse width modulating intensity level displaying method, it is characterized that the control circuit is lightened of load by large reduction in times of data transfer per one indicative cycle by the weighted period.
The circuit for the aforementioned conventional pulse width modulating intensity level displaying method is provided with input terminals corresponding to the number of bits constituting the indicative data in order to input the indicative data defining the intensity level, and a indicative drive control circuit including a plurality of parallel signal processing circuit connected to them. However, it is a disadvantage for the conventional indicative drive control circuit that the size of the circuit and the cost should increase with accordance with an increase in the intensity level defined by the indicative data and the number of bits, due to a proportional increase in the number of the aforementioned input terminals and a plurality of the parallel signal processing circuit connected to them. For instance, since the indicative data for 8 intensity levels is constituted of 3 bits, three pairs of the input terminals and the parallel signal processing circuits connected to them are sufficient. In the case of the indicative data for 64 intensity levels, it is constituted of 6 bits. Then, six pairs of the input terminals and the parallel signal processing circuits connected to them are required, and, accordingly, the display drive control circuits are required on a twofold scale.
Further, when integrated display drive control circuits are manufactured, it is difficult to provide various kinds of them, and various kinds of integrated display drive control circuits are required to be manufactured in accordance with the respective intensity levels, accordingly, it is a disadvantage that it causes high costs.
Then, although not yet disclosed, it is inventable without increasing the scale of the display drive control circuit and high costs, that displaying in, for instance, the aforementioned 64 intensity levels are achieved by dividing a plurality of bits, that is, 6 bits constituting the indicative data defining multiple intensity levels, that is, 64 intensity levels, into the upper digit bit group including upper 3 bits and the lower digit bit group including lower 3 bits and alternately inputting them to the aforementioned input terminals, by displaying in a relatively roughly-set intensity level corresponding to the upper digit bit group in the first period, and in a relatively finely-set intensity level corresponding to the lower digit bit group in the second period. However, in this case, the second period is shorter, that is, eighth (⅛) of the indicative cycle than the first period, and, accordingly, it is insufficient of time to send the indicative data of the lower 3 bits in the second period, then, the input of the indicative data of the lower 3 bits with adding an additional period following the second period is required to receive the indicative data, however, it causes a disadvantage that the additional period is useless because it does not contribute to emitting light and reduces luminance of the image display apparatus. Otherwise, it is inventable that a high frequency clock is provided to supply the indicative data for displaying the aforementioned second period to the second period, however, it is expensive and raises the cost.
It is therefore an object of the present invention to provide an improvement of the image display method and image display apparatus to implement the method having the small-sized display drive control circuit at a reasonable cost in more intensity levels. And it is another object of the present invention to provide an improvement of the image display method and image display apparatus to implement the method having the small-sized display drive control circuit at a reasonable cost in more intensity levels without reduction of luminance in the image display apparatus.
The object defined above may be achieved according to the invention in claim 1, which provides an image display method for displaying an image having an intensity level defined by indicative data, (a) including a plurality of light-emitting bodies disposed on a surface to constitute a plurality of respective pixels, a parallel signal processing circuit corresponding to a plurality of input terminals and output terminals to which the indicative data supplied to light the plurality of light-emitting bodies are input, including: (b) a display data supply step for dividing a plurality of bits constituting the indicative data that define the number of the intensity level more than the number of the intensity level defined by the number of a bit corresponding to the number of the input terminal, into a first bit group and a second bit group, and for alternately supplying them to the input terminals; (c) a first period luminous control step for lighting predetermined light-emitting bodies selected from the plurality of light-emitting bodies in an intensity level corresponding to the first bit group of the indicative data, in a first period set in a luminous control period that is repeatedly assigned to the predetermined light-emitting bodies; and (d) a second period luminous control step for lighting the predetermined light-emitting bodies in an intensity level corresponding to the second bit group of the indicative data, in a second period set following the first period in the luminous control period.
The object defined above may be achieved according to another invention in claim 5, which provides an image display apparatus for displaying an image having an intensity level defined by indicative data, (a) including a plurality of light-emitting bodies disposed on a surface to constitute a plurality of respective pixels, a parallel signal processing circuit corresponding to a plurality of input terminals and output terminals to which the indicative data supplied to light the plurality of light-emitting bodies are input, including: (b) a display data supply means for dividing a plurality of bits constituting the indicative data that define the number of the intensity level more than the number of the intensity level defined by the number of a bit corresponding to the number of the input terminal, into a first bit group and a second bit group, and for alternately supplying them to the input terminals; (c) a first period luminous control means for lighting predetermined light-emitting bodies selected from the plurality of light-emitting bodies in an intensity level corresponding to the first bit group by supplying the indicative data of the first bit group to the input terminals, in a first period set in a luminous control period that is repeatedly assigned to the predetermined light-emitting bodies; and (d) a second period luminous control means for lighting the predetermined light-emitting bodies in an intensity level corresponding to the second bit group by supplying the indicative data of the second bit group to the input terminals, in a second period set following the first period in the luminous control period.
According to the inventions in claims 1 and 5, a display data supply step or means divides a plurality of bits constituting the indicative data constituted of the number of bits more than the number of a bit corresponding to the number of the input terminal in order to define the number of the intensity level more than the number of the intensity level defined by the number of bits corresponding to the number of the input terminal, into a first bit group and a second bit group, and for alternately supplies them to the input terminals; a first period luminous control step or means lights predetermined light-emitting bodies selected from the plurality of light-emitting bodies in an intensity level corresponding to the first bit group of the indicative data, in a first period set in a luminous control period that is repeatedly assigned to the predetermined light-emitting bodies; and a second period luminous control step or means lights the predetermined light-emitting bodies in an intensity level corresponding to the second bit group of the indicative data, in a second period set prior to or following the first period in the luminous control period. Accordingly, since the display drive control circuit including the fewer input terminals than the value of bits defining the intensity level of the aforementioned indicative data and the following parallel signal processing circuits connected is sufficient, even if the value of the intensity level increases, a small-sized display drive control circuits can be provided at a reasonable cost.
Preferably, the display data supply step or means divides the plurality of bit strings constituting the indicative data into the first bit group including a plurality of bits which constitute each of the bit strings and are positioned in non-successive order in the bit string and the second bit group including a plurality of bits except the bits included in the first bit group, and alternately supplies them to the input terminals. That is, the first bit group to control the intensity levels in the first period includes a plurality of bits which constitute each of the bit strings and are positioned in non-successive order in the bit string selected from a plurality of bit strings constituting the indicative data, and the second bit group including a plurality of bits except the bits included in the first bit group selected from a plurality of bits constituting the indicative data. Accordingly, since the second period has a longer duration of time, in comparison with another case in which the second bit group is constituted of the lower bits selected from a plurality of bits constituting the indicative data, and the duration of time of the second period approaches that of the first period, it is not necessary to reduce the luminance of the image display apparatus or to use a high frequency clock for providing the indicative data in order to define the second period, and, consequently, a small-sized display drive control circuits can be provided at a reasonable cost.
Preferably, the first bit group includes an uppermost bit and a lowermost bit of each of the indicative data, and the second bit group includes a plurality of intermediate bits interposed by the bits constituting the first bit group. Accordingly, since the second period has a longer duration of time, in comparison with another case in which the second bit group is constituted of the lower bits selected from a plurality of bits constituting the indicative data, and the duration of time of the second period approaches that of the first period, it is not necessary to reduce the luminance of the image display apparatus or to use a high frequency clock for providing the indicative data in order to define the second period, and, consequently, a small-sized display drive control circuits can be provided at a reasonable cost.
Preferably, the display data supply step divides the plurality of bit strings constituting the indicative data into the first bit group including upper part of the bit strings, that is, a predetermined number of successive bits including the most significant bit (MSB) in the bit strings and the second bit group including lower part of the bit strings, that is, a predetermined number of successive bits including the least significant bit (LSB) in the bit strings, and alternately supplies them to the input terminals. Accordingly, since the display drive control circuit including the fewer input terminals than the value of bits defining the intensity level of the aforementioned indicative data and the following parallel signal processing circuits connected is sufficient, even if the value of the intensity level increases, a small-sized display drive control circuits can be provided at a reasonable cost.
Preferably, (a) the first period luminous control means outputs a first GCP signal defining timing to steppingly reduce along with time elapsing in the first period; (b) the second period luminous control means outputs a second GCP signal defining timing to steppingly reduce along with time elapsing in the second period; and (c) the display drive control circuit includes a luminous pulse width control circuit configured to compare the first GCP signal and the first bit group in the first period, and to output a comparison signal when a value defined by the first GCP signal is equal to or lower than a value defined by the first bit group, and to compare the second GCP signal and the second bit group in the second period, and to output a comparison signal when a value defined by the second GCP signal is equal to or lower than a value defined by the second bit group, and a drive circuit configured to light the light-emitting element in response to an output of the comparison signal from the luminous pulse width control circuit. Accordingly, during the summed period of the first period from the output of the comparison signal to the termination of the first period and the second period from the output of the comparison signal to the termination of the second period, the light-emitting element is lighted, and displaying the intensity level defining the indicative data is achieved.
Preferably, (a) the first period luminous control means outputs a first GCP signal defining timing to steppingly increase along with time elapsing in the first period; (b) the second period luminous control means outputs a second GCP signal defining timing to steppingly increase along with time elapsing in the second period; and (c) the display drive control circuit includes a luminous pulse width control circuit configured to compare the first GCP signal and the first bit group in the first period, and to output a comparison signal when a value defined by the first GCP signal exceeds a value defined by the first bit group, and to compare the second GCP signal and the second bit group in the second period, and to output a comparison signal when a value defined by the second GCP signal exceeds a value defined by the second bit group, and a drive circuit configured to put out the light-emitting element in response to an output of the comparison signal from the luminous pulse width control circuit. Accordingly, during the summed period of the first period from the initiation of the first period to the output of the comparison signal and the second period from the initiation of the second period to the output of the comparison signal, the light-emitting element is lighted, and displaying the intensity level defining the indicative data is achieved.
Preferably, (a) the plurality of light-emitting bodies disposed are fluorescent bodies that are disposed on a positive electrode of a fluorescence display tube and are configured to light by collision of an electron generated in a cathode of the fluorescence display tube and accelerated through any of a plurality of control grids; and (b) the luminous control period assigned to the predetermined light-emitting bodies is a period in which an accelerated voltage is applied to a control grid covering the predetermined light-emitting bodies selected from the control grids; and (c) the apparatus further includes a grid switching means for serially selecting light-emitting bodies capable of emitting light from the plurality of light-emitting bodies disposed, by serially and repeatedly applying a control voltage pulse to the plurality of control grids. Accordingly, the fluorescent body of the fluorescence display tube is displayed in the intensity level of the indicative data by fewer display drive control circuits including the input terminals and the parallel signal processing circuits connected to them, than the number of the bits defining the intensity level of the indicative data.
Preferably, the grid switching means serially and repeatedly applies one control voltage pulse having a time width corresponding to the first period and the following second period, to the plurality of control grids. Accordingly, the fluorescent body of the fluorescence display tube is displayed in the intensity level of the indicative data by fewer display drive control circuits including the input terminals and the parallel signal processing circuits connected to them, than the number of the bits defining the intensity level of the indicative data.
Preferably, the grid switching means serially applies a first control voltage pulse having a time width corresponding to the first period to the plurality of control grids, and then serially applies a second control voltage pulse having a time width corresponding to the second period to the plurality of control grids, and repeatedly applies them. Accordingly, the fluorescent body of the fluorescence display tube is displayed in the intensity level of the indicative data by fewer display drive control circuits including the input terminals and the parallel signal processing circuits connected to them, than the number of the bits defining the intensity level of the indicative data.
Referring to the drawings, there will be described in detail a preferred embodiment of the present invention.
Referring back to
A display drive control circuit 30 is provided for each of the anode terminals such as A1a, A1b and A1c.
The control circuit 34 is provided with a first input terminal 36, second input terminal 38, third input terminal 40, first shift register 42, second shift register 44, third shift register 46, first latch circuit 48, second latch circuit 50, third latch circuit 52, pulse width control signal generating circuit (GCP decoder) 54, luminous pulse control circuit 56. Into the first, second and third input terminals 36, 38, 40, a first bit group and second bit group are alternately input in parallel. The first bit group includes an uppermost digit bit b5 and a lowermost digit bit b0 such as a set of b5, b1 and b0 that are selected from the indicative data D, for instance, constituted of six bits b5 to b0 defining luminance in 64 intensity levels, and the second bit group includes a plurality of interposed digit bits, that is, b4, b3 and b2 in this example, interposed among the bits b5, b1 and b0 that constitutes the first bit group. The first, second and third shift registers 42, 44, 46, are configured to serially store each signal supplied into the first, second and third input terminals 36, 38, 40, respectively, in response to a CLK (clock) signal. The first, second and third latch circuits 48, 50, 52 are configured to latch each output signal from the first, second and third shift registers 42, 44, 46 for a predetermined period of time. The pulse width control signal generating circuit (GCP decoder) 54 is configured to convert a GCP signal into a 3-bit parallel signal. The luminous pulse control circuit 56 is configured to compare the 3-bit parallel signal converted from the GCP signal, with three bit signals from the first, second and third latch circuits 48, 50, 52, and to output a comparative output (on-output) through a blanking circuit 58 to the driver 32 when a value of the GCP signal is equal to or lower than a value of the three bit signals. The blanking circuit 58 is configured to interrupt a signal supplied from the luminous pulse width control circuit 56 to the driver 32 in response to a BK (blanking) signal, and to preferentially place the driver 32 in the off state.
Referring to
Referring to
Referring to
Referring to the time chart of
As shown in the time chart of
In a predetermined period of luminous control of the light-emitting element 22 implemented in a respective grid switching, the timing control means 60 generates a first BK signal SB1 having a predetermined pulse width at a point t1 prior to the first period K1 (from t3 to t10), and generates a second BK signal SB2 having a pulse width equal to that of the first BK signal SB1 at the termination point, that is, a point t10 prior to the second period K2 (from t12 to t19)
In the aforementioned first period K1 in a prior luminous control period, the indicative data supply means 64 divides 6-bit luminous data D defining 64 intensity level luminance of a predetermined light-emitting element 22 in a present luminous control period, into the first bit group of the bits b5, b1, b0 including the uppermost digit bit b5 and the lowermost digit bit b0 and the second bit group including the plurality of interposed bits b4, b3, b2 interposed by the bits b5, b1, b0 constituting the first bit group, and at first supplies the signals of the second bit group of the bits b4, b3, b2 to the first, second and third input terminals 36, 38, 40, respectively. The supplied signals of the second bit group of the bits b4, b3, b2 are stored in the first, second and third shift registers 42, 44, 46, in synchronization with supplying the CLK signal CLK1 in the first indicative data supply period TD1. Then, in the aforementioned second period K2 in the prior luminous control period, the indicative data supply means 64 supplies the remaining signals of the first bit group of the bits b5, b1, b0 to the first, second and third input terminals 36, 38, 40, respectively. The supplied signals of the first bit group of the bits b5, b1, b0 are stored following the signals of the second bit group of the bits b4, b3, b2 in the first, second and third shift registers 42, 44, 46, in synchronization with supplying the CLK signal CLK1 in the second indicative data supply period TD2. In the present luminous control period, the indicative data supply means 64 divides the luminous data D for lighting in the following luminous control period as well, serially supplies the second bit group of the bits b4, b3, b2 in the first period K1 and the first bit group of the bits b5, b1, b0 in the second period K2 to the first, second and third input terminals 36, 38, 40, respectively, and has them serially stored in the first, second and third shift registers 42, 44, 46.
The timing control means 60 generates the first LAT signal SL1 (at point t2) during generation of the aforementioned first BK signal SB1, and generates the second LAT signal SL2 (at point t11) during generation of the aforementioned second BK signal SB2. By generation of the first LAT signal SL1, the bits b5, b1, b0 of the first bit group of the luminous data D stored in the first, second and third shift registers 42, 44, 46 are latched in the first, second and third latch circuit 48, 50, 52, the bits b5, b1, b0 of the first bit group of the luminous data D latched in the first, second and third latch circuit 48, 50, 52 are supplied to the luminous pulse width control circuit 56 until supply of the second LAT signal SL2. By generation of the second LAT signal SL2, the bits b4, b3, b2 of the second bit group of the luminous data D stored in the first, second and third shift registers 42, 44, 46 are latched in the first, second and third latch circuit 48, 50, 52, the bits b4, b3, b2 of the second bit group of the luminous data D latched in the first, second and third latch circuit 48, 50, 52 are supplied to the luminous pulse width control circuit 56 until supply of the next first LAT signal SL1.
When the timing control means 60 has the first BK signal SB1 fallen (at point t3), the grid switching means 62 supplies a signal to apply a control voltage to a grid G to light a predetermined light-emitting element 22 until the following luminous control period starts, to the grid driver. Concurrently, the first period luminous control means 68 of the luminous control means 66 starts to supply the first GCP signal SG1 to the pulse width control signal generating circuit 54, and then, the first GCP signal SG1 is converted into a 3-bit parallel signal and the converted signal is supplied from the pulse width control signal generating circuit 54 to the luminous pulse width control circuit 56. The first GCP signal SG1 for the first period K1 that is a pulse defining timing of intensity level reduction such that the intensity levels “35”, “34”, “33”, “32”, “3”, “2”, “1” and “0” correspond to reduction stage numbers “7”, “6”, “5”, “4”, “3”, “2”, “1” and “0” in the first period K1, is output. In an example shown in
When the timing control means 60 raises the second BK signal SB2 (at point t10) and generates the second LAT signal during raising of the second BK signal SB2 (at point t11), the generation of the second LAT signal causes the signals of the bits b4, b3, b2 of the second bit group of the luminous data D stored in the first, second and third shift registers 42, 44, 46 to be latched in the first, second and third latch circuit 48, 50, 52, the signals of the bits b4, b3, b2 of the second bit group of the luminous data D latched in the first, second and third latch circuit 48, 50, 52 is supplied to the luminous pulse width control circuit 56 until the first LAT signal of the following luminous control period is supplied. Concurrently, the second period luminous control means 70 of the luminous control means 66 supplies the second GCP signal SG2 to the pulse width control signal generating circuit 54, and then, the second GCP signal SG2 is converted into a 3-bit parallel signal and the converted signal is supplied from the pulse width control signal generating circuit 54 to the luminous pulse width control circuit 56. The second GCP signal SG2 is a pulse defining timing of intensity level reduction at seven equal intervals of time in the second period K2 such that the intensity levels “28”, “24”, “20”, “16”, “12”, “8”, “4” and “0” correspond to reduction stage numbers “7”, “6”, “5”, “4”, “3”, “2”, “1” and “0”. In an example shown in
Since drive voltages that are luminous pulses corresponding to the on states of the driver 32 in the first and second periods K1, K2 are applied to the light-emitting element 22, the element 22 is driven in a duty ratio corresponding to the intensity level “37”, the sum of the intensity level “33” in the first period K1 and the intensity level “4” in the second period k2, as shown by the aforementioned luminous data D, and the element 22 is lighted in the intensity level “37” defined by the luminous data D.
In S5 corresponding to the action of the indicative data supply means 64 and the indicative data supply step, concurrently with the action in S4, in the first period K1, the bits b4, b3, b2 of the second bit group that are the indicative data D used in the following luminous control period K2 are supplied to the first, second and third input terminals 36, 38, 40, and to be stored in the first, second and third shift registers 42, 44, 46. The bits b4, b3, b2 of the second bit group are supplied in the first period K1, that is, the first indicative data supply period TD1 between points t3 and t10 in
Thus, the first period K1 is terminated, and in S6 and S7 corresponding to the action of the timing control means 60, the second BK signal SB2 with a predetermined duration of time is output and the second LAT signal is output during raising of the second BK signal SB2 (from point t10 to t11 in
As described above, according to the present embodiment, the indicative data D that are defining “64” intensity levels more than “8” intensity levels defined by three (3) bits corresponding to the number of the input terminals 36, 38, 40, are divided into the first bit group including the bits b5, b1, b0 and the second bit group including the bits b4, b3, b2, and the bits of the divided groups are alternately supplied to the first, second and third input terminals 36, 38, 40, in the first period K1 set within the luminous control period that is repeatedly assigned to a predetermined light-emitting element 22 selected from a plurality of light-emitting elements, the predetermined light-emitting element 22 is lighted in an intensity level corresponding to the indicative data of the first bit group including the bits b5, b1, b0 stored in the second period K2, and, furthermore, in the second period K2 following the first period K1, the predetermined light-emitting element 22 is lighted in an intensity level corresponding to the indicative data of the second bit group including the bits b4, b3, b2 stored in the first period K1. Accordingly, since the display drive control circuit 30 including the fewer input terminals 36, 38, 40 than the value of bits defining the intensity level of the aforementioned indicative data D and the following parallel signal processing circuits (the first, second and third shift registers 42, 44, 46 and the first, second and third latch circuits 48, 50, 52) is sufficient, even if the value of the intensity level increases, a small-sized display drive control circuits 30 can be provided at a reasonable cost.
According to the present embodiment, the first bit group including the bits b5, b1, b0 to control the intensity levels in the first period K1 includes the uppermost digit bit b5 and lowermost digit bit b0 in a plurality of bits constituting the indicative data D, and the second bit group including the bits b4, b3, b2 to control the intensity levels in the second period K2 includes a plurality of interposed digit bits, that is, b4, b3, b2 which are interposed among the bits b5, b1, b0 constituting the first bit group in a plurality of bits constituting the indicative data D. Accordingly, since the second period K2 has a longer duration of time in the present embodiment in which the second bit group is constituted of the bits b4, b3, b2, in comparison with another embodiment in which the second bit group is constituted of the bits b2, b1, b0, that is, the lower bits in a plurality of bits constituting the indicative data D, and the duration of time of the second period K2 approaches that of the first period K1, it is not necessary to reduce the luminance of the image display apparatus 10 or to use a high frequency clock for providing the indicative data D in order to define the second period K2, and, consequently, a small-sized display drive control circuits 30 can be provided at a reasonable cost.
According to the present embodiment, it is provided the image display apparatus wherein (a) the first period luminous control means 68 outputs a first GCP signal SG1 defining timing to steppingly reduce along with time elapsing in the first period K1; (b) the second period luminous control means 70 outputs a second GCP signal SG2 defining timing to steppingly reduce along with time elapsing in the second period K2; and (c) the display drive control circuit 30 includes a luminous pulse width control circuit 56 configured to compare a reduction stage number defined by the first GCP signal SG1 and the first bit group including b5, b1, b0 in the first period K1, and outputs a comparison signal when the reduction stage number defined by the first GCP signal SG1 is equal to or lower than a value defined by the first bit group including b5, b1, b0, and to compare a reduction stage number defined by the second GCP signal SG2 and the second bit group including b4, b3, b2 in the second period K2, and outputs a comparison signal when the reduction stage number defined by the second GCP signal SG2 is equal to or lower than a value defined by the second bit group including b4, b3, b2, and a driver (drive circuit) 32 configured to light the light-emitting element 22 in response to an output of the comparison signal from the luminous pulse width control circuit 56. Consequently, during the summed period of the first period K1 from the output of the comparison signal to the termination of the first period K1 and the second period K2 from the output of the comparison signal to the termination of the second period K2, the light-emitting element 22 is lighted, and it corresponds to the intensity level defining the indicative data D.
According to the present embodiment, it is provided the image display apparatus wherein (a) the plurality of light-emitting elements 22 disposed are fluorescent bodies that are disposed on a positive electrode of a fluorescence display tube 12 and are configured to light by collision of an electron generated in a cathode of the fluorescence display tube 12 and accelerated through any of a plurality of control grids Gn; and (b) the luminous control period assigned to the predetermined light-emitting element 22 is a period in which an accelerated voltage is applied to a control grid G covering the predetermined light-emitting element 22 selected from the control grids Gn; and the apparatus further includes (c) a grid switching means 62 for serially selecting a light-emitting element 22 capable of emitting light from the plurality of light-emitting elements 22 disposed, by serially and repeatedly applying a control voltage pulse to the plurality of control grids Gn. Consequently, the fluorescent body of the fluorescence display tube 12 is displayed in the intensity level of the indicative data D by fewer display drive control circuits 30 than the number of the bits defining the intensity level of the indicative data D. The display drive control circuits 30 includes the first, second and third input terminals 36, 38, 40 and the parallel signal processing circuits (the first, second and third shift registers 42, 44, 46 and the first, second and third latch circuits 48, 50, 52) connected to the input terminals.
According to the present embodiment, it is provided the image display apparatus wherein the grid switching means 62 serially and repeatedly applies one control voltage pulse having a time width corresponding to the first period K1 and the following second period K2 to the plurality of control grids Gn. Consequently, the light-emitting element 22 is displayed in the intensity level of the indicative data D by fewer display drive control circuits 30 than the number of the bits defining the intensity level of the indicative data D. The display drive control circuits 30 includes the first, second and third input terminals 36, 38, 40 and the parallel signal processing circuits (the first, second and third shift registers 42, 44, 46 and the first, second and third latch circuits 48, 50, 52) connected to the input terminals.
There will be described in detail another embodiment of the present invention. In the following descriptions, the same reference signs are assigned to the common components to the above and below embodiments and the description on them will be omitted.
The descriptions are common to this embodiment and the aforementioned embodiment in
Referring to
Referring to
The control circuit 34 in this embodiment is provided with the first input terminal 36, second input terminal 38, third input terminal 40, first shift register 42, second shift register 44, third shift register 46, first latch circuit 48, second latch circuit 50, third latch circuit 52, GCP decoder 54, luminous pulse control circuit 56. Into the first, second and third input terminals 36, 38, 40, the upper digit bits b5 to b3 and the lower digit bits b2 to b0 of the 6-bit indicative data D defining luminance in 64 intensity levels are alternately input. The first, second and third shift registers 42, 44, 46, are configured to serially store each signal supplied into the first, second and third input terminals 36, 38, 40, respectively, in response to a CLK (clock) signal. The first, second and third latch circuits 48, 50, 52 are configured to latch each output signal from the first, second and third shift registers 42, 44, 46 for a predetermined period of time, in response to the LAT signal. The GCP decoder 54 is configured to convert the GCP signal into a 3-bit parallel signal. The luminous pulse control circuit 56 is configured to compare the 3-bit parallel signal converted from the GCP signal, with three bit signals from the first, second and third latch circuits 48, 50, 52, and to output a comparative output to the blanking circuit 58 when a value of the GCP signal is equal to or lower than a value defined by the three bit signals. The blanking circuit 58 is configured to interrupt a signal supplied from the luminous pulse width control circuit 56 to the driver 32 in response to a BK (blanking) signal, and to preferentially place the driver 32 in the off state.
Referring to the time chart of
As shown in the time chart of
In the aforementioned first period K1 in the prior luminous control period, the indicative data supply means 64 divides 6-bit luminous data D defining 64 intensity level luminance of the predetermined light-emitting element 22 in the present luminous control period, into the upper digit bits b5 to b3 and the lower digit bits b2 to b0, and at first supplies the signals of the upper digit bits b5 to b3 to the first, second and third input terminals 36, 38, 40, respectively. The supplied signals of the upper digit bits b5 to b3 are stored in the first, second and third shift registers 42, 44, 46, in synchronization with supplying the CLK signal. Then, the indicative data supply means 64 supplies the remaining signals of the lower digit bits b2 to b0 to the first, second and third input terminals 36, 38, 40, respectively. The supplied signals of the lower digit bits b2 to b0 are stored following the signals of the upper digit bits b5 to b3 in the first, second and third shift registers 42, 44, 46, in synchronization with supplying the CLK signal. In the present luminous control period, the indicative data supply means 64 divides the luminous data D for lighting in the following luminous control period as well, serially supplies the upper digit bits b5 to b3 and the lower digit bits b2 to b0 to the first, second and third input terminals 36, 38, 40, respectively, and has them serially stored in the first, second and third shift registers 42, 44, 46.
The timing control means 60 generates the first LAT signal (at point t2) during generation of the aforementioned first BK signal, and generates the second LAT signal (at point t11) during generation of the aforementioned second BK signal. By generation of the first LAT signal, the upper digit bits b5 to b3 of the luminous data D stored in the first, second and third shift registers 42, 44, 46 are latched in the first, second and third latch circuit 48, 50, 52, the upper digit bits b5 to b3 of the luminous data D latched in the first, second and third latch circuit 48, 50, 52 are supplied to the luminous pulse width control circuit 56 until supply of the second LAT signal.
When the timing control means 60 has the first BK signal fallen (at point t3), the grid switching means 62 applies the control voltage to the grid G to light the predetermined light-emitting element 22 until the following luminous control period starts. Concurrently, the first period luminous control means 68 of the luminous control means 66 supplies the first GCP signal to the pulse width control signal generating circuit 54, and then, the first GCP signal is converted into the 3-bit parallel signal and the converted signal is supplied from the pulse width control signal generating circuit 54 to the luminous pulse width control circuit 56. The first GCP signal is a function of time which presents such that a value is steppingly reduced by a predetermined value as “56”, “48”, “40”, “32”, “24”, “16”, “8” and “0” at seven equal intervals of time in the first period K1. In an example shown in
When the timing control means 60 raises the second BK signal (at point t10) and generates the second LAT signal (at point t11) during raising of the second BK signal, the generation of the second LAT signal causes the signals of the lower digit bits b2 to b0 of the luminous data D stored in the first, second and third shift registers 42, 44, 46 to be latched in the first, second and third latch circuit 48, 50, 52, the signals of the lower digit bits b2 to b0 of the luminous data D latched in the first, second and third latch circuit 48, 50, 52 is supplied to the luminous pulse width control circuit 56 until the first LAT signal of the following luminous control period is supplied. Concurrently, the second period luminous control means 70 of the luminous control means 66 supplies the second GCP signal to the pulse width control signal generating circuit 54, and then, the second GCP signal is converted into the 3-bit parallel signal and the converted signal is supplied from the pulse width control signal generating circuit 54 to the luminous pulse width control circuit 56. The second GCP signal is a function of time which presents such that a value is steppingly reduced in a period of one seventh of the first period, that is, the duration of the first GCP signal by a predetermined value as “7”, “6”, “5”, “4”, “3”, “2”, “1” and “0” at seven equal intervals of time in the second period. In an example shown in
Since drive voltages that are luminous pulses corresponding to the on states of the driver 32 in the first and second periods K1, K2 are applied to the light-emitting element 22, the element 22 is driven in a duty ratio corresponding to the intensity level “37” defined by the aforementioned luminous data D, and the element 22 is lighted in the intensity level “37” defined by the luminous data D.
Also in this embodiment, the control routine goes along with the flowchart as well as that in
According to the present embodiment, the indicative data D that are defining “64” intensity levels more than “8” intensity levels defined by three (3) bits corresponding to the number of the input terminals 36, 38, 40, are divided into the upper digit bits b5 to b3 and the lower digit bits b2 to b0, and they are alternately supplied to the first, second and third input terminals 36, 38, 40, in the first period K1 set within the luminous control period that is repeatedly assigned to a predetermined light-emitting element 22 selected from the plurality of light-emitting elements, the predetermined light-emitting element 22 is lighted in a relatively roughly-set intensity level corresponding to the upper digit bits b5 to b3 by supplying the indicative data of the upper digit bits b5 to b3 to the first, second and third input terminals 36, 38, 40, and, furthermore, in the second period determined as shorter than the first period, the predetermined light-emitting element 22 is lighted in a relatively finely-set intensity level corresponding to the lower digit bits b2 to b0 by supplying the indicative data of the lower digit bits b2 to b0 to the first, second and third input terminals 36, 38, 40. Accordingly, since the display drive control circuit 30 including the fewer input terminals 36, 38, 40 than the value of bits defining the intensity level of the aforementioned indicative data D and the following parallel signal processing circuits (the first, second and third shift registers 42, 44, 46 and the first, second and third latch circuits 48, 50, 52) is sufficient, even if the value of the intensity level increases, a small-sized display drive control circuits 30 can be provided at a reasonable cost.
According to the present embodiment, it is provided the image display apparatus wherein (a) the first period luminous control means 68 supplies a first GCP signal defining a value steppingly reduced along with time elapsing in the first period, to the first, second and third input terminals 36, 38, 40; (b) the second period luminous control means 70 supplies a second GCP signal defining a value steppingly reduced along with time elapsing in the second period, to the first, second and third input terminals 36, 38, 40; and (c) the display drive control circuit 30 includes a luminous pulse width control circuit 56 configured to compare the first GCP signal and the upper digit bits b5 to b3, and outputs a comparison signal during that the value defined by the upper digit bits b5 to b3 exceeds that of the first GCP signal, and to compare the second GCP signal and the lower digit bits b2 to b0, and outputs a comparison signal during that the value defined by the lower digit bits b2 to b0 exceeds that of the second GCP signal, and a driver (drive circuit) 32 configured to output a luminous pulse to light the light-emitting element 22 in response to an output of the comparison signal from the luminous pulse width control circuit 56. Consequently, during the summed period of the first period from the output of the comparison signal to the termination of the first period and the second period from the output of the comparison signal to the termination of the second period, the light-emitting element 22 is lighted, and it corresponds to the intensity level defining the indicative data D.
According to the present embodiment, it is provided the image display apparatus wherein (a) the plurality of light-emitting elements 22 disposed are fluorescent bodies that are disposed on a positive electrode of a fluorescence display tube 12 and are configured to light by collision of an electron generated in a cathode of the fluorescence display tube 12 and accelerated through any of a plurality of control grids Gn; and (b) the luminous control period assigned to the predetermined light-emitting element 22 is a period in which an accelerated voltage is applied to a control grid G covering the predetermined light-emitting element 22 selected from the control grids Gn; and the apparatus further includes (c) a grid switching means 62 for serially selecting a light-emitting element capable of emitting light from the plurality of light-emitting elements 22 disposed, by serially and repeatedly applying a control voltage pulse to the plurality of control grids Gn. Consequently, the fluorescent body of the fluorescence display tube 12 is displayed in the intensity level of the indicative data D by fewer display drive control circuits 30 than the number of the bits defining the intensity level of the indicative data D. The display drive control circuits 30 includes the first, second and third input terminals 36, 38, 40 and the parallel signal processing circuits (the first, second and third shift registers 42, 44, 46 and the first, second and third latch circuits 48, 50, 52) connected to the input terminals.
According to the present embodiment, it is provided the image display apparatus wherein the grid switching means 62 serially and repeatedly applies one control voltage pulse having a time width corresponding to the first period and the following second period to the plurality of control grids Gn. Consequently, the light-emitting element 22 is displayed in the intensity level of the indicative data D by fewer display drive control circuits 30 than the number of the bits defining the intensity level of the indicative data D. The display drive control circuits 30 includes the first, second and third input terminals 36, 38, 40 and the parallel signal processing circuits (the first, second and third shift registers 42, 44, 46 and the first, second and third latch circuits 48, 50, 52) connected to the input terminals.
In the display drive control circuit 30 of the present embodiment, the indicative data D is divided into two groups, that is, the upper digit bits b5, b4, b3 and the lower digit bits b2, b1, b0 and they are to be alternately input to the first, second and third input terminals 36, 38, 40, since the intensity level defined by the lower digit bits b2, b1, b0 has a narrow width for representing the intensity level, the second period K2 between the second BK signal SB2 and the first BK signal SB1 is short and one eighth (⅛) of the indicative cycle in the 64 intensity levels with regard to the intensity level indicative control, however, when the lower digit bits b2, b1, b0 are supplied through the first, second and third input terminals 36, 38, 40 to the first, second and third shift registers 42, 44, 46 to be serially stored, a relatively long duration as well as the second indicative data supply period TD2 in
There will be described in detail another embodiment of the present invention. In the following descriptions, the same reference signs are assigned to the common components to the above and below embodiments and the description on them will be omitted.
While the preferred embodiment of this invention has been described above in detail by reference to the drawings, it is to be understood that the invention may be otherwise embodied.
In the aforementioned Example 1, for instance, in the luminous control period in which the control voltage is applied to one unit of grids to light the light-emitting element 22 in the one grid scanning, there are set the first period K1 for the first scanning to generate the luminous pulse corresponding to the intensity level defined by the first bit group including b5, b1, b0 of the defined data D, and the second period K2 for the second scanning to generate the luminous pulse corresponding to the intensity level defined by the second bit group including b4, b3, b2 of the defined data D. Or the second period K2 for the lower scanning may be conducted for one picture after the first period K2 for the upper scanning is conducted for one picture.
In the aforementioned Example 1, the second period K2 is set following the first period K1 within one luminous control period as shown in
In the aforementioned Example 1, the indicative data D for displaying in 64 intensity levels is divided into the 3-bit first bit group including b5, b1, b0 and the 3-bit second bit group including b4, b3, b2. For instance, the indicative data D for displaying in 128 intensity levels may be divided into the 3-bit first bit group including b6, b1, b0 and the 4-bit second bit group including b5, b4, b3, b2. It is not necessarily required that the first bit group and second bit group have equal number of bits functioning as the indicative data D.
In the aforementioned Example 1, the indicative data D is divided into the 3-bit first bit group of b5, b1, b0 including the uppermost digit bit b5 and the lowermost digit bit b0 and the second bit group of b4, b3, b2 including intermediate bits between the uppermost digit bit and the lowermost digit bit, selected from the bit strings b5, b4, b3, b2, b1, b0 in order constituting the indicative data D. Or the first bit group may be constituted of b5, b2, b0 and the second bit group may be constituted of b4, b3, b1, or the first bit group may be constituted of b5, b3, b0 and the second bit group may be constituted of b4, b2, b1. That is, it is sufficient that the first bit group ensures the first indicative data supply period TD1 in the first period K1 and the second bit group ensures the second indicative data supply period TD2 in the second period K2. Consequently, it is sufficient that the indicative data D is divided into the first bit group including a plurality of bits which constitute each of the bit strings and are positioned in non-successive order in the bit string, selected from the bit strings constituting the indicative data D, and the second bit group including a plurality of bits which are not included in the first bit group.
In the aforementioned Example 1, the fluorescence display tube 12 functioning as the image display device is provided in the image display apparatus 10. Or an LED image display device in which a plurality of LED chips disposed on a surface of the substrate and operating in the simple matrix drive are used for displaying images, is available. An LCD image display device operating in the simple matrix drive is available as the image display device.
In the aforementioned Example 1, the first period luminous control means 68 outputs the first GCP signal SG1 steppingly reducing along with time elapsing in the first period K1; the second period luminous control means 70 outputs a second GCP signal SG2 steppingly reducing along with time elapsing in the second period K2; and the luminous pulse width control circuit 56 compares the first GCP signal SG1 steppingly reducing along with time elapsing and the first bit group including b5, b1, b0 in the first period K1, and outputs the comparison signal when the first GCP signal SG1 is equal to or lower than a value defined by the first bit group including b5, b1, b0, and compares the second GCP signal SG2 steppingly reducing along with time elapsing and the second bit group including b4, b3, b2 in the second period K2, and outputs the comparison signal when the second GCP signal SG2 is equal to or lower than a value defined by the second bit group including b4, b3, b2. Or it is also available to proceed such that the first period luminous control means 68 outputs the first GCP signal SG1 steppingly increasing along with time elapsing in the first period K1; the second period luminous control means 70 outputs a second GCP signal SG2 steppingly increasing along with time elapsing in the second period K2; and the luminous pulse width control circuit 56 compares the first GCP signal SG1 steppingly increasing along with time elapsing and the first bit group including b5, b1, b0 in the first period K1, and outputs the comparison signal when the first GCP signal SG1 exceeds a value defined by the first bit group including b5, b1, b0, and compares the second GCP signal SG2 steppingly increasing along with time elapsing and the second bit group including b4, b3, b2 in the second period K2, and outputs the comparison signal when the second GCP signal SG2 exceeds a value defined by the second bit group including b4, b3, b2. In this case, during the summed period of the first period K1 from the initiation of the first period K1 to the output of the comparison signal and the second period K2 from the initiation of the second period K2 to the output of the comparison signal, the light-emitting element 22 is lighted, and it corresponds to the intensity level defining the indicative data. The driver (drive circuit) 32 puts out the light-emitting element 22 in response to the comparison signal. Such a variation is applicable not only to the Example 1 but to the Example 2.
In such as the aforementioned Examples 1 and 2, in the luminous control period in which the control voltage is applied to one unit of grids to light the light-emitting element 22 in the one grid scanning, there are set the first period for the upper digit scanning to generate the luminous pulse corresponding to the intensity level defined by the upper digit bits of the defined data D, and the second period for the lower digit scanning to generate the luminous pulse corresponding to the intensity level defined by the lower digit bits of the defined data D. Or the second period for the lower scanning may be conducted for one picture after the first period for the upper scanning is conducted for one picture.
In the aforementioned Examples, the fluorescence display tube 12 functioning as the image display device is provided in the image display apparatus 10. Or an LED image display device in which a plurality of LED chips disposed on a surface of the substrate and operating in the simple matrix drive are used for displaying images, is available. An LCD image display device operating in the simple matrix drive is available as the image display device.
It is to be understood that the present invention may be embodied with other changes, improvements, and modifications that may occur to a person skilled in the art without departing from the scope and spirit of the invention defined in the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2007-121320 | May 2007 | JP | national |
| 2008-019757 | Jan 2008 | JP | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP2008/058339 | 5/1/2008 | WO | 00 | 11/25/2009 |
