BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a circuit diagram showing one example of an existing pixel circuit;
FIG. 2 is a block diagram showing an image display according to a related art;
FIG. 3 is a circuit diagram showing a pixel circuit included in the image display shown in FIG. 2;
FIG. 4 is a timing chart for explaining the operation of the image display according to the related art shown in FIG. 2;
FIG. 5 is another timing chart for explaining the operation of the image display according to the related art;
FIG. 6 is a block diagram showing an image display according to a first embodiment of the present invention;
FIG. 7 is a timing chart for explaining the operation of the first embodiment;
FIG. 8 is a block diagram showing an image display according to a second embodiment of the invention;
FIG. 9 is a timing chart for explaining the operation of the second embodiment;
FIG. 10 is a block diagram showing an image display according to a third embodiment of the invention;
FIG. 11 is a timing chart for explaining the operation of the third embodiment;
FIG. 12 is a timing chart for explaining the operation of a fourth embodiment of the invention;
FIG. 13 is a block diagram showing an image display according to a fifth embodiment of the invention;
FIG. 14 is a timing chart for explaining the operation of the fifth embodiment;
FIG. 15 is a circuit diagram showing a configuration example of a flip-flop included in the fifth embodiment;
FIG. 16 is a block diagram showing an image display according to a sixth embodiment of the invention;
FIG. 17 is a circuit diagram showing a pixel circuit in the sixth embodiment;
FIG. 18 is a timing chart for explaining the operation of the sixth embodiment;
FIG. 19 is a timing chart showing a reference example for comparison with the fourth embodiment; and
FIG. 20 is a timing chart showing a modification of the fourth embodiment.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. Initially, to clarify the background of the present invention, an image display according to a related art as a basis of the present invention will be described below with reference to FIG. 2. Details of this image display according to the related art are disclosed in Japanese Patent Application No. 2005-027028 by the present assignee. A large part of the image display according to the related art is in common with image displays according to embodiments of the present invention, and therefore the image display according to the related art will be described below as a part of the present invention. As shown in FIG. 2, the image display is formed of a pixel array 1 and a peripheral circuit part. The pixel array 1 includes pixel circuits 2 arranged in rows and columns and serves as a screen. The peripheral circuit part includes four scanners 4, 5, 71, and 72 to line-sequentially scan the pixel array 1. Furthermore, the peripheral circuit part includes a horizontal driver 3 for supplying video signals to the pixel array 1.
Each pixel circuit 2 is disposed at the intersection between a row scan line WS and a column signal line SL. FIG. 2 shows only one pixel circuit 2 for easy understanding. The signal line SL is connected to the horizontal driver 3. The scan line WS is connected to the write scanner 4. The image display includes, besides the scan line WS for signal sampling, additional scan lines DS, AZ1, and AZ2. These scan lines DS, AZ1, and AZ2 are disposed in parallel to the sampling scan line WS. The scan line DS is connected to the drive scanner 5 and controls the light emission period. The scan line AZ1 is connected to the first correction scanner 71 and used for reference potential setting operation. The scan line AZ2 is connected to the second correction scanner 72 and used for initialization operation.
The pixel circuit 2 includes five transistors T1, T2, T3, T4, and Td, one pixel capacitor Cs, and one light-emitting element OLED. In the present example, all the transistors are N-channel transistors. However, the present invention is not limited thereto. The pixel circuit can be formed by adequately mixing N-channel transistors and P-channel transistors. The gate of the drive transistor Td is connected to a node A. The source thereof is connected to a node B. The drain thereof is connected via the switching transistor T4 to a power supply line Vcc. The sampling transistor T1 is connected between the signal line SL and the node A. The gate of the sampling transistor T1 is connected to the scan line WS. The transistor T2 for setting to a reference potential (hereinafter, referred to as “reference potential setting transistor T2”) is connected between the node A and a predetermined reference potential Vofs. The gate thereof is connected to the scan line AZ1. The initialization transistor T3 is connected between the node B and a predetermined initialization potential Vini. The gate thereof is connected to the scan line AZ2. The switching transistor T4 is connected between the power supply line Vcc and the drive transistor Td. The gate thereof is connected to the scan line DS. The pixel capacitor Cs is connected between the nodes A and B. In other words, the pixel capacitor Cs is connected between the gate and source of the drive transistor Td. The light-emitting element OLED is formed of a two-terminal device such as an organic EL element. The anode thereof is connected to the node B, while the cathode thereof is connected to the ground. An equivalent capacitor Coled of the light-emitting element OLED is also shown in the drawing.
As shown in the drawing, this image display employs the following four scanners in order to line-sequentially scan the pixel array 1: the write scanner 4, the drive scanner 5, the first correction scanner 71, and the second correction scanner 72. This correspondingly causes increase in the manufacturing costs.
FIG. 3 schematically shows only the pixel circuit 2 extracted from the pixel array 1 shown in FIG. 2.
FIG. 4 is a timing chart for explaining the operation of the image display shown in FIG. 2. FIG. 4 shows the waveforms of control signals that are line-sequentially output from the respective scanners 4, 5, 71, and 72. In FIG. 4, each of the control signals (gate selection pulses) applied to the corresponding scan line is indicated by the same symbol as that of the corresponding scan line for easy understanding. Specifically, the control signal for sampling applied to the sampling scan line WS is also indicated by symbol WS, and the control signal for initialization applied to the initialization scan line AZ2 is also indicated by symbol AZ2. Furthermore, the control signal for setting to the reference potential, applied to the scan line AZ1, is also indicated by symbol AZ1. In addition, the control signal applied to the scan line DS is also indicated by symbol DS. In addition to the waveforms of these control signals, the potential changes at the nodes A and B are also indicated in FIG. 4. The potential change at the node A indicates the change of the gate potential of the drive transistor Td. The potential change at the node B indicates the potential change at the source of the drive transistor Td.
The respective scanners 4, 5, 71, and 72 shown in FIG. 2 output the corresponding control signal in a time-series manner, so that the operations of steps 0 to 3 are sequentially carried out. In the timing chart of FIG. 4, each step is represented as a number surrounded by a circle. At first, initialization operation is carried out in the step 0. Subsequently, Vth cancel operation is carried out in the step 1. Furthermore, signal write operation (sampling operation) is carried out in the step 2, followed by light emission operation in the step 3. The steps 0 to 3 are line-sequentially carried out in each one field, so that an image of one field is displayed on the pixel array 1.
In the initialization step 0, the control signal AZ2 is at the high level, and hence the N-channel transistor T3 is in the on-state. Thus, the source potential of the drive transistor Td becomes the initialization potential Vini. Subsequently, in the Vth cancel step 1, the control signals AZ1 and DS are at the high level, and hence the N-channel transistors T2 and T4 are in the on-state. As a result, the gate potential of the drive transistor Td becomes the reference potential Vofs. Because the potentials are set to satisfy the relationship Vofs−Vini>Vth, a current flows through the drive transistor Td and the source potential rises from the potential Vini. When the voltage between the gate and source of the drive transistor Td has become equal to the threshold voltage Vth, the flow of the drain current through the drive transistor Td stops, and therefore the voltage equal to the threshold voltage Vth is held in the pixel capacitor Cs.
Thereafter, in the signal write step S2, the control signal WS is kept at the high level, and thus the sampling transistor T1 is in the on-state, which allows a video signal potential Vsig to be sampled from the signal line SL. At this time, the source potential of the drive transistor Td is substantially the same as that in the step 1 because the capacitance of the equivalent capacitor Coled of the light-emitting element OLED is sufficiently higher than that of the pixel capacitor Cs. Consequently, a voltage of ΔVsig+Vth is held in the pixel capacitor Cs. The voltage LVsig satisfies the relationship ΔVsig=Vsig−Vofs.
Thereafter, when the operation sequence enters the light emission period in the light emission step 3, the control signal DS is turned to the high level again, which turns on the switching transistor T4. This connects the drive transistor Td to the power supply line Vcc, so that the drain current Ids flows into the light-emitting element OLED. As a result, due to the internal resistance of the light-emitting element OLED, the anode potential Vanode thereof (i.e., the source potential of the drive transistor) rises. At this time, the voltage written to the pixel capacitor Cs is kept as it is due to bootstrap operation, and thus the gate potential of the drive transistor Td also rises in linkage with the rise of the potential Vanode. That is, during the light emission period, a constant voltage of AVsig+Vth is applied between the gate and source of the drive transistor Td.
The drain current that flows through the drive transistor Td during the light emission period in the step 3 is given by Equation 1, and therefore is expressed as Equation 2. As is apparent from Equation 2, the drain current Ids does not depend on the threshold voltage Vth of the drive transistor Td.
FIG. 5 shows an example in which operation for correcting variation in the mobility μ of the drive transistors is added to the above-described threshold voltage correction operation. The timing chart of FIG. 5 employs the same representation manner as that of the timing chart of FIG. 4 for easy understanding. In this example, a mobility correction step 3 is carried out in the latter half of the signal write step 2. The mobility correction step 3 is followed by a light emission step 4. In the mobility correction step 3, the control signal DS is kept at the high level with the control signal WS kept at the high level. Therefore, the drain current flows through the drive transistor Td, which raises the source potential thereof by ΔV. On the other hand, the gate potential of the drive transistor Td is fixed at Vsig. As a result, the voltage Vgs of the drive transistor Td decreases by ΔV. The larger the current that flows through the drive transistor Td is, the higher the degree of the voltage decrease ΔV is. In other words, as is apparent from Equation 1 as a transistor characteristic equation, a higher mobility μ of the drive transistor Td yields a larger voltage decrease ΔV. The control signal WS is turned to the low level at the end of the step 3 and thus the operation sequence proceeds to the light emission operation of the step 4. The larger the voltage decrease ΔV is, the lower the level of the output current supplied to the light-emitting element OLED in the step 4 is. That is, negative feedback is carried out corresponding to the voltage decrease ΔV. Consequently, even when there is variation in the mobility μ of the drive transistor Td among the respective pixel circuits, this negative feedback on each pixel circuit basis can alleviate luminance unevenness attributed to the variation in the mobility.
This is the end of the description of the image display according to the related art as a basis of the present invention. Next, image displays according to embodiments of the present invention will be described below. FIG. 6 is a block diagram showing an image display according to a first embodiment of the present invention. The same parts in FIG. 6 as those in the image display according to the related art shown in FIG. 2 are given the same numerals for easy understanding. FIG. 6 shows the pixel circuit 2 on the n-th row in particular. To clearly indicate this, symbol n is added to the symbol of the scan line WS for sampling, so that this sampling scan line is indicated by symbol WSn. Similarly, the other scan lines are also given symbol n so as to be indicated by symbols DSn and AZ2n in order to clearly indicate that this pixel circuit 2 is on the n-th row.
The feature of the present embodiment is that the first correction scanner 71 is absent and the scan line AZ1n corresponding thereto is also absent. Instead of the scan line AZ1n, the scan line WSn-k is disposed in parallel to the sampling scan line WSn. That is, the reference potential setting transistor T2 is controlled by the sampling scan line WSn-k. This scan line WSn-k arises from branching of the sampling scan line WS on the (n−k)-th row from the top along the scan direction. In the present embodiment, k denotes a positive integer number and the scan direction is set to the downward direction. Thus, turning of the sampling scan line WSn-k to the high level is previous to turning of the sampling scan line WSn on the n-th row to the high level. In this manner, in the first embodiment, the need for the first correction scanner is eliminated through sharing of the write scanner 4 by the sampling transistor T1 and the reference potential setting transistor T2. Thereby, the number of the scanners necessary for the line-sequential scanning of the pixel array 1 is reduced to three from four in the related art example.
FIG. 7 is a timing chart for explaining the operation of the first embodiment shown in FIG. 6. For easy understanding, the timing chart of FIG. 7 employs the same representation manner as that of the timing chart of FIG. 5 for explaining the operation of the image display according to the related art. As is apparent from the timing chart, the control signal WSn-k is turned to the high level prior to turning of the write control signal WSn on the n-th row to the high level. Therefore, the Vth cancel step 1 can be carried out prior to the signal write step 2. This eliminates the need for the scanner dedicated to the reference potential setting transistors T2, and thus permits simplification and cost reduction of the image display. According to the timing chart of FIG. 7, mobility variation correction is carried out in the step 3. However, the execution of the step 3 is optional, and embodiments of the present invention are effective no matter whether the step 3 is carried out or not. Also in other embodiments to be described below, the mobility variation correction step 3 is carried out. However, the present invention is not necessarily limited thereto but this step 3 may be omitted.
FIG. 8 is a block diagram showing an image display according to a second embodiment of the present invention. The same parts in FIG. 8 as those in the first embodiment shown in FIG. 6 are given the same numerals for easy understanding. The feature of the second embodiment is that the initialization transistor T3 is controlled by the write scan line WSn-m, i.e., by the write scan line WS on the (n−m)-th row from the top. This eliminates the need for the second correction scanner for controlling the initialization transistors T3, and thus can reduce the total number of the scanners to three.
FIG. 9 is a timing chart for explaining the operation of the image display according to the second embodiment shown in FIG. 8. The timing chart of FIG. 9 employs the same representation manner as that of the timing chart of FIG. 7 for the first embodiment for easy understanding. As shown in FIG. 9, first the control signal WSn-m is turned to the high level, and thereafter the control signals AZln, DSn, and WSn are turned to the high level in that order, so that the steps 0 to 4 are sequentially carried out. In the present embodiment, m denotes a positive integer number and the scan direction is set to the downward direction. Thus, turning of the write scan line WSn-m to the high level is previous to turning of the write scan line WSn to the high level as shown in the timing chart. The initialization step 0 is carried out through the turning of this preceding sampling control signal WSn-m to the high level, so that the source potential of the drive transistor Td is initialized to the potential Vini. Because the scanner dedicated to the initialization transistors T3 is unnecessary, simplification and cost reduction of the image display are possible.
FIG. 10 is a block diagram showing an image display according to a third embodiment of the present invention. The same parts in FIG. 10 as those in the first embodiment shown in FIG. 6 are given the same numerals for easy understanding. The feature of the embodiment of FIG. 10 is that the reference potential setting transistor T2 is controlled by the write scan line WSn-k, i.e., by the write scan line WS on the (n−k)-th row from the top, and the initialization transistor T3 is controlled by the write scan line WSn-m, i.e., by the write scan line WS on the (n−m)-th row from the top. This feature allows the number of the scanners to be reduced by two.
FIG. 11 is a timing chart for explaining the operation of the third embodiment shown in FIG. 10. The timing chart of FIG. 11 employs the same representation manner as that of the timing chart of FIG. 7 for the first embodiment for easy understanding. The control signals WSn-m, WSn-k, and WSn are sequentially output from the write scanner 4. In the present embodiment, k denotes a positive integer number and m denotes a positive integer number larger than k, and the scan direction is set to the downward direction. Thus, turning of the write scan line WSn-k to the high level is previous to turning of the write scan line WSn assigned to the n-th row to the high level. Furthermore, turning of the write scan line WSn-m to the high level is previous to the turning of the write scan line WSn-k to the high level. When the control signal WSn-m is turned to the high level first, the initialization step 0 is carried out, so that the source potential of the drive transistor Td is initialized to the potential Vini. Subsequently, in the Vth cancel step 1, the control signal WSn-k is kept at the high level, so that the gate potential of the drive transistor Td is set to the reference potential Vofs. Because the control signal DSn is turned to the high level in this state, the threshold voltage Vth of the drive transistor Td is written to the pixel capacitor Cs. Thereafter, the scan line WSn on the n-th row is turned to the high level in the signal write step 2, and thus the video signal Vsig is written to the pixel capacitor Cs. The Vth cancel operation can be carried out by utilizing a preceding write control signal in this manner. Because the dedicated scanners for the initialization transistors and the reference potential setting transistors are unnecessary, simplification and cost reduction of the image display are possible.
FIG. 12 is a timing chart showing the operation of an image display according to a fourth embodiment of the present invention. The circuit configuration of the present embodiment is the same as that of the third embodiment shown in FIG. 10. However, the waveforms of the control signals in the fourth embodiment are different from those in the third embodiment, and correspondingly the timing chart of FIG. 12 is different from the timing chart of FIG. 11. Specifically, in the third embodiment shown in FIG. 11, the selection period of the write scan line WS is set to one horizontal scanning period (1H). In contrast, in the fourth embodiment, the selection period of the write scan line WS is set to a period longer than 1H. That is, the width of the control signal (selection pulse) applied to each write scan line WS from the write scanner is larger than 1H. As a result, the pulse width of the initialization control signal WSn-m used in the initialization step 0 is also larger than 1H. Therefore, a period longer than 1H can be ensured as the initialization period for the drive transistor Td, and thus the source potential of the drive transistor Td can be initialized to the potential Vini more surely. This allows the Vth cancel operation in the Vth cancel step 1 to be carried out more accurately.
In the timing charts of FIG. 11 and so on, m and k denote positive integer numbers satisfying the relationship m>k. Typically m and k are set to 2 and 1, respectively. Specifically, according to this setting, the reference potential setting transistor T2 is controlled by the scan line WSn-1 on the previous row of this transistor T2, and the initialization transistor T3 is controlled by the scan line WSn-2 on the further previous row.
However, it should be noted that this setting is not necessarily available in the case of the timing chart of FIG. 12. Specifically, the selection period of the scan line is 2H in FIG. 12. Therefore, when m and k are 2 and 1, respectively, as shown in FIG. 19, the period during which both the reference potential setting transistor T2 and the sampling transistor T1 are in the on-state simultaneously exists. In this case, the signal line is short-circuited to the reference potential Vini and thus an inadequate through-current flows, which results in failure in normal Vth cancel operation.
For correct operation, it is required that the sampling transistor T1 be turned on after the reference potential setting transistor T2 has entered the off-state. Therefore, when the selection period of the scan line is 2H like in the embodiment of FIG. 12, the value of k needs to be two or more. When the selection period of the scan line is 3H or more, the value of k needs to be further increased depending on the selection period.
FIG. 20 shows a modification of the embodiment of FIG. 12. In this example, the Vth cancel operation is carried out over 2H, and hence the Vth cancel operation can be carried out more surely compared with in the example of FIG. 12. Also in this example, the value of k needs to be two or more for the same reason as that of the example of FIG. 12. Although a long period is unnecessary for the Vth cancel operation in some actual cases, it is preferable that the values of k and m be set to large values because larger k and m offer higher flexibility of the timing design, as shown in the present example.
FIG. 13 is a block diagram showing an image display according to a fifth embodiment of the present invention. Basically the fifth embodiment is similar to the third embodiment shown in FIG. 10, and therefore the same parts in FIG. 13 as those in FIG. 10 are given the same numerals for easy understanding. The difference of the fifth embodiment from the third embodiment is that the scan line AZ2n is used instead of the scan line WSn-m arising from branching of a scan line on a preceding row. This scan line AZ2n is controlled by the write scanner 4 via an SR flip-flop (SRFF) 41. A set terminal S of the SR flip-flop 41 is supplied with a control signal WSn-q, and a reset terminal R thereof is supplied with a control signal WSn-p.
FIG. 14 is a timing chart for explaining the operation of the fifth embodiment shown in FIG. 13. The timing chart of FIG. 14 employs the same representation manner as that of the timing chart of FIG. 11 for the third embodiment for easy understanding. As shown in FIG. 14, from the write scanner to the pixel circuit on the n-th row, initially the control signal WSn-q is output, and then the control signal WSn-p is output. Subsequently, the control signal WSn-k is output, and then finally the control signal WSn assigned to the n-th row is output. In the present embodiment, p denotes a positive integer number and q denotes a positive integer number larger than p, and the scan direction is set to the downward direction. Thus, as shown in the timing chart, the output of the SR flip-flop 41, i.e., the control signal AZ2n, is turned to the high level at the timing when the write scan line WSn-q is turned to the high level, and then is turned to the low level at the timing when the write scan signal WSn-p is turned to the high level. Depending on the way of selection of the values of p and q, the high-level period (i.e., the pulse width) of the control signal AZ2n can be optionally set to any period. Consequently, the initialization period of the initialization step 0 can be set to a sufficiently long period over 1H, and thus the initialization operation for the source of the drive transistor Td can be carried out more surely.
FIG. 15 is a circuit diagram showing a configuration example of the SR flip-flop 41 included in the image display of FIG. 13. The SR flip-flop 41 is formed by connecting a pair of N-channel transistors in series to each other between the power supply line Vcc and a ground line Vss. The output signal AZ2 is obtained from the connection node between the transistors. The gate of one transistor serves as the set terminal S and the control signal WSn-q is applied thereto. The gate of the other transistor serves as the reset terminal R and is supplied with the control signal WSn-p from the write scanner 4. The SR flip-flop 41 is composed only of N-channel transistors and therefore can be formed even by an amorphous-silicon process.
FIG. 16 is a block diagram showing an image display according to a sixth embodiment of the present invention. Basically the sixth embodiment is similar to the third embodiment shown in FIG. 10, and therefore the same parts in FIG. 16 as those in FIG. 10 are given the same numerals for easy understanding. The difference between the sixth and third embodiments is that in the sixth embodiment, the switching transistor T4 is absent and hence the pixel circuit 2 is formed of the total four transistors T1, T2, T3, and Td. That is, the number of the transistors as components is reduced to four from five, which can correspondingly contribute to yield improvement. To respond to the removal of the switching transistor T4, a power supply drive line DSn is disposed in the pixel circuit 2 instead of the simple power supply line Vcc. This power supply drive line DSn is controlled by the drive scanner 5 similarly to the scan line. The power supply drive line DSn supplies a supply voltage Vcc in each light emission period, so that the drive transistor Td, of which drain is connected to the corresponding power supply drive line DSn, supplies the output current Ids to the light-emitting element OLED depending on the supply voltage. The switching transistor T4 used in the third embodiment is connected between the drain of the drive transistor Td and the predetermined power supply line Vcc. During the light emission period, the switching transistor T4 conducts in response to the control signal DS so as to connect the drive transistor Td to the power supply line Vcc, so that the output current Ids flows through the light-emitting element OLED.
FIG. 17 is a circuit diagram showing only one pixel circuit extracted from the image display according to the sixth embodiment shown in FIG. 16.
FIG. 18 is a timing chart for explaining the operation of the image display according to the sixth embodiment shown in FIG. 16. The timing chart of FIG. 16 employs the same representation manner as that of the timing chart of FIG. 11 for the third embodiment for easy understanding. As shown in FIG. 18, in the Vth cancel step 1, the mobility variation correction step 3, and the light emission step 4, the power supply drive line DS is kept at the high level so as to supply the power necessary for the operation. During the other period, the power supply drive line DS is at the low level or in the high-impedance state, to thereby block the flow of the current through the drive transistor Td. This configuration can eliminate the need for the switching transistor T4. As for other respects, similarly to the above-described third embodiment, the scanners dedicated to the initialization transistors and the reference potential setting transistors are unnecessary, which allows simplification and cost reduction of the image display.
It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.
Patent Application
20070273620
