Image intensifiers are used in low light (e.g., night vision) applications to amplify ambient light into a more visible image.
An image intensifier may be degraded by internal stray light or ion feedback, which may originate from an anode device such as a phosphor screen or other sensor device.
A light intensifier includes a semiconductor structure to multiply electrons and block stray photons or ions (collectively referred to herein as “stray particles”). The semiconductor structure includes an electron multiplier region that is doped to generate a plurality of electrons for each electron that impinges a reception surface of the semiconductor structure, blocking regions that are doped to direct the plurality of electrons towards emissions areas of an emission surface of the semiconductor structure, and shielding regions that are doped to absorb stray particles that impinge the emission surface of the semiconductor structure and stop emission of the resulting electrons.
Disclosed herein are techniques to limiting effects of stray particles in semiconductor-based gain layer of an image intensifier.
Image intensifier 100 includes a photo-cathode 102 to convert photons 104 to electrons 106. Each photon 104 that impinges an input surface 102a has a probability to create a free electron 106. Free electrons 106 are emitted from an output surface 102b. Output surface 102b may be activated to a negative electron affinity state to facilitate the flow of electrons 106 from output surface 102b.
Photo-cathode 102 may be fabricated from a semiconductor material that exhibits a photo emissive effect, such as gallium arsenide (GaAs), GaP, GaInAsP, InAsP, InGaAs, and/or other semiconductor material. Alternatively, photo-cathode 102 may be a known Bi-alkali.
In an embodiment, a photo-emissive semiconductor material of photo-cathode 102 absorbs photons, which increases a carrier density of the semiconductor material, which causes the semiconductor material to generate a photo-current of electrons 106, which are emitted from output surface 102b.
Image intensifier 100 further includes a semiconductor structure 110 configured as an electron multiplier and shield to generate a plurality of free electrons 112 for each electron 106 that impinges a surface 110a of semi-conductor structure 110, and to absorb stray particles 114.
Semiconductor structure 110 may also be referred to herein as an electron multiplier, an electron amplifier, and/or an electron bombarded device (EBD). Semiconductor structure 110 may be configured to generate, for example and without limitation, several hundred free electrons 112 for each free electron 106 that impinges surface 110a.
Image intensifier 100 further includes an anode 118 to receive electrons 112 from semiconductor structure 110. Anode 118 may include a sensor to sense electrons 112 that impinge a surface 118a of anode 118. Anode 118 may include a phosphor screen to convert electrons 112 to photons. Anode 118 may include an integrated circuit having a CMOS substrate and a plurality of collection wells. In this example, electrons collected in the collection wells may be processed with a signal processor to produce an image, which may be provided to a resistive anode and/or an image display device.
Image intensifier 100 further includes a vacuum region 108 to facilitate electrons flow between photo cathode 102 and semiconductor structure 110.
Image intensifier 100 further includes a vacuum region 116 to facilitate electron flow between semiconductor structure 110 and anode 118.
Image intensifier 100 and/or portions thereof, may be configured as described in one or more examples below. Image intensifier 100 is not, however, limited to the examples below.
Image intensifier 100 further includes a bias circuit 150. In the example of
A peripheral surface of photo-cathode 102 may be coated with a conductive material, such as chrome, to provide an electrical contact to photo-cathode 102.
A peripheral surface of semiconductor structure 110 may be coated with a conducting material, such as chrome, to provide an electrical contact to one or more surfaces of semiconductor structure 110.
A peripheral surface of anode 118 may be coated with a conductive material, such as chrome, to provide an electrical contact to anode 118.
Image intensifier 100 may include a vacuum housing 130 to house photo-cathode 102, semiconductor structure 110, and anode 118.
Photo-cathode 102 and semiconductor structure 110 may be positioned such that output surface 102b of photo-cathode 102 is in relatively close proximity to input surface 110a of semiconductor structure 110 (e.g., less than approximately 10 millimeters, or within a range of approximately 100 to 254 microns).
Semiconductor structure 110 and anode 118 may be positioned such that emission surface 110b is in relatively close proximity to anode surface 118a. For example, if anode 118 includes an integrated circuit, the distance between emission surface 110b and anode surface 118a may be, without limitation, within a range of approximately 10 to 15 millimeters, or within a range of approximately 250 to 381 microns. If anode 118a includes a phosphor screen, the distance between emission surface 110b and sensor surface 118a may be, without limitation, approximately 10 millimeters.
Image intensifier 100, or portions thereof, may be configured as described in one or more examples below. Image intensifier 100 is not, however, limited to the examples below.
Semiconductor structure 200 is doped to generate a plurality of free electrons 204 for each free electron 201 that impinges a surface 200a of semiconductor structure 200.
Semiconductor structure 200 includes first and second regions 202 and 208, which are doped to direct the flow of electrons 204 to emission areas 210 of emission surface 202b. Emission areas 210 may be activated to a negative electron affinity state to facilitate electron flow from emission regions 210. Second region 208 may also be referred to herein as a background region.
First region 202 is doped to force electrons 204 away from input surface 200a into semiconductor structure 200, thus inhibiting recombination of electron-hole pairs at input surface 200a. Inhibiting recombination of electron-hole pairs at input surface 200a ensures that more electrons flow through semiconductor structure 200 to emission surface 200b, thereby increasing efficiency.
Region 208 (alone and/or in combination with region 202), may also be referred to herein as an electron multiplier region.
Semiconductor structure 200 further includes regions 212, which are doped to repel free electrons 204. Regions 212 may also be referred to herein as blocking structures 212. Blocking structures 212 define blocking areas 214 of emission surface 200b, where electron flow into and out of semiconductor structure 200 is inhibited. Blocking regions 212 may help to maintain spatial fidelity. Blocking structures 212 may provide other benefits and/or perform other functions. Semiconductor structure 200 may provide suitable electron multiplication without blocking structures 212. Thus, in an embodiment, blocking structures 212 are omitted.
Stray particles 222 that impinge emission surface 200b of semiconductor structure 200 may convert to free electrons and corresponding holes. Thereafter, the free electrons may be emitted from emission surface 200b to contact anode 118 (
In
Semiconductor structure 200 may further include a dielectric film 224 disposed over blocking areas 214, or a portion thereof.
Semiconductor structure 200 may include silicon and/or other semi conductive material such as, without limitation, gallium arsenide (GaAs).
In an embodiment, semiconductor structure 200 includes silicon and is relatively doped with a P-type dopant to generate a plurality of free electrons 204 for each free electron 201 that impinges a surface 200a of semiconductor structure 200. First doped region 202 may be doped with a P-type dopant such as boron or aluminum. First doped region 202 may be relatively heavily doped (e.g., 1019 parts per cubic centimeter). Second doped region 108 may be relatively moderately doped with a P-type dopant. Blocking structures 212 may be relatively heavily doped with a P-type dopant such as boron or aluminum (e.g., 1019 parts per cubic centimeter). Shields 220 may be doped with an N-type dopant, such as by diffusion or implanting.
Semiconductor structure 200 may have a thickness of, without limitation, approximately 20-30 microns). First doped region 128 may have a thickness T of approximately 10-15 nanometers. Blocking structures 212 may have a height H of approximately 24 microns.
A gap 240 may be provided between first doped region 202 and blocking structures 212. Gap 240 may be sized or dimensioned such that second doped region 212 does not interfere with the generation of electrons 204 at input surface 200a. This may provide semiconductor structure 200 with an effective electron multiplication area that equals or approaches 100% of an area of input surface 200a. Gap 240 may be, without limitation, approximately one micron.
Other suitable dopants, concentrations, dimensions, and/or semiconductor materials, such as GaAs, may be used, as will be readily apparent to one skilled in the relevant art(s).
In
Semiconductor structure 200 may be configured to generate, for example, several hundred electrons in each EBC 402 that receives an electron. The number of electrons emitted from emission areas 210 may thus be significantly greater than the number of electrons that impinge input surface 200a.
In the examples of
In the examples of
In the examples of
Each EBC 402 and associated emission area 210 corresponds to a region of input surface 200a (
At 702, a plurality of electrons is generated within a semiconductor structure, for each electron that impinges a reception surface of a semiconductor structure, such as described in one or more examples herein.
At 704, the plurality of electrons is repelled from blocking regions of the semiconductor structure that are doped to repel electrons, towards emissions areas of an emission surface of the semiconductor structure, such as described in one or more examples herein.
At 706, stray particles that impinge the emission surface of the semiconductor structure are absorbed within shielding regions of the semiconductor structure, such as described in one or more examples herein.
Techniques disclosed herein may be implemented with/as passive devices (i.e., with little or no active circuitry or additional electrical connections).
Techniques disclosed herein are compatible with conventional high temperature semiconductor processes and wafer scale processing, including conventional CMOS and wafer bonding processes.
Methods and systems are disclosed herein with the aid of functional building blocks illustrating functions, features, and relationships thereof. At least some of the boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries may be defined so long as the specified functions and relationships thereof are appropriately performed. While various embodiments are disclosed herein, it should be understood that they are presented as examples. The scope of the claims should not be limited by any of the example embodiments disclosed herein. While a particular embodiment of the present invention has been shown and described in detail, adaptations and modifications will be apparent to one skilled in the art. Such adaptations and modifications of the invention may be made without departing from the scope thereof, as set forth in the following claims.
Number | Name | Date | Kind |
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6836059 | Smith | Dec 2004 | B2 |
20040232403 | Sillmon | Nov 2004 | A1 |
20120112056 | Brucker | May 2012 | A1 |
20190088393 | Stresau | Mar 2019 | A1 |
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