Patent Application
20050018064
This application claims benefit of Japanese Application No. 2003-124309 filed in Japan on Apr. 28, 2003, the contents of which are incorporated by this reference.
1. Field of the Invention
The present invention relates to an image pick-up device of a multi-channel output system, with the multi channels having a uniform structure.
2. Description of the Related Art
An MOS solid-state image pick-up device adopts a multi-channel output system (multi-line output system) for simultaneously obtaining a plurality of video signal outputs in parallel therewith from a single image pick-up device, as a general method for obtaining a video signal at a high frame rate from an image pick-up device having millions of pixels.
Matrix-arranged pixels P11 to Pnn are divided into four areas. A divided-area-1 has an area ranging from P11 to Paa, a divided-area-2 has an area ranging from P1b to Pan, a divided-area-3 has an area ranging from Pb1 to Pna, and a divided-area-4 has an area ranging from Pbb to Pnn.
A vertical scanning circuit 5 drives pixels on first to a-th rows, and a vertical scanning circuit 6 drives pixels on b-th to n-th rows. Horizontal reading circuits 1 and 3 read pixels on first to a-th columns, and horizontal reading circuits 2 and 4 read pixels on b-th to n-th columns.
Signal outputs are obtained from the pixels arranged in the respective divided-area-1 to divided-area-4, that is, the signal outputs from the pixels P11 to Paa in the divided-area-1 are obtained by the horizontal reading circuit (also referred to as a horizontal scanning circuit) 1 and the vertical scanning circuit 5. The signal outputs from the pixels P1b to Pan in the divided-area-2 are obtained by the horizontal reading circuit 2 and the vertical scanning circuit 5. The signal outputs from the pixels Pb1 to Pna in the divided-area-3 are obtained by the horizontal reading circuit 3 and the vertical scanning circuit 6. The signal outputs from the pixels Pbb to Pnn in the divided-area-4 are obtained by the horizontal reading circuit 4 and the vertical scanning circuit 6.
By the way, in the device with the above structure, the video signals in each of the divided-area-i to divided-area-4 pass through signal processing systems individually comprising a scanning circuit and a video signal processing unit. Thus, the differences of electric property among the signal processing systems cause the variation in signal level. Consequently, the quality of the finally-combined one image degrades.
Then, Japanese Unexamined Patent Application Publication No. 2000-209503 (Patent Document 1) discloses the suggestion to solve the above-mentioned problem.
The pixel arrangement of the image pick-up device shown in
Respective horizontal reading circuits 15 to 18 read the pixels in the divided-area-1 to divided-area-4. For example, the signals of the pixels Paa and Pbb are outputted from the entire horizontal reading circuits 15 to 18. The signals of the pixels Pa1 and Pb1 are outputted from both of the horizontal reading circuits 15 and 17. The outputs from the overlappingly-read pixels are averaged, thus to average the property variation in horizontal reading circuits at the boundary of the divided areas and to improve the image deterioration.
According to the present invention, an image pick-up device includes a pixel portion having the matrix arrangement of pixels corresponding to respective intersecting points between a plurality of signal lines arranged in a first direction and second direction, the pixel portion converting a subject image to an electric signal, and a scanning unit comprising a first scanning circuit for selecting a pixel position in a first direction of the matrix in the pixel portion and a second scanning circuit for selecting a pixel position in a second direction intersecting at the first direction, at least one of the first scanning circuit and the second scanning circuit having respectively a plurality of sub-scanning circuits for outputting a video signal, the plurality of sub-scanning circuits sharing the respective signal lines. Further, the image pick-up device includes a scanning control circuit for controlling the first scanning circuit and the second scanning circuit.
The above and other objects, features and advantages of the invention will become more clearly understood from the following description referring to the accompanying drawings.
Hereinbelow, the embodiments of the present invention will be described with reference to the drawings.
The solid-state pick-up device shown in
A pixel area 21 comprises pixels P1a to P5e arranged in a matrix. Each pixel Puv (1≦u≦5 and a≦v≦e in
According to the first embodiment, the respective divided areas which are adjacent in the vertical and horizontal directions include a common pixel. That is, the divided-area-1 has pixels P1a to P3c, the divided-area-2 has pixels P1c to P3e, the divided-area-3 has pixels P3a to P5c, and the divided-area-4 has pixels P3c to P5e. Pixels shown by dotted patterns in
According to the first embodiment, the pixels on the same row are respectively connected to two common row selecting lines φVu1 and φVu2. The row selecting lines φVu1 and φVu2 supply row selecting signals to the two switches SWuv
A vertical sub-scanning circuit 26 supplies the row selecting signal to the row selecting line φVu1. A vertical sub-scanning circuit 27 supplies the row selecting signal to the row selecting line φVu2. According to the first embodiment, the vertical sub-scanning circuits 26 and 27 have the same structure and have a pulse transfer unit and an output terminal corresponding to the respective rows in the pixel area. The each output terminal of the vertical scanning circuit 26 is connected to the row selecting line φVu1. The each output terminal of the vertical sub-scanning circuit 27 is connected to the respective row selecting line φVu2. The vertical scanning control circuit 24 supplies a vertical start pulse φVST and a vertical reset pulse φVRST to the vertical sub-scanning circuits 26 and 27 so that the row selecting lines φVu1 and φVu2 of the rows selectively supply the row selecting signals.
That is, in the vertical sub-scanning circuits 26 and 27 in the vertical scanning circuit 25 respectively, the vertical start pulse φVST is supplied to the pulse transfer unit on a predetermined row and pulses are sequentially transferred to the pulse transfer unit on the next row at a predetermined clock timing (not shown), and the row selecting signal is outputted from the output corresponding to the row. Further, in the vertical sub-scanning circuits 26 and 27 respectively, the vertical reset pulse φVRST is supplied to the pulse transfer unit on a predetermined row so that the row selecting signal is reset at the timing of the vertical reset pulse φVRST.
According to the first embodiment, the pixels at the same column are connected to two common vertical signal lines VSIG1v and VSIG2v (1≦v≦5). That is, the photoelectrically converting element of the pixel on the v-th column is connected to the vertical signal lines VSIG1v and VSIG2v via the two switches SWuv
According to the first embodiment, horizontal sub-scanning circuits 35 to 38 in horizontal scanning circuits 33 and 34 have the same structure, and have horizontal reading circuits and input terminals in accordance with the respective columns in the pixel areas. The input terminals of the horizontal sub-scanning circuits 35 and 36 are respectively connected to the vertical signal line VSIG1v. The input terminals of the horizontal sub-scanning circuits 37 and 38 are respectively connected to the vertical signal line VSIG2v. The horizontal scanning control circuits 31 and 32 respectively supply a horizontal start pulse φHST and a horizontal reset pulse φHRST to the horizontal sub-scanning circuits 35 and 36 or 37 and 38, and control the reading of the pixel signals via the vertical signal line.
In the horizontal sub-scanning circuits 35 to 38, the horizontal start pulse φHST is supplied to the horizontal reading circuits on a predetermined column, then, the pulses are sequentially transferred to the horizontal reading circuits at the next stage at a predetermined clock timing (not shown). Furthermore, in the horizontal sub-scanning circuits 35 to 38, the signals are captured via the vertical signal line connected to the input terminal corresponding to the column at a clock period based on the transferred pulses, and signals as outputs 1 to 4 are outputted from the output terminals thereof. Moreover, in the horizontal sub-scanning circuits 35 to 38, the horizontal reset pulse φHRST is supplied to the horizontal reading circuits at a predetermined column and the horizontal reading circuits are reset at the timing of the horizontal reset pulse φHRST.
Therefore, both the vertical sub-scanning circuits 26 and 27 can output the signals from all the pixels Puv in the pixel area 21, and horizontal sub-scanning circuits 35 to 38 can read and output the pixel signals from all the pixels Puv in the pixel area 21.
As mentioned above, according to the first embodiment, the structures of the pixels in the pixel area are the same, and the wiring patterns of the signals in the pixel areas are also the same. The plurality of vertical sub-scanning circuits for driving the pixels have the same structure and the plurality of horizontal sub-scanning circuits for reading the pixels have the same structure.
Next, the operation with the above-mentioned structure will be described with reference to
The vertical scanning control circuit 24 supplies a vertical start pulse φVST shown in
In this state, the horizontal scanning control circuits 31 and 32 supply the horizontal start pulse φHST to the horizontal reading circuits on the first columns in the horizontal sub-scanning circuits 35 and 37 and to the horizontal reading circuits on the third columns of the horizontal sub-scanning circuits 36 and 38. The horizontal sub-scanning circuits 35 to 38 sequentially shift the horizontal start pulse φHST to the horizontal reading circuits at the next stages. The respective horizontal reading circuits output, from the output terminal, the signals from the vertical signal lines connected to the input terminals at a predetermined clock-timing after inputting the horizontal start pulse φHST. In this case, the horizontal sub-scanning circuits 35 to 38 first respectively output signals read from the pixels P1a, P1c, P3a, and P3c.
At the next clock timing, the horizontal reading circuits on the second and fourth columns perform the reading operation. In this case, the horizontal sub-scanning circuits 35 to 38 respectively output signals from the pixels P1b, P1d, P3b, and P3d. Further, at the next clock timing, the horizontal reading circuits on the third and fifth columns perform the reading operation. In this case, the horizontal sub-scanning circuits 35 to 38 respectively output signals from the pixels P1c, P1e, P3c, and P3e. After ending the reading operation of the pixel signals, the horizontal reset pulse φHRST is supplied to the horizontal reading circuits on the fourth columns in the horizontal sub-scanning circuits 35 and 37, thereby stopping the pulse transfer and ending the pixel reading.
At the next horizontal scanning period, the pulses are transferred to the pulse transfer units on the second rows of the vertical sub-scanning circuits 26 and 27. The vertical sub-scanning circuits 26 and 27 supply the “H” row selecting signal to row selecting lines φV21 and φV42 on the second and fourth rows. In this state, the horizontal start pulse φHST of the “H” row selecting signal is generated and the pixel reading is performed from the first and third columns similarly to the scanning period of the first row. In this case, the similar reading as that on the first row is performed.
Further, the similar reading operation is performed in the horizontal scanning period of the third row. After ending the horizontal scanning period of the third row, the vertical reset pulse φVRST is supplied to the pulse transfer unit on the fourth column in the vertical sub-scanning circuit 26, thereby stopping the shift of the row selecting signal and ending the reading of the pixels in one frame.
As shown by the outputs 1 to 4 in
In this case, the pixels have the same structure, the wiring state and connecting state of the row selecting lines φVu1 and φVu2 are the same or uniform, the wiring state and connecting state of the vertical signal lines VSIG1v and VSIG2v are the same or uniform, and the structures of the horizontal sub-scanning circuits 35 to 38 are the same or uniform. Therefore, the signals stored in the respective pixels are outputted from the output terminals of the outputs 1 to 4 as the pixel signals having no property difference without being influenced by the difference in signal paths.
As mentioned above, according to the first embodiment, the plurality of pixels have the same structure and have the same wiring state and connecting state of the row selecting lines and the vertical signal lines. Further, the plurality of vertical sub-scanning circuits 26 and 27 for supplying the row selecting signal to the vertical signal lines in the divided areas have the same structure. Further, the respective outputs have no property difference among the signals stored in the pixels without being influenced by the signal paths because of the same structure among the plurality of horizontal sub-scanning circuits 35 to 38 for reading and outputting the pixel signals from the row selecting lines in the divided area. For example, the same-level signal is obtained from the overlapped pixels outputted from a plurality of output terminals.
The selecting order of the vertical signal line and the row selecting line is not limited to those shown in
Unlike the first embodiment, in place of the horizontal scanning control circuits 31 and 32, horizontal scanning control circuits 41 and 42 are used and, in place of the horizontal scanning circuits 33 and 34, horizontal scanning circuits 43 and 44 are used according to the second embodiment. Referring to
The horizontal sub-scanning circuits 45 to 48 have the same structure, and comprise: a horizontal reading circuit corresponding to each column in the pixel area 21; and a sample holding circuit between the vertical signal lines VSIG1v and VSIG2v. The horizontal scanning control circuits 41 and 42 supply the horizontal start pulse φHST and the horizontal reset pulse φHRST to the horizontal sub-scanning circuits 45 to 48, and further supply a sample holding control signal indicating the sample holding timing.
That is, a holding capacitor C1v is arranged between the input terminal of the horizontal reading circuit on the v-th column in the horizontal sub-scanning circuit 45 and the reference potential point. A sampling switch SH_SW1v is arranged between the vertical signal line VSIG1v and the input terminal of the horizontal reading circuit on the v-th column in the horizontal sub-scanning circuit 45. A holding capacitor C2v is arranged between the input terminal of the horizontal reading circuit on the v-th column in the horizontal sub-scanning circuit 46 and the reference potential point. A sampling switch SH_SW2v is arranged between the vertical signal line VSIG1v and the input terminal of the horizontal reading circuit on the v-th column in the horizontal sub-scanning circuit 46. A holding capacitor C3v is arranged between the input terminal of the horizontal reading circuit on the v-th column in the horizontal sub-scanning circuit 47 and the reference potential point. A sampling switch SH_SW3v is arranged between the vertical signal line VSIG2v and the input terminal of the horizontal reading circuit on the v-th column in the horizontal sub-scanning circuit 47. A holding capacitor C4v is arranged between the input terminal of the horizontal reading circuit on the v-th column in the horizontal sub-scanning circuit 48 and the reference potential point. A sampling switch SH_SW4v is arranged between the vertical signal line VSIG2v and the input terminal of the horizontal reading circuit on the v-th column in the horizontal sub-scanning circuit 48.
Next, the operation with the above structure will be described with reference to
First, referring to
In this case, the pixel signals from the pixels P3a to P3e are supplied to the vertical signal line VSIG1v via switches SW3a
On the basis of a sample holding control signal φSH, the output signals from the vertical signal lines VSIG1v (VSIG11 to VSIG15) are stored in holding capacitors C1a to C1e and C2a to C2e via sampling switches SH_SW1a to SH_SW1e in the horizontal sub-scanning circuit 45 and sampling switches SH_SW2a to SH_SW2e in the horizontal sub-scanning circuit 46. Further, based on the sample holding control signal φSH, the storage of the output signals from the vertical signal lines VSIG2v (VSIG21 to VSIG25) are stored into holding capacitors C3a to C3e and C4a to C4e via sampling switches SH_SW3a to SH_SW3e in the horizontal sub-scanning circuit 47 and sampling switches SH_SW4a to SH_SW4e in the horizontal sub-scanning circuit 48.
As mentioned above, the pixel signals of all the pixels on the third row selected by the vertical sub-scanning circuit 26 are held in the sample holding circuits in the horizontal sub-scanning circuits 45 and 46. The pixel signals of all the pixels on the third row selected by the vertical sub-scanning circuit 27 are held in the sample holding circuits in the horizontal sub-scanning circuits 47 and 48.
Next, all the sampling switches SH_SW1a to SH_SW4e are switched off and the electrical connection is shut off between the vertical signal lines VSIG11 to VSIG25 and the holding capacitors C1a to C4e. Next, the horizontal scanning control circuits 41 and 42 supply the horizontal start pulse φHST to the horizontal reading circuits on the first columns of the horizontal sub-scanning circuits 45 and 47 and to the horizontal reading circuits on the third columns of the horizontal sub-scanning circuits 46 and 48. Thus, referring to
After reading these pixel signals, the horizontal scanning control circuits 41 and 42 supply the horizontal reset pulse φHRST to the fourth horizontal reading circuits in the horizontal sub-scanning circuits 45 and 47. Consequently, the operation of the horizontal sub-scanning circuits 45 and 47 stops and the reading operation of the pixels P3a to P3e ends. In this way it is possible to obtain the signals of the pixels P3a to P3e from the corresponding output terminals of a plurality of output systems.
According to the second embodiment, the horizontal sub-scanning circuits of the four output systems have the same structure and have the same wiring state and connecting state. The pixel signals obtained from the four output systems have no property difference. For example, the wiring state and connecting state are the same in the vertical signal lines VSIG11 to VSIG15 and in the vertical signal lines VSIG21 to VSIG25 for reading the signal from the pixel P3c. The signals of the pixel P3c obtained from the outputs 1 to 4 are substantially the same.
The output signals from the pixel are temporarily stored in the holding capacitors C1a to C4c in the horizontal sub-scanning circuits 45 to 48. Therefore, in the pixel in which the non-breaking reading operation is impossible, the output signals from the pixel can be read from a plurality of output terminals.
Since the output signals from the pixel are temporarily stored in the holding capacitors C1a to C4e, sampling timings of the pixel signals read from the P3a to P3e can match and the duration for photoelectric conversion every pixel match.
At the next horizontal scanning period, the vertical scanning control circuit 24 supplies a vertical reset pulse φVRST1 to the pulse transfer unit on the fourth row and the vertical sub-scanning circuit 26 prohibits the pulse from being transferred to the pulse transfer unit on the next row. Then, the vertical scanning control circuit 24 supplies a vertical start pulse φVST2 to the pulse transfer unit on the first row in the vertical sub-scanning circuit 26. Thus, the vertical sub-scanning circuit 26 supplies the “H” row selecting signal to a row selecting line φV11 and the vertical sub-scanning circuit 27 supplies the “H” row selecting signal to a row selecting line φV42.
In this case, the operation similar to that for the horizontal scanning period reads the signals from the pixels P1a to P1e and P4a to P4e (refer to
The pixel signals from the pixels P1c, P2c, P3a, P3b, P3c, P3d, P3e, P4c, and P5c shown by the dotted patterns are outputted plural times respectively from the output terminals of the outputs 1 to 4. These pixel signals are averaged, for example, thereby preventing the deterioration in image quality at the boundary. Since the structures of the pixel area 21, the horizontal driving system, the vertical driving system, and the output system are uniform, the pixel signals at the pixels have no property difference and the image with high quality is obtained in accordance with the incident light amount.
According to the second embodiment, the same advantages as those according to the first embodiment are obtained. Further, even the output signals from the pixels in which the non-break reading is impossible can be outputted from a plurality of output terminals by temporarily storing the pixel signals into the holding capacitors C1a to C4e in the horizontal sub-scanning circuits 45 to 48. Furthermore, it is possible to match the sampling timings of the signals from the pixels P3a a to P3e to the holding capacitors C1a to C4e.
Obviously, the reading order according to the second embodiment can be applied to the first embodiment.
The solid-state pick-up device according to the third embodiment has a pixel area and a vertical driving system of which structures are different from those according to the second embodiment. Referring to
According to the third embodiment, the divided areas which are adjacent in the vertical and horizontal directions include a common pixel. That is, the divided-area-1 has pixels P1a to P3c, the divided-area-2 has pixels P1c to P3e, the divided-area-3 has pixels P3a to P5c, and the divided-area-4 has pixels P3c to P5e. Pixels shown by dotted patterns in
According to the third embodiment, the pixels on the same row are connected to one common row selecting line φVu (1≦u≦5 in
A vertical scanning circuit 55 supplies the row selecting signal to the row selecting line φVu. The vertical scanning circuit 55 has the pulse transfer unit and the output terminal corresponding to the respective rows in the pixel area 51. The each output terminal of the vertical scanning circuit 55 is connected to the row selecting line φVu. A vertical scanning control circuit 54 supplies vertical start pulses φVST1 and φVST2 to the vertical scanning circuit 55 so as to enable to selectively supply the row selecting signal to the row selecting line φVu.
That is, in the vertical scanning circuit 55, the vertical start pulses φVST1 and φVST2 are sequentially supplied to the pulse transfer unit on a predetermined row. The pulses are sequentially transferred to the pulse transfer unit on the next row at a predetermined clock timing (not shown), and are outputted as the row selecting signal from the output terminal corresponding to the row. Further, in the vertical scanning circuit 55, the vertical reset pulse φVRST is supplied to the pulse transfer unit on a predetermined row and the row selecting signal is reset at the timing of the vertical reset pulse φVRST. According to the third embodiment, the pixels on the same column are connected to a common vertical signal line VSIGv (1≦v≦5). That is, the photoelectrically converting element of the pixel on the v-th column is connected to the vertical signal line VSIG, via the respective switches SWuv. The respective switches SWuv are switched on, thereby transmitting the signals stored in the pixels to the connected vertical signal line.
Next, the operation with the above structure will be described with reference to
First, the vertical scanning control circuit 54 supplies vertical start pulses φVST1 shown in
A sample holding control signal φSH1 enables the output signal from the vertical signal line VSIGv (VSIG1 to VSIG5) to be supplied to the holding capacitors C1a to C1e and C2a to C2e via the sampling switches SH_SW1a to SH_SW1e in the horizontal sub-scanning circuit 45 and sampling switches SH_SW2a to SH_SW2e in the horizontal sub-scanning circuit 46. Further, a sample holding control signal φSH2 stores the output signals from the vertical signal lines VSIGv (VSIG1 to VSIG5) into holding capacitors C3a to C3e and C4a to C4e via sampling switches SH_SW3a to SH_SW3e in the horizontal sub-scanning circuit 47 and sampling switches SH_SW4a to SH_SW4e in the horizontal sub-scanning circuit 48.
As mentioned above, the pixel signals of all the pixels on the third row selected by the vertical scanning circuit 55 are held in the sample holding circuits of the horizontal sub-scanning circuits 45 and 46. The pixel signals of all the pixels on the third row selected by the vertical scanning circuit 55 are also held in the sample holding circuits of the horizontal sub-scanning circuits 47 and 48.
Next, all the sampling switches SH_SW1a to SH_SW4e are switched off and the electrical connection is shut off between the vertical signal lines VSIG1 to VSIG5 and the holding capacitors C1a to C4e. Next, the horizontal scanning control circuits 41 and 42 supply the horizontal start pulse φHST to the horizontal reading circuits on the first columns of the horizontal sub-scanning circuits 45 and 47 and the horizontal reading circuits on the third columns of the horizontal sub-scanning circuits 46 and 48. Thus, referring to
After reading the pixel signals (at the end of the output period), the horizontal scanning control circuits 41 and 42 supply the horizontal reset pulse φHRST to the fourth horizontal reading circuits in the horizontal sub-scanning circuits 45 and 47. Consequently, the operation of the horizontal sub-scanning circuits 45 and 47 stops and the reading operation of the pixels P3a to P3e ends. It is possible to obtain the signals from the pixels P3a to P3e from the corresponding output terminals of a plurality of output systems.
According to the third embodiment, the four output systems have the same structure of the horizontal sub-scanning circuit, the same wiring state and the same connecting state. The pixel signals obtained from the four output systems have no property difference. The signals from the pixel P3c obtained from the outputs 1 to 4 are the same.
The output signals from the pixel are temporarily stored in the holding capacitors C1a to C4e in the horizontal sub-scanning circuits 45 to 48. Therefore, even in the pixel in which the non-breaking reading operation is impossible, the output signals from the pixel can be read from a plurality of output terminals.
Since the output signals from the pixel are temporarily stored in the holding capacitors C1a to C4e, the sampling timings of the pixel signals read from the P3a to P3e can be matched and the duration for photoelectric conversion in every pixel can be matched.
When starting the next horizontal scanning period (in the former half of the horizontal reading period), the vertical scanning control circuit 54 supplies the vertical start pulse φVST2 to the pulse transfer unit on the first row in the vertical scanning circuit 55. Thus, the vertical scanning circuit 55 supplies the “H” row selecting signal to the row selecting line φV1. Consequently, in the former half of the horizontal reading period, the switches SW1v of the pixels on the first row are switched on, thereby supplying the pixel signal from the pixels to the vertical signal lines VSIG1 and VSIG5.
In the horizontal scanning control circuit 41, on the basis of the sample holding control signal φSH1, the output signals from the vertical signal line VSIGv (VSIG1 to VSIG5) are stored into the holding capacitors C1a to C1e and C2a to C2e via the sampling switches SH_SW1a to SH_SW1e of the horizontal sub-scanning circuit 45 and the sampling switches SH_SW2a to SH_SW2e of the horizontal sub-scanning circuit 46. Next, the sampling switches SH_SW1a to SH_SW2e are switched off and the vertical signal lines VSIGv (VSIG1 to VSIG5) are separated from the holding capacitors C1a to C2e, thereby ending the reading operation of the signals from the pixels P1a to P1e.
In the latter half period of the horizontal scanning period, the pulses based on the vertical start pulse φVST1 are outputted to the row selecting line φV4 as the “H” row selecting signal. Thus, in the latter half period of the reading period in the horizontal scanning period, the switch SW4v in the fourth pixels is switched on, thereby supplying the pixel signals from the pixels to the vertical signal lines VSIG1 to VSIG5.
In the horizontal scanning control circuit 42, on the basis of the sample holding control signal φSH2, the output signals from the vertical signal lines VSIG1 to VSIG5 are supplied and stored into the holding capacitors C3a to C3e and C4a to C4e via the sampling switches SH_SW3a to SH_SW3e in the horizontal sub-scanning circuit 47 and the sampling switches SH_SW4a to SH_SW4e in the horizontal sub-scanning circuit 48. Next, the sampling switches SH_SW3a to SH_SW4e are switched off and the vertical signal lines VSIG1 to VSIG5 are separated from the holding capacitors C3a to C4e, thereby ending the reading operation of the signals from the pixels P4a to P4e.
As mentioned above, at the reading period in the horizontal scanning period, the pixel signals at the entire pixels at the first and fourth rows are stored in the holding capacitors C1a to C4e.
Next, at the start timing of the output period in the horizontal scanning period, the horizontal scanning control circuits 41 and 42 supply the horizontal start pulse φHST to the horizontal reading circuits at the first columns in the horizontal sub-scanning circuits 45 and 47 and the horizontal reading circuits at the third columns in the horizontal sub-scanning circuits 46 and 48. Thus, referring to
After reading the these pixel signals (at the end of the output period), the horizontal scanning control circuits 41 and 42 supply the horizontal reset pulse φHRST to the fourth horizontal reading circuits in the horizontal sub-scanning circuits 45 and 47. Consequently, the operation of the horizontal sub-scanning circuits 45 and 47 stops and the reading operation of the pixels P1a to P1e and P4a to P4e. It is possible to obtain the signals from the pixels P1a to P1e and P4a to P4e from the output terminals of a plurality of output systems.
In the next horizontal scanning period, the pixels on the second and fifth rows are selected and are read and outputted as mentioned above. Thus, in the horizontal scanning period, the signals from the pixels P2a to P2e and P5a to P5e are outputted from the output terminals of four output systems.
After ending the reading of the pixels P1a to P5e, the vertical scanning control circuit 54 supplies the vertical reset pulse φVRST to the vertical scanning circuit 55. Thus, the operation of the vertical scanning circuit 55 stops and the row selection ends.
As mentioned above, in the case of the reading method shown in
As mentioned above, according to the third embodiment, the pixels in a pixel area have the same structure, the plurality of pixels have the same wiring state and connecting state of the row selecting line and the vertical signal line. Further, the horizontal sub-scanning circuits for reading and outputting the pixel signals of the row selecting lines in the divided areas have the same structure. Therefore, the outputs have no property difference in accordance with the signals stored in the pixels without any influence from the signal path. For example, the same-level signal is obtained from the overlapped pixels outputted from a plurality of output terminals. In addition, the row selecting line and the vertical signal line for driving the pixels forming the pixel area have the single system, respectively, and the circuit can be simplified by arranging in each pixel only the single system of switch for selecting the row.
Referring to
According to the fourth embodiment, the dividing method of the pixel area 51 is different from those according to the first and third embodiments, and the pixel area 51 is divided into divided-area-i and divided-area-2. The divided-area-1 includes the pixels P1a to P5b and the pixels P1c, P3c, and P5c. The divided-area-2 includes the pixels P1d to P5e and the pixels P2c and P4c. That is, as shown by a broken line in
Next, the operation according to the fourth embodiment with the above structure will be described with reference to
First, the vertical scanning control circuit 54 supplies the vertical start pulse φVST shown in
The horizontal scanning control circuit 31 generates a horizontal start pulse φHST1 shown in
Thus, horizontal sub-scanning circuit 35 sequentially outputs the output signals from the vertical signal lines VSIG1 to VSIG3 as the output 1. The horizontal sub-scanning circuit 36 sequentially outputs the output signals from the vertical signal lines VSIG4 to VSIG5 as the output 2 (refer to
After reading the necessary pixel signals, the horizontal scanning control circuit 31 supplies the horizontal reset pulse φHRST to the horizontal sub-scanning circuit 35. Thus, the operation of the horizontal sub-scanning circuit 35 stops and the reading of the pixels P1a to P1e ends.
Next, the vertical scanning circuit 55 selects the row selecting line φV2, thereby supplying the pixel signals from the P2a to P2e to the vertical signal lines VSIG1 to VSIG5 via the row selecting switches SW2a to SW2e.
The horizontal scanning control circuit 31 supplies the horizontal start pulse φHST2 to the horizontal reading circuits at the first column in the horizontal sub-scanning circuit 35 to the horizontal reading circuit at the third column in the horizontal sub-scanning circuit 36. Thus, the horizontal sub-scanning circuit 35 sequentially outputs the pixel signals P2a to P2b as the output 1, and the horizontal sub-scanning circuit 36 sequentially outputs the pixel signals P2c to P2e as the output 2.
After reading the necessary pixel signals, the horizontal scanning control circuit 31 supplies a horizontal reset pulse φHRST2 to the horizontal sub-scanning circuit 35. Thus, the operation of the horizontal sub-scanning circuit 35 stops and the reading of the pixels P2a to P2e ends.
Then, similarly, the vertical scanning circuit 55 sequentially selects the row selecting lines φV3 to φV5 thereby sequentially reading and outputting the signals of the pixels P3a to P5e by the horizontal sub-scanning circuits 35 and 36.
As mentioned above, according to the fourth embodiment, similarly to the first to third embodiments, the pixel areas have the same structure, the wirings have the same structure, the structures of the vertical and horizontal driving systems and output system and the like are unified, respectively. The pixel signal from the pixel can be outputted from the two-system output system without property difference.
The boundary of the divided areas in the horizontal direction can be made to non-straight line by controlling, by the horizontal scanning control circuit 31, the start position of the horizontal start pulse φHST1 and φHST2. Thus, it is possible to obtain the video image in which the variation in properties in the pixel areas at the boundary portions is visually suppressed.
Referring to
According to the fifth embodiment, the pixel area 51 is divided into the divided-area-1 and divided-area-2 in the vertical direction. The divided-area-1 includes the pixels P1a to P2e and the pixels P3a, P3c, and P3e. The divided-area-2 includes the pixels P4e to P5e and the pixels P3b and P3d. That is, as shown by a broken line in
According to the fifth embodiment, in place of the horizontal scanning control circuit 31, horizontal scanning control circuits 61 and 62 are used. In place of the horizontal scanning circuit 33, horizontal scanning circuits 63 and 64 are used. Referring to
The structures of the horizontal sub-scanning circuits 45 and 47 and the structure of sample holding circuits arranged between the horizontal sub-scanning circuits 45 and 47 as the horizontal sub-scanning circuits and the vertical signal lines VSIG1 to VSIG5 are the same as those in
Next, the operation with the above structure will be described with reference to
First, the vertical scanning control circuit 54 supplies the vertical start pulses φVST1 shown in
The horizontal scanning control circuit 61 generates a sample holding control signal φSH1A shown in
On the other hand, the horizontal scanning control circuit 62 generates a sample holding control signal φSH2B shown in
Next, all the sampling switches SH_SW1a to SH_SW2e are switched off and the connection is shut off between the vertical signal lines VSIG1 to VSIG5 and the holding capacitors C1a to C1e. Next, the horizontal scanning control circuits 61 and 62 supply the horizontal start pulse φHST to the first columns of the horizontal sub-scanning circuits 45 and 47. Thus, the horizontal sub-scanning circuit 45 sequentially outputs the pixel signals of the pixels P3a, P3c and P3e stored in the holding capacitors C1a, C1c and C1e as the output. The horizontal sub-scanning circuit 47 sequentially outputs the pixel signals of the pixels P3b and P3d stored in the holding capacitors C2b and C2d as the output 2.
Next, the vertical scanning control circuit 54 supplies the vertical start pulse φVST2 to the pulse transfer unit on the first row in the vertical scanning circuit 55, thereby selecting the row selecting line φV1. The signals from the pixels P1a and P1e are supplied to the vertical signal lines VSIG1 to VSIG5 via the switches SW1a to SW1e for selecting the row.
The horizontal scanning control circuit 61 stores, by the sample holding control signal φSH1A and φSH1B, the output signals of the vertical signal lines VSIG1 to VSIG5 into the holding capacitors C1a and C1e via the corresponding sampling switches SW_SW1a to SW_SW1e in the horizontal sub-scanning circuit 45.
Next, the horizontal scanning control circuit 61 switches off the sampling switches SW_SW1a to SW_SW1e and separates the vertical signal lines VSIG1 to VSIG5 from the holding capacitors C1a to C1e, thereby ending the reading operation of the pixels P1a to P1e.
Next, the vertical scanning circuit 55 selects the row selecting line φV4, thereby supplying, the pixel signals P4a to P4e to the vertical signal lines VSIG1 to VSIG5 via the switches SW4a to SW4e for selecting the row. The horizontal scanning control circuit 62 stores, by sample holding control signal φSH2A and φSH2B, the output signals of the vertical signal lines VSIG1 to VSIG5 into the holding capacitors C2a to C2e via the corresponding sampling switches SW_SW2a to SW_SW2e in the horizontal sub-scanning circuit 46.
Next, the horizontal scanning control circuit 62 switches off the sampling switches SW_SW2a to SW_SW2e and separates the vertical signal lines VSIG1 to VSIG5 from the holding capacitors C2a and C2e. Then, the horizontal scanning control circuits 61 and 62 supply the horizontal start pulse φHST to the first column in the horizontal sub-scanning circuits 45 and 47. Thus, the pixel signals P1a to P1e stored in the holding capacitors C1a to C1e are outputted as the outputs 1 of the horizontal sub-scanning circuit 45. The pixel signals P4a to P4e stored in the holding capacitors C2a to C2e are outputted as the outputs 2 of the horizontal sub-scanning circuit 45.
After that, by the similar operation, the signals from the pixels P2a to P2e and P5a to P5e are read. After ending the reading operation from the pixels P1a to P5e, the horizontal scanning control circuit 54 supplies the vertical reset pulses φVRST to the vertical scanning circuit 55 and the operation of the vertical scanning circuit 55 stops, thereby ending the row selection.
As mentioned above, according to the fifth embodiment, the same advantages as those according to the third embodiment with reference to
According to the sixth embodiment, the image pick-up device comprises: a pixel area 71; a vertical driving system mainly comprising a vertical scanning control circuit 72 and a vertical scanning circuit 73; a horizontal driving system mainly comprising horizontal scanning control circuits 81 and 82 and horizontal scanning circuits 83 and 84; and an output system mainly comprising a horizontal reading circuit.
The pixel area 71 has the same structure as that of the pixel area 21 shown in
According to the sixth embodiment, the vertical scanning control circuit 72 can vary the row positions of the vertical start pulse φVST and the vertical reset pulse φVRST for supplying the pulses to the vertical sub-scanning circuits 74 and 75. The horizontal scanning control circuits 81 and 82 can vary the column positions of the horizontal start pulse φHST and the horizontal reset pulse φVRST for supplying the pulses to the horizontal sub-scanning circuits 85 to 88.
A hatched portion in the pixel area 71 shown in
The overlapped scanning area in the vertical direction is determined by the vertical start pulse φVST and the vertical reset pulse φVRST which are supplied to the vertical sub-scanning circuits 74 and 75. Similarly, the overlapped scanning area in the horizontal direction is determined by the horizontal start pulse φHST and the horizontal reset pulse φHRST which are supplied to the horizontal sub-scanning circuits 85 to 88.
Next, the operation with the above structure according to the sixth embodiment will be described.
According to the sixth embodiment, the vertical scanning control circuit 72 changes the row positions of the vertical start pulse φVST and the vertical reset pulse φVRST which are supplied to the vertical sub-scanning circuits 74 and 75. The horizontal scanning control circuits 81 and 82 changes the column position of the horizontal start pulse φHST and the horizontal reset pulse φHRST which are supplied to the horizontal sub-scanning circuits 85 to 88.
For example, the horizontal start pulse φHST is supplied to the horizontal reading circuits on the second columns in the horizontal sub-scanning circuits 86 and 88. The horizontal reset pulse φHRST is supplied to the horizontal reading circuits on the fourth columns in the horizontal sub-scanning circuits 85 and 87. Consequently, the pixel column to overlappingly be read can be increased by three pixel columns in the horizontal direction.
As mentioned above, according to the sixth embodiment, the overlappingly scanning areas in the horizontal direction and vertical direction are adjusted based on the unit of one pixel by changing the supply position of the vertical start pulse φVST, the vertical reset pulse φVRST, the horizontal start pulse φHST and the horizontal reset pulse φHRST.
According to the sixth embodiment, the vertical driving system and the horizontal driving system are structured corresponding to the entire pixel area and therefore it is possible to increase or decrease the number of pixels which are overlappingly read at the boundary portion of the divided areas. Thus, it is possible to effectively suppress the variation in properties in every divided area. For example, the dynamic correction is possible by controlling the number of overlapped pixels in units of frame in accordance with the scene or photographing state. Thus, the frame rate can be changed within a predetermined range by properly controlling the number of overlapped pixels in accordance with a camera mode or the like in the case of using a camera used for specific photographing which can effectively photograph images by various frame rates.
Unlike the according to the sixth embodiment, a vertical scanning control circuit 90 and a horizontal scanning control circuit 92 are used, in place of the vertical scanning control circuit 72 and the horizontal scanning control circuits 81 and 82.
The vertical scanning control circuit 90 supplies the vertical start pulse φVST and the vertical reset pulse φVRST to the pulse transfer unit at the arbitrary number of rows in the vertical sub-scanning circuits 74 and 75. The horizontal sub-scanning circuits 91 and 92 supply the horizontal start pulse φHST and the horizontal reset pulse φHRST to the horizontal reading circuits at the arbitrary number of columns in the horizontal sub-scanning circuits 85 to 88.
According to the seventh embodiment, with the above structure, the divided area of the pixel area 71 is determined in accordance with the positions of the rows of the vertical start pulse φVST and the vertical reset pulse φVRST supplied to the vertical sub-scanning circuits 74 and 75 and the positions of the columns of the horizontal start pulse φHST and the horizontal reset pulse φHRST supplied to the horizontal sub-scanning circuits 85 to 88 Further, it is possible to arbitrarily set the numbers of the vertical start pulse φVST and the vertical reset pulse φVRST and the numbers of the horizontal start pulse φHST and the horizontal reset pulse φHRST. The number of divided areas can freely be set.
According to the seventh embodiment, the vertical sub-scanning circuits 74 and 75 have the same structure, corresponding to the entire area of the pixel area 71 in the vertical direction. The horizontal sub-scanning circuits 85 to 88 have the same structure, corresponding to the entire area of the pixel area 71 in the horizontal direction. Therefore, the number of divided areas can properly and simply be changed.
Thus, a camera for a still image, such as a digital still camera does not necessarily need the high frame rate. In this case, the number of divided areas is reduced in accordance with the photographing situation or camera application and therefore the number of areas having the property variation is reduced. Thus, it is possible to obtain the image with high quality. The power consumption is reduced by stopping the unnecessary circuit operation.
When an image output is necessary at the high frame rate, all the vertical sub-scanning circuits and horizontal sub-scanning circuits are not necessarily used.
Referring to
For example, the horizontal scanning control circuits 91 and 92 supply the horizontal start pulse φHST to only the horizontal sub-scanning circuits 85 and 87, thus enabling the reading shown by the hatched portion in
As compared with the reading of (2×2) division, the divided area in the horizontal direction is reduced to half in the example shown in
Referring to
For example, the vertical scanning control circuit 90 supplies the vertical start pulse φVST to only the vertical sub-scanning circuit 74, thus enabling the reading shown by the hatched portion in
As compared with the reading of (2×2) division, the divided area in the vertical direction is reduced to half in the example shown in
Referring to
For example, the horizontal scanning control circuit 91 supplies the horizontal start pulse φHST to only the horizontal sub-scanning circuit 85 and the vertical scanning control circuit 90 supplies the vertical start pulse φVST to only the vertical sub-scanning circuit 74, thus enabling the reading shown by the hatched portion in
As compared with the reading of (2×2) division, the divided area in the horizontal and vertical directions is reduced to half in the example shown in
In the examples shown in FIGS. 16 to 18, the same advantages as those described with reference to
Generally, the pixel area has an optical black pixel for adjusting the black level at both-end portions. The pixel signals in the divided areas obtained according to the first to seventh embodiments are outputted via the different output systems. Therefore, in the case of adjusting the black level by using the outputs via the output systems, the adjustment of the black level changes depending on the divided area and the image quality deteriorates if no consideration of the using optical black pixel is made.
According to the eighth embodiment, it is possible to obtain the pixel signal of the common optical black pixel via the output systems for outputting the pixel signals in the divided areas. For the purpose of a brief description,
The image pick-up device according to the eighth embodiment comprises: a pixel area 102; a vertical driving system comprising a vertical scanning control circuit (not shown) and a vertical scanning circuit 107; a horizontal driving system mainly comprising a horizontal scanning control circuit 101 and a horizontal scanning circuit 103; and an output system mainly comprising the horizontal reading circuit.
The pixel area 102 has the same structure as that of the pixel area 21 shown in
Referring to
The vertical scanning circuit 107 has the same structure as that of the vertical sub-scanning circuit 26 shown in
The structures of the horizontal sub-scanning circuits 105 and 106 are substantially the same. The horizontal sub-scanning circuits 105 and 106 have the horizontal reading circuits corresponding to the respective columns in the pixel area 102. The horizontal reading circuit on the i-th column (including the OB areas OB1 and OB2 in
A sample holding circuit is arranged between the horizontal reading circuit and the vertical signal line. The sample holding circuit comprises a sampling switch and a holding capacitor. That is, a holding capacitor Cia is arranged between the input terminal of the horizontal reading circuit on the i-th column in the horizontal sub-scanning circuit 105 and the reference potential point, and a sampling switch SW_Cia is arranged between the input terminal of the horizontal reading circuit on the i-th column in the horizontal sub-scanning circuit 105 and the vertical signal line on the corresponding column. Similarly, a holding capacitor Cib is arranged between the input terminal of the horizontal reading circuit on the i-th column in the horizontal sub-scanning circuit 106 and the reference potential point, and a sampling switch SW_Cib is arranged between the input terminal of the horizontal reading circuit on the i-th column in the horizontal sub-scanning circuit 106 and the vertical signal line on the corresponding column.
These structures are the same as those in the horizontal sub-scanning circuits 45 and 46 shown in
The horizontal scanning control circuit 101 supplies, to the horizontal sub-scanning circuits 105 and 106, a sample holding control signal φSW, horizontal start pulses φHST, φHST1, and φHST2, horizontal reset pulses φRST1 and φRST2, and control clocks φCONT1 and φCONT2.
According to the eighth embodiment, a transfer control switch SW4a is arranged between shift register units SR4a and SR5a in the horizontal sub-scanning circuit 105. A transfer control switch SW7b is arranged between shift register units SR7b and SRn-1b in the horizontal sub-scanning circuit 106. The transfer control switches SW4a and SW7b are respectively on/off controlled by the control clocks φCONT1 and φCONT2, thereby stopping the operation of the shift register units. The transfer control switches SW4a and SW7b control the start position for reading an optical black pixel signal (hereinafter, referred to as an OB pixel signal) from the OB area O2.
Next, the operation according to the eighth embodiment will be described with reference to
The vertical scanning circuit 107 outputs the “H” row selecting signal to the row selecting line on the first row in the pixel area 102, thus supplying, to the corresponding vertical signal line, the pixel signals of all the pixels including the optical black pixel at the first row.
In the reading period, the sampling switches in the horizontal sub-scanning circuits 105 and 106 are switched on by the sample holding control signal φSW from the horizontal scanning control circuit 101. Consequently, the pixel signals on the first row are stored in the holding capacitors Cia to Cib via the sampling switches SW_Cia and SW_Cib in the horizontal sub-scanning circuits 105 and 106 through the vertical signal line of the corresponding column. Consequently, the pixel signals of all the pixels on the first row selected by the vertical scanning circuit 107 are held in the sample holding circuits in the horizontal scanning circuits 105 and 106.
A reset pulse φRST1 is supplied to the horizontal sub-scanning circuit 105 and a reset pulse φRST2 respectively is supplied to the horizontal sub-scanning circuit 106, thereby resetting the node in the shift register unit. Next, the horizontal start pulse φHST is supplied to the shift register units at the first column. Thus, pixel signals FOB1 and FOB2 corresponding respectively to the holding capacitors C1a and C2a in the horizontal reading circuits are outputted as the outputs 1 via sampling switches SW_S1a and SW_S2a. Also, pixel signals FOB1 and FOB2 corresponding respectively to the holding capacitors C1b and C2b in the horizontal reading circuits are outputted as the output 2 via sampling switches SW_S1b and SW_S2b.
After outputting the OB pixel signal, the horizontal sub-scanning circuit 105 outputs the OB pixel signal, then supplies the reset pulse φRST1 again, and resets the node in the shift register unit. Next, the control clock φCONT1 switches off the switch SW4a, thereby inputting the horizontal start pulse φHST1 for scanning the shift register unit corresponding to the columns from the divided-area-2 to the OB area O2 to the corresponding position of the shift register in the horizontal sub-scanning circuit 105, namely, between the switch SW4a and the shift register unit SR5a.
Thus, selecting pulses generated by the horizontal start pulses φHST are sequentially transferred from the reading start position of the divided-area-2, thereby outputting, as the outputs 1, the pixel signals P3, P4, and P5 corresponding to the divided-area-2 stored in the holding capacitors C5a, C6a, and C7a via the switches SW_S5a, SW_S6a, and SW_S7ab. In the OB area O2 at the latter stage, the signals are sequentially scanned, thereby reading OB pixel signals ROB1 and ROB2 at the latter stage stored in the holding capacitors Cn-1a and Cna via the switches SW_Sn-1a and SW_Sna. Then, the scanning ends.
By the horizontal start pulses φHST inputted to the horizontal sub-scanning circuit 106, the pixel signals FOB1 and FOB2 are outputted via sampling switches SW_S1a, SW_S2a, SW_S1b, and SW_S2b. Further, the selecting pulses are sequentially transferred through the shift registers, and the pixel signals P1, P2, and P3 in the divided-area-1 are outputted from the holding capacitors C3b, C4b, and C5b via the sampling switches SW_S3b, SW_S4b, and SW_S5b.
After scanning the divided-area-1, a reset pulse φRST2 is supplied to the horizontal sub-scanning circuit 106, thereby resetting the node in the shift register. Next, the control clock φCONT2 switches off the switch SW7b, thereby inputting the horizontal start pulse φHST2 for scanning the shift register unit corresponding to the OB area O2 to the position of the shift register unit in the horizontal sub-scanning circuit 106, namely, between the transfer control switch SW7b and the shift register unit SR_Sn-1b. Thus, the OB pixel signals ROB1 and ROB2 stored in the holding capacitors Cn-1b and Cnb are read via the sampling switches SW_Sn-1b and SW_Snb. Then, the scanning ends.
As mentioned above, according to the eighth embodiment, the same outputs from the OB pixel areas are obtained for the respective read divided areas. The OB pixels are shielded for prescribing the black level of the video signals. The OB pixel may basically be arranged at any place as long as the place has no problems on property and the place is in a non-light-receiving unit of the solid-state pick-up device. Therefore, in the image pick-up device for dividing the pixel portions and reading them, the same OB pixel is read by the reading circuit in every different divided area and thus it is possible to monitor in real-time and correct the property variation of the reading circuit on the black level at the latter circuit.
The same optical black pixel among the output systems may be read and all the optical black pixels may not necessarily be read.
According to the eighth embodiment, a free time in which the pixel signal is not read is generated. However, according to the ninth embodiment, the free time generation is prevented by transferring the pulses for designating the pixel signal to be read.
According to the ninth embodiment, unlike the according to the eighth embodiment with reference to
The transfer unit 111 transfers output pulses of the shift register unit SR2a and supplies the transferred output pulses to the shift register units SR5a. The transfer unit 112 transfers output pulses of the shift register unit SR5b and supplies the transferred output pulses to the shift register units SRn-1b.
The transfer units 111 and 112 thin out the shift register unit corresponding to the column which is not read. The transfer units 111 and 112 may only comprise simple metallic wiring to connect the shift register unit, or may have a buffer function which is controlled by clocks. However, preferably, the delay time of pulses transferred by the transfer units 111 and 112 may be suppressed to the low level.
Next, a description is given of the operation with the above structure according to the ninth embodiment with reference to
The vertical scanning circuit 107 outputs the “H” row selecting signal to the row selecting line on the first row in the pixel area 102, thus supplying, to the corresponding vertical signal line, the pixel signals of all the pixels including the optical black pixel at the first row.
In the reading period, the respective sampling switches in the horizontal sub-scanning circuits 105 and 106 are switched on by the sample holding control signal φSW sent from the horizontal scanning control circuit 101. Consequently, the pixel signals at the first row are stored in the holding capacitors Cia to Cib via the sampling switches SW_Cia and SW_Cib in the horizontal sub-scanning circuits 105 and 106 from the vertical signal line of the corresponding column. Consequently, the pixel signals of all the pixels at the first row selected by the vertical scanning circuit 107 are held in the sample holding circuits in the horizontal scanning circuits 105 and 106.
The reset pulse φRST is supplied to the horizontal sub-scanning circuits 105 and 106, thereby resetting the node in the shift register unit. Next, a control clock φCONT3 is inputted in the horizontal sub-scanning circuit 105, thereby switching off the switches SW2a and SW4a. Then, a clock transfer system of the shift register unit SR2a, the transfer unit 111, and the shift register unit SR5a is formed. Similarly, the control clock φCONT3 is inputted in the horizontal sub-scanning circuit 106, thereby switching off the switches SW5b and SW7b. Then, a clock transfer system of the shift register unit SR5b, the transfer unit 112, and the shift register unit SRn-1b is formed.
Next, the horizontal start pulse φHST is supplied to the shift register units SR1a and SR1b of the first state. Thus, the optical black pixel signals FOB1 and FOB2 held in the holding capacitors C1a, C2a, C1b, and C2b in the horizontal reading circuits are outputted as the outputs 1 and 2 via the switches SW_S1a and SW_S2a and switches SW_S1b and SW_S2b.
Since the switch SW2a is switched off in the horizontal sub-scanning circuit 105, the horizontal start pulse φHST is not transmitted to the shift register unit SR3a and is supplied to the input terminal of the shift register unit SR5a via the transfer unit 111. That is, in the divided-area-1, the processing skips the operation for reading of the signals from the holding capacitors C3a and C4a, which store the pixel signals of the pixels P1 and P2 corresponding to the shift register units SR3a and SR4a, via the switches SW_S3a and SW_S4a.
Next, the horizontal start pulse φHST is sequentially transferred to the shift register units SR5a, SR6a, and SR7a. Thus, the pixels signals P3, P4, and P5 in the divided-area-2 stored in the holding capacitors C5a, C6a, and C7a are outputted as the outputs 1 via the SW_S5a, SW_S6a, and SW_S7a. In the OB area O2 at the latter stage, the signals are sequentially scanned, thereby reading the OB pixel signals ROB1 and ROB2 stored in the holding capacitors Cn-1a and Cna via the switches SW_Sn-1a and SW_Sna. Consequently, the scanning operation ends.
The similar operation is performed in the horizontal reading circuit in the horizontal sub-scanning circuit 106. That is, by the horizontal start pulse φHST, the OB pixel signals FOB1 and FOB2 are read from the holding capacitors C1b and C2b via the switches SW_S1b and SW_S2b. Further, the horizontal start pulse φHST is transferred in the shift registers SR3b, SR4b, and SR5b and is outputted from the holding capacitors C3b, C4b, and C5b, which hold the pixel signals P1, P2, and P3 in the divided-area-1, via the switches SW_S3b, SW_S4b, and SW_S5b.
The switches SW2a and SW5b are switched off. Thus, the horizontal start pulse φHST is not transmitted to the shift register unit SR6b but is supplied to the input terminal of the shift register unit SR7b via the transfer unit 112. That is, in the divided-area-2, the processing skips the operation for reading of the signals from the holding capacitors C6b and C7b, which store the pixel signals of the pixels P4 and P5 corresponding to the shift register units SR6b and SR7b, via the switches SW_S6b and SW_S7b.
Next, the horizontal start pulse φHST is sequentially transferred to the shift register units SRn-1b and SRnb. Thus, the selecting pulses are transferred from the reading start position of the OB area O2, thereby outputting, as the outputs 2, the OB pixel signals ROB1 and ROB2 stored in the holding capacitors Cn-1b and Cnb via the switches SW_Sn-1b and SW_Snb. Consequently, the scanning operation ends.
As mentioned above, the outputs including the same OB pixel signals FOB1 and FOB2 and the OB pixel signals ROB1 and ROB2 are obtained from either the output system for outputting the pixel signal in the divided-area-1 and the output system for outputting the pixel signal in the divided-area-2.
As mentioned above, according to the ninth embodiment, in the image pick-up device which divides the pixel portion into a plurality of areas and reads the areas, the same OB pixels are read by the reading circuit in every different divided area. Consequently, the circuit at the latter circuit monitors and corrects in real-time the property variation in reading circuit on the black level and the free time in which the reading operation is not performed is removed.
Having described the preferred embodiments of the invention referring to the accompanying drawings, it should be understood that the present invention is not limited to those precise embodiments and various changes and modifications thereof could be made by one skilled in the art without departing from the spirit or scope of the invention as defined in the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2003-124309 | Apr 2003 | JP | national |
