BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram showing an example of a configuration of an image processing system to which the present invention is applied;
FIG. 2 is a block diagram showing an example of a detailed configuration of a RAM module shown in FIG. 1;
FIGS. 3 and 4 are a block diagram and a diagrammatic view, respectively, illustrating details of flows of pixel values before and after an interpolation operation;
FIGS. 5 and 6 are views illustrating write addresses;
FIG. 7 is a diagrammatic view illustrating a read address;
FIG. 8 is a view illustrating a pixel group;
FIG. 9 is a flow chart illustrating an image transform process;
FIG. 10 is a flow chart illustrating a writing process;
FIG. 11 is a flow chart illustrating a reading out process;
FIG. 12 is a block diagram showing an example of an image processing apparatus in which a DME shown in FIG. 1 is incorporated; and
FIG. 13 is a block diagram showing an example of a recording and reproduction apparatus in which the DME is incorporated.