Image processing apparatus capable of selecting a non-rectangular area

Abstract

An image processing apparatus includes an input unit for inputting image data, a storage unit for storing a plurality of non-rectangular area data, a selection unit for selecting the non-rectangular area data stored in the storage unit, a control unit for reading out the non-rectangular area data selected by the selection unit from the storage unit in synchronism with input of the image data by the input unit, and a processing unit for processing the image data in accordance with the non-rectangular area data selected by the selection unit.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an image processing apparatus which digitally processes an input image and performs various image processing operations on the digital image data.

2. Related Background Art

In recent years, digital color copying machines have become popular. In a copying machine of this type, a color original is color-separated and read in units of pixels, read image data are digitally processed, and obtained digital signals are output to a color printer, thereby creating a digital color hard copy. Since an apparatus of this type can digitally process image data, various image processes are available, and the application range in the field of color copy tends to be widened. In the image process modes, an output position of an image is shifted (FIG. 72 A), a desired image area is extracted (FIG. 72 B), only a color in a desired area is converted (FIG. 72 C), a character or image stored in a memory is fitted in a reflective original (FIG. 72 D), and so on.

Therefore, upon combination of various functions, a digital color copying machine can be easily applied to color planning reports, advertising posters, sales promotion references, design drawings, and the like.

However, since the prior art has no standard non-rectangular area generation means (for a circle, an oval, and the like). When trimming, masking, color converting, image synthesizing, or the like using a circular or oval pattern is to be performed (e.g., a reflective original image), an original must be cut into a desired pattern, adhered to a white paper sheet, and then read to designate an area, resulting in cumbersome and time-consuming operations.

A conventional color conversion technique, a technique in which a predetermined rectangular area in a color image is designated and a desired color portion in the area is converted to another color, is disclosed in U.S. Pat. No. 4,855,765 and U.S. patent application Ser. No. 120,820.

However, in the prior arts, since color conversion processing is executed within a rectangular area, the following drawbacks are posed:

(1) When a plurality of areas including a color to be converted are situated too closely to each other to be divided by rectangular areas, and color conversion processing is to be executed for one of the areas (FIG. 10 ), the desired image cannot be obtained.

(2) When color conversion is performed for an area consisting of multi-gradational colors, the detection width must be considerably increased, thus resulting in a conspicuous detection error. When the detection width is decreased to suppress these errors, even a desired portion of the image cannot be converted.

SUMMARY OF THE INVENTION

It is an object of the present invention to eliminate the conventional drawbacks in the prior art.

It is another object of the present invention to provide an image processing apparatus which can easily designate a non-rectangular area.

It is still another object of the present invention to provide an image processing apparatus which can designate a non-rectangular area within a short period of time.

In order to achieve the above objects, according to the present invention, there is provided an image processing apparatus comprising input means for inputting image data, storage means for storing a plurality of non-rectangular area data, selection means for selecting the non-rectangular area data stored in the storage means, control means for reading out the non-rectangular area data selected by the selection means from the storage means in synchronism with input of the image data by the input means, and processing means for processing the image data in accordance with the non-rectangular area data selected by the selection means.

There is also provided an image processing apparatus comprising input means for inputting image data, generation means for generating a non-rectangular area signal on the basis of a predetermined coordinate designation, storage means for storing the non-rectangular area signal, control means for reading out the non-rectangular area signal stored in the storage means in synchronism with input of the image data by the input means, and processing means for processing the image data in accordance with the non-rectangular area signal read out by the control means.

It is still another object of the present invention to provide an image processing apparatus which can appropriately execute color conversion processing.

In order to achieve the above object, according to the present invention, there is provided an image processing apparatus comprising detection means for detecting a specific color in an image on the basis of input image data, generation means for generating a non-rectangular area signal, and conversion means for converting the specific color detected by the detection means into another color on the basis of an output signal from the detection means and the non-rectangular area signal.

It is still another object of the present invention to provide an apparatus having high-grade image processing and editing functions.

It is still another object of the present invention to provide an image processing apparatus which has good color reproducibility.

It is still another object of the present invention to provide a copying apparatus and a copying system having novel functions.

Other objects and arrangements of the present invention will be apparent from the following description.

BRIEF DESCRIPTION OF THE DRAWINGS:

FIG. 1 is a schematic view of an overall image processing apparatus according to an embodiment-of the present invention:

FIGS. 2A , 2 B and 2 C is a block diagram of an image processing circuit according to the embodiment of the present invention;

FIGS. 3A and 3B are respectively a schematic view and a timing chart showing color read sensors and drive pulses;

FIGS. 4A and 4B are respectively a circuit diagram and a timing chart of an ODRV 118 a and an EDRV 119 a;

FIGS. 5A and 5B are respectively a circuit diagram and a schematic view for explaining a black correction operation;

FIGS. 6A to 6 D are respectively a circuit diagram and schematic views for explaining shading correction;

FIG. 7 is a block diagram of a color conversion section;

FIGS. 8A and 8B is a block diagram of a color detection unit;

FIG. 9 is a block diagram of a color conversion circuit;

FIG. 10 is a view showing an example of color conversion;

FIGS. 11A and 11B are views for explaining logarithmic conversion;

FIGS. 12A and 12B are respectively a circuit diagram and a table for explaining a color correction circuit;

FIG. 13 shows unnecessary transmission regions of a filter;

FIG. 14 shows unnecessary absorption components of a filter;

FIGS. 15A to 15 C are respectively circuit diagrams and a view for explaining a character/image area separation circuit;

FIGS. 16A to 16 E are views for explaining the principle of outline regeneration;

FIGS. 17A to 17 N are views for explaining the principle of outline regeneration;

FIG. 18 is a circuit diagram of an outline regeneration circuit;

FIG. 19 is a circuit diagram of the outline regeneration circuit;

FIG. 20 is a timing chart of signals EN 1 and EN 2 ;

FIGS. 21A and 21B is a block diagram of a character/image correction unit;

FIGS. 22A to 22 D are views for explaining addition/subtraction processing;

FIG. 23 is a circuit diagram of a switching signal generation circuit;

FIG. 24 is a color residual removal processing circuit;

FIGS. 25A to 25 P are views, and FIG. 25Q is a flow chart, for explaining color residual removal processing, addition/subtraction processing, and the like;

FIG. 26 is a view showing edge emphasis processing;

FIG. 27 is a view showing smoothing processing;

FIGS. 28A to 28 C are respectively a circuit diagram and views for explaining image process and modulation using binary signals;

FIGS. 29A to 29 D are views showing character/image synthesizing processing;

FIG. 30 is a block diagram of an image process and edit circuit;

FIGS. 31A to 31 C are views showing texture processing;

FIG. 32 is a circuit diagram of a texture processing circuit;

FIG. 33 is a circuit diagram-of a zoom, mosaic, taper processing unit;

FIG. 34 is a circuit diagram of a mosaic processing unit;

FIGS. 35A to 35 F are views and a circuit diagram for explaining mosaic processing, and the like;

FIG. 36 is a circuit diagram of a line memory address control unit;

FIGS. 37A to 37 N are a circuit diagram, timing charts, and explanatory views of a mask bit memory, and the like;

FIG. 38 is a view showing addresses;

FIG. 39 is a view showing an example of a mask;

FIG. 40 is a circuit diagram of an address counter;

FIG. 41 is a timing chart in enlargement and reduction states;

FIGS. 42A to 42 C are views showing an example of enlargement and reduction;

FIGS. 43A to 43 C are circuit diagrams and a schematic view of a binarization circuit;

FIG. 44 is a timing chart of an address counter;

FIG. 45 is a chart showing an example of bit map memory write access;

FIGS. 46A to 46 D are views showing an example of character/image synthesizing processing;

FIG. 47 is a circuit diagram of a switch circuit;

FIGS. 48A to 48 C show an example of a non-linear mask;

FIGS. 49A to 49 F are explanatory views and a circuit diagram of an area signal generation circuit;

FIG. 50 shows area designation by a digitizer;

FIG. 51 is a circuit diagram of an interface with an external apparatus;

FIG. 52 shows a truth table of a selector;

FIGS. 53A and 53B show examples of rectangular and non-rectangular areas;

FIG. 54 shows an outer appearance of an operation unit;

FIGS. 55A , 55 B and 55 C is a chart for explaining a color conversion sequence;

FIGS. 56A , 56 B, 56 C and 56 D is a Chart for explaining a trimming area designation sequence;

FIG. 57 is a view for explaining the trimming area designation sequence;

FIG. 58 is a flow chart showing a circular area designation algorithm;

FIG. 59 is a flow chart showing an elliptical and R rectangular area designation algorithm;

FIGS. 60A , 60 B and 60 C is a chart for explaining a character synthesizing sequence;

FIGS. 61A , 61 B, 61 C, 61 D, 61 E and 61 F is a chart for explaining the character synthesizing sequence;

FIG. 62 is a chart for explaining the character synthesizing sequence;

FIGS. 63A-1 , 63 A- 2 and 63 B are charts for explaining texture processing;

FIGS. 64A and 64B are charts for explaining mosaic processing;

FIGS. 65A , 65 B, 65 C and 65 D is a chart for explaining an * mode sequence;

FIGS. 66A , 66 B and 66 C is a chart for explaining a program memory operation sequence;

FIGS. 67A and 67B is a chart for explaining the program memory operation sequence;

FIG. 68 is a chart for explaining the program memory operation sequence;

FIG. 69 is a flow chart showing a program memory registration algorithm;

FIG. 70 is a flow chart showing an algorithm of an operation after a program memory is called;

FIG. 71 shows a format of a recording table;

FIGS. 72A to 72 D are views showing image processing and edit processing;

FIGS. 73A to 73 C are respectively a partial circuit diagram and timing charts of a driver of a color laser beam printer;

FIGS. 74A and 74B are graphs showing contents of a gradation correction table;

FIG. 75 is a perspective view showing an outer appearance of a laser beam printer; and

FIGS. 76A and 76B are views for explaining non-rectangular area designation.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS:

The present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 schematically shows an internal arrangement of a digital color image processing system according to the present invention. The system of this embodiment comprises a digital color image reading apparatus (to be referred to as a color reader hereinafter) 1 , shown in the upper portion of FIG. 1 , and a digital color image print apparatus (to be referred to as a color printer hereinafter) 2 , shown in the lower portion of FIG. 1 . The color reader 1 reads color image information of an original in units of colors by a color separation means and a photoelectric transducer such as a CCD (to be described later), and converts the read information into an electrical digital image signal. The color printer 2 comprises an electrophotograpic laser beam color printer which reproduces color images in units of colors in accordance with the digital image signal and repeatedly transfers the reproduced images onto a recording sheet in a digital dot format, thereby recording an image.

The color reader 1 will be briefly described below.

The color reader 1 includes a platen glass 4 on which an original is to be placed, and a rod lens array 5 for converging an optical image reflected by an original which is exposure-scanned by a halogen exposure lamp 10 , and inputting the focused image onto an equi-magnification full-color sensor 6 . The components 5 , 6 , 7 , and 10 exposure-scan the original in a direction of an arrow Al together with an original scanning unit 11 . Color separation image signals of one line read during exposure scanning are amplified to predetermined voltages by a sensor output signal amplifier circuit 7 , and the amplified signals are input to a video processing unit 12 (to be described later) through a signal line 501 . The input signals are then subjected to signal processing. The video processing unit 12 and its signal processing will be described in detail later. The signal line 501 comprises a coaxial cable which can guarantee faithful signal transmission. A signal line 502 is used to supply drive pulses to the equi-magnification full-color sensor 6 . All the necessary drive pulses are generated by the video processing unit 12 . The color reader 1 also includes white and black plates 8 and 9 used for white and black level correction of image signals (to be described later). When the black and white plates 8 and 9 are irradiated with light emitted from the halogen exposure lamp 10 , signal levels of predetermined densities can be obtained. Thus, these plates are used for white and black level correction of video signals. The color reader 1 includes a control unit 13 having a microcomputer. The control unit 13 performs all the control operations of the color reader 1 , e.g., display and key input control of an operation panel 1000 through a bus 508 , control of the video processing unit 12 , detection of a position of the original scanning unit 11 using position sensors S 1 and S 2 through signal lines 509 and 510 , control of a stepping motor drive circuit for pulse-driving a stepping motor 14 or moving the original scanning unit 11 through a signal line 503 , ON/OFF control of the halogen exposure lamp 10 using an exposure lamp driver through a signal line 504 , control of a digitizer 16 and internal keys through a signal line 505 , and the like. In an original exposure-scanning mode, color image signals read by the exposure scanning unit 11 described above are input to the video processing unit 12 through the amplifier circuit 7 and the signal line 501 , and are subjected to various processing operations (to be described later). The processed signals are then sent to the color printer 2 through an interface circuit 56 .

The color printer 2 will be briefly described below. The printer 2 includes a scanner 711 . The scanner 711 comprises a laser output unit for converting image signals from the color reader 1 into light signals, a polygonal mirror 712 of a polygon (e.g., an octahedron), a motor (not shown) for rotating the mirror 712 , an f/θ lens (focusing lens) 713 , and the like. The color printer 2 includes a reflection mirror 714 , and a photosensitive drum 715 . A laser beam emerging from the laser output unit is reflected by the polygonal mirror 712 , and linearly scans (raster-scans) the surface of the photosensitive drum 715 via the lens 713 and the mirror 714 , thereby forming a latent image corresponding to an original image.

The color printer 2 also includes an entire surface exposure lamp 718 , a cleaner unit 723 for recovering a non-transferred residual toner, and a pretransfer charger 724 . These members are arranged around the photosensitive drum 715 .

Furthermore, the color printer 2 includes a developing unit 726 for developing an electrostatic latent image formed on the surface of the photosensitive drum 715 , developing sleeves 731 Y, 731 M, 731 C, and 731 Bk which are brought into direct contact with the photosensitive drum 715 to perform developing, toner hoppers 730 Y, 730 M, 730 C, and 730 Bk for storing supplementary toners, and a screw 732 for transferring a developing agent. These sleeves 731 Y to 731 Bk, the toner hoppers 730 Y to 730 Bk, and the screw 732 constitute the developing unit 726 . These members are arranged around a rotating shaft P of the developing unit. For example, when a yellow toner image is to be formed, yellow toner developing is performed at a position illustrated in FIG. 1 . When a magenta toner image is to be formed, the developing unit 726 is rotated about the shaft P in FIG. 1 , so that the developing sleeve 731 M in a magenta developing unit is located at a position where it can be in contact with the photosensitive drum 715 . Cyan and black images are developed in the same manner as described above.

The color printer 2 includes a transfer drum 716 for transferring a toner image formed on the photosensitive drum 715 onto a paper sheet, an actuator plate 719 for detecting a moving position of the transfer drum 716 , a position sensor 720 which approaches the actuator plate 719 to detect that the transfer drum 716 has moved to a home position, a transfer drum cleaner 725 , a sheet pressing roller, a discharger 728 , and a transfer charger 729 . These members 719 , 720 , 725 , and 729 are arranged around the transfer roller 716 .

The color printer 2 also includes sheet cassettes 735 and 736 for storing paper sheets (cut sheets), sheet feed rollers 737 and 738 for feeding paper sheets from the cassettes 735 and 736 , and timing rollers 739 , 740 , and 741 for taking sheet feed and convey timings. A paper sheet fed and conveyed via these rollers is guided to a sheet guide, and is wound around the transfer drum 716 while its leading end is carried by a gripper (to be described later). Thus, an image formation process is started.

Moreover, the color printer includes a drum rotation motor 550 for synchronously rotating the photosensitive drum 715 and the transfer drum 716 , a separation pawl 750 for separating a paper sheet from the transfer drum 716 after the image formation process is completed, a conveyor belt 742 for conveying the separated paper sheet, and an image fixing unit 743 for fixing a toner image on the paper sheet conveyed by the conveyor belt 742 . The image fixing unit 743 comprises a pair of heat and press rollers 744 and 745 .

An image processing circuit according to the present invention will be described below with reference to FIG. 2 and subsequent drawings. This circuit can be applied to a color image copying apparatus in which a full-color original is exposed with an illumination source such as a halogen lamp or a fluorescent lamp (not shown), a reflected color image is picked up by a color image sensor such as a CCD, and an obtained analog image signal is converted into a digital signal by an A/D converter or the like, the digital full-color image is processed, and the processed signal is output to a thermal transfer color printer, an ink-jet color printer, a laser beam color printer, or the like (not shown) to obtain a color image, or a color image output apparatus which receives a digital color image signal in advance from a computer, another color image reading apparatus, a color image transmission apparatus, or the like, performs processing such as synthesizing, and outputs the processed signal. This circuit can also be applied to a head for causing film boiling by heat energy to inject ink droplets, and a recording system using this head. This technique is disclosed in U.S. Pat. Nos. 4,723,129 and 4,740,793.

In FIG. 2 , an image reading unit A comprises staggered CCD line sensors 500 a , a shift register 501 a , a sample/hold circuit 502 a , an A/D converter 503 a , a positional aberration correction circuit 504 a , black correction/white correction circuit 506 a , a CCD driver 533 a , a pulse generator 534 a , and an oscillator 558 a.

The image processing circuit includes a color conversion circuit B, a LOG conversion circuit C, a color correction circuit D, a line memory O, a character/image correction circuit E, a character synthesizing circuit F, a color balance circuit P, an image process and edit circuit G, an edge emphasis circuit H, a character/image area separation circuit I, an area signal generation circuit J, a 400-dpi binary memory K, a 100-dpi binary memory L, an external apparatus interface M, a switch circuit N, a binarization circuit 532 , a driver R such as a laser driver for a laser beam printer, a BJ head driver for a bubble-jet printer, or the like, for driving a printer, and a printer unit S including the driver R.

A bubble-jet recording system is a recording system for injecting ink droplets by utilizing film boiling, and is disclosed in U.S. Pat. Nos. 4,723,129 and 4,740,793.

The image processing circuit also includes a digitizer 58 , the operation unit 1000 , an operation interface 1000 ′, RAMs 18 and 19 , a CPU 20 , a ROM 21 , a CPU bus 22 , and I/O ports 500 and 501 .

An original is irradiated with light emitted from an exposure lamp (not shown), and light reflected by the original is color-separated in units of color components, and read by the color read sensors 500 a . The read color image signals are amplified to predetermined levels by the shift register (or amplifier circuit) 501 a . The CCD driver 533 a supplies pulse signals for driving the color read sensors, and a necessary pulse source is generated by the system control pulse generator 534 a.

FIGS. 3A and 3B respectively show the color read sensors and drive pulses. FIG. 3A shows the color read .sensors used in this embodiment. Each color read sensor has 1,024 pixels in a main scan direction in which one pixel is defined as 63.5 μm (400 dots/inch (hereinafter dpi) so as to read the main scan direction while dividing it into five portions, and each pixel is divided into G. B, and R portions in the main scan direction. Thus, the sensor of this embodiment has a total of 1,024×3=3,072 effective pixels. Chips 58 to 62 are formed on a single ceramic substrate. First, third, and fifth sensors (or CCDs) ( 58 a , 60 a , and 62 a ) are arranged on a line LA, and second-and fourth sensors are arranged on a line LB separated from the line LA by four lines (63.5 μm×4=254 μm). These sensors scan in a direction of an arrow AL in an original read mode.

Of the five CCDs, the first, third, and fifth CCDs are independently and synchronously driven by a drive pulse group ODRV 118 a , and the second and fourth CCDs are independently and synchronously driven-by a drive pulse group EDRV 119 a . The pulse group ODRV 118 a includes charge transfer clocks 001 A and 002 A, and a charge reset pulse ORS, and the pulse group EDRV 119 a includes charge transfer clocks E 01 A and E 02 A, and a charge reset pulse,ERS. These clocks and pulses are completely synchronously generated not to be jitters to prevent mutual interferences and to attain noise reduction among the first, third and fifth pulses, and the second and fourth pulses. For this reason, these pulses are generated by one reference oscillation source OSC 558 a (FIG. 2 ).

FIG. 4A is a circuit diagram of a CCD drive pulse generation circuit for generating the pulse groups ODRV 118 a and EDRV 119 a , and FIG. 4B is a timing chart of the CCD drive pulses. The CCD drive pulse generation circuit is included in the system control pulse generator 534 a shown in FIG. 2. A clock KO 135 a obtained by frequency-dividing an original clock CLKO generated by the single OSC 558 a is used to generate reference signals SYNC 2 and SYNC 3 for determining generation timings of pulses ODRV and EDRV. The output timings of the reference signals SYNC 2 and SYNC 3 are determined by setup values of presettable counters 64 a and 65 a which are set by the CPU bus 22 . The reference signals SYNC 2 and SYNC 3 initialize frequency demultipliers 66 a and 67 a and drive pulse generation units 68 a and 69 a . The pulse groups ODRV 118 a and EDRV 119 a can be obtained as signals free from jitters since they are generated with reference to a signal HSYNC 118 input to this circuit on the basis of the clock CLK 0 output from the single oscillation source OSC 558 a and frequency-divided clocks which are all synchronously generated, thus preventing signal errors caused by interferences among sensors.

The synchronously obtained sensor drive pulses ODRV 118 a are supplied to the first, third, and fifth sensors 58 a , 60 a , and 62 a , and the sensor drive pulses EDRV 119 a are supplied to the second and fourth sensors 59 a and 61 a . The sensors 58 a , 59 a , 60 a , 61 a , and 62 a independently output video signals V 1 to V 5 in synchronism with the drive pulses. The video signals V 1 to V 5 are amplified to predetermined voltage values by independent amplifier circuits 501 - 1 to 501 - 5 in units of channels shown in FIG. 2 . The amplified signals V 1 , V 3 , and V 5 are output at a timing defined by clock signal OOS 129 a in FIG. 3B , and the amplified signals V 2 and V 4 are output at a timing defined by a clock signal EOS 134 a , and these signals are input to a video image processing circuit through a coaxial cable 101 a.

Color image signals obtained by reading an original while dividing the original into five portions and input to the video image processing circuit are separated into three colors, i.e., G (green), B (blue), and R (red) by the sample/hold (S/H) circuit 502 a . Therefore, after S/H processing, signals of 3×5=15 systems are subjected to signal processing.

The analog color signals sampled and held by the S/H circuit 502 a in units of R, G, and B are converted to digital signals in units of first to fifth channels by the next A/D converter 503 a . The digital signals of the first to fifth channels are parallelly and independently output to the next circuit.

In this embodiment, since the original is read by the five staggered sensors which have an interval of four lines (63.5 μm×4=254 μm) in a sub scan direction, and correspond to five divided areas in the main scan direction, as described above, the preceding second and fourth channels and the remaining first, third, and fifth channels have a positional aberration. In order to normally connect outputs of these channels, the positional aberration correction circuit 504 a comprising a memory of a plurality of lines corrects the positional aberration.

A black correction operation in the black correction/white correction circuit 506 a will be described below with reference to FIG. 5 A. FIG. 5B shows the principle of black correction. As shown in FIG. 5B , when the amount of light input to the sensors is very small, the black level outputs of the first to fifth channels largely vary among chips and pixels. If these signals are directly output to output an image, a stripe or nonuniform pattern is formed in the data portion of an image. Thus, a variation in black output must be corrected and correction is performed by the circuit shown in FIG. 5 A. Prior to the original read operation, the original scanning unit is moved to a position of the black plate having a uniform density and arranged on a non-image region at the distal end portion of an original table and a halogen lamp is turned on to input a black level image signal to this circuit. As for a blue signal B IN , in order to store this image data of one line in a black level RAM 78 a , a selector 82 a selects an A input ({circle around (d)}), a gate 80 a is disabled (â), and a gate 81 a is enabled. More specifically, data lines 151 a , 152 a and 153 a are connected in the order named. Meanwhile, ĉ is output to a selector 83 a so that an output 154 a of an address counter 84 a which is initialized by a signal {overscore (HSYNC)} and counts clocks VCLK is input to an address input 155 a of the RAM 78 a . Thus, a black level signal of one line is stored in the RAM 78 a (the above operation will be referred to as a black reference value fetch mode hereinafter).

In an image read mode, the RAM 78 a is set in a data read mode, and data of each pixel is read out and input to a B input of a subtracter 79 a via data lines 153 a and 157 a in units of lines. In this case, the gate 81a is disabled ({circle around (b)}), and the gate 80 a is enabled (â). The selector 86 a generates an A output. Therefore, for, e.g., the blue signal, a black correction circuit output 156 a is obtained as B IN (i)−DK(i)=B OUT (i) with respect to black level data DK(i) (to be referred to as a black correction mode hereinafter). Similarly, the same control is performed for a green signal G IN and a red signal R IN by circuits 77 a G and 77 a R. Control lines â, {circle around (b)}, ĉ, {circle around (d)}, and ê for selector gates for attaining this control are selected by a latch 85 a assigned as I/Os of the CPU 20 under the control of the CPU. When the selectors 82 a , 83 a , and 86 a select B inputs, the CPU 20 can access the RAM 78 a.

White level correction (shading correction) in the black correction/white correction circuit 506 a will be described below with reference to FIGS. 6A to 6 D. In white level correction, variations in sensitivities of an illumination system, an optical system, and sensors are corrected on the basis of white data obtained when the original scanning unit is moved to a position of the uniform white plate and radiates light onto the white plate. FIG. 6A show a basic circuit arrangement. The basic circuit arrangement is the same as that shown in FIG. 5A. A difference between black and white correction operations is as follows. Black correction is performed by the subtracter 79 a , while in white correction, a multiplier 79 a ′ is used. Thus, a description of the same parts will be omitted.

When the CCDs ( 500 a ) for reading an original are located at a reading position of the uniform white plate (home position) in a color correction mode, an exposure lamp (not shown) is turned on, and image data of a uniform white level is stored in a one-line correction RAM 78 a ′ prior to a copying operation or a reading operation. For example, if the main scan width corresponds to a width in a longitudinal direction of an A4 size, 16×297 mm=4,752 pixels for 16 pels/mm, that is, the capacity of the RAM is at least 4,752 bytes, and data of the white plate in units of pixels are stored in the RAM 78 a ′, as shown in FIG. 6C , when white plate data Wi of an ith pixel (i=1 to 4,752) is as shown in FIG. 6B showing the principle of white correction.

A normal image read value Di of an ith pixel must be corrected with reference to Wi to obtain corrected data Do=Di×FF H /Wi. The CPU 20 outputs data to signal lines â′, {circle around (b)}′, ĉ′, and {circle around (d)}′ of a latch 85 a ′ so that gates 80 a ′ and 81 a ′ are enabled, and selectors 82 a ′, 83 a ′, and 86 a ′ select B inputs. As a result, the CPU 20 can access a RAM 78 a ′. In a white correction sequence shown in FIG. 6D , the CPU 20 sequentially calculates FF H /W 0 for the start pixel W 0 , FF/W 1 for a pixel W 1 , etc. and substitutes data. When the CPU 20 completes calculations of a blue component-of a color component image (step B in FIG. 6 D), it similarly performs calculations for a green component (step G), and a red component (step R). Thereafter, the gate 80 a ′ is enabled (â′), the gate 81 a ′ is disabled ({circle around (b)}′), and the selectors 83 a ′ and 86 a ′ select A inputs, so that Do=Di×FF H /Wi is output in response to input original image data Di. Coefficient data FF H /Wi read out from the RAM 78 a ′ is-multiplied with original image data 151 a ′ from one input terminal via signal lines 153 a ′ and 157 a ′, and the product is then output.

As described above, black and white levels are corrected on the basis of various factors such as a black level sensitivity of an image input system, a variation in dark current of CCDs, a variation in sensitivity among sensors, a variation in light amount of an optical system, a white level sensitivity, and the like. Furthermore, image data B OUT 101 , G OUT 102 , and R OUT 103 , whose white and black levels are uniformly corrected in units of colors in the main scan direction, are obtained. Upon istruction from an operation unit (not shown), the black- and white-level corrected color separation image data are supplied to the color conversion circuit B in order to detect a pixel having a specific color density or a specific color ratio and to convert the detected data into another color density or ratio as instructed by the operation unit.

Color Conversion

FIG. 7 is a block diagram of the color conversion (gradation color conversion and density color conversion) unit. The circuit shown in FIG. 7 comprises a color detection unit 5 b for judging an arbitrary color set in a register 6 b by the CPU 20 from 8-bit color separation signals R IN , G IN , and B IN ( 1 b to 3 b ), an area signal Ar 4 b for performing color detection and color conversion at a plurality of positions, line memories 10 b and 11 b for performing processing to expand a signal of “specific color” output from the color detection unit (to be referred to as a hit signal hereinafter) in a main or sub scan direction (only in the sub scan direction in FIG. 7 ), an OR gate 12 b , line memories 13 b to 16 b for synchronizing a color conversion enable signal 33 b with input color separation data (R IN , G IN , and B IN 1 b to 3 b ) and the area signal Ar 4 b , delay circuits 17 b to 20 b , a color conversion unit 25 b for performing color conversion on the basis of the enable signal 33 b , the synchronized color separation data (R IN ′, G IN ′, and B IN ′ 21 b to 23 b ), an area signal Ar 24 b , and color-converted color data set in a register 26 b . The color conversion enable signal 33 b is generated by an AND gate 32 b based on the expanded hit signal 34 b and a non-rectangular signal (including rectangle) BHi 27 b . A hit signal H OUT 31 b is output in synchronism with color-converted color separation data (R OUT , G OUT , and B OUT 28 b to 30 b ).

An algorithm of gradation color judgement and gradation color conversion will be briefly described below. Note that gradation color judgement or conversion means that color judgement or conversion of colors having the same hue is performed so that color conversion is performed while preserving a density value of colors having the same hue.

As the same color (or hue), it is known that ratios of a red signal R 1 , a green signal G 1 , and a blue signal B 1 are equal to each other.

Thus, data M 1 of one (maximum value color, to be referred to as a main color hereinafter) of colors to be color-converted is selected, and ratios of the selected color to the remaining two color data are calculated. For example, when the main color is R, M 1 =R to calculate G 1 /M 1 and B 1 /M 1 .

A pixel in which the following relations are established for input data R i , G i , and B i is determined as a pixel to be color-converted: $$ R i × G 1 M 1 × α 1 ≦ G i ≦ R i × G 1 M 1 × α 2 ( 1 ) R i × B 1 M 1 × β 1 ≦ B i ≦ R i × B 1 M 1 × β 2 ( 2 )   M 1 ×γ 1 ≦R i ≦M 1 ×γ 2   (3)

For α 1 , β 1 , γ 1 ≦1

α 2 , β 2 , γ 2 ≧1

For color-converted data (R 2 , G 2 , and B 2 ), ratios of data M 2 of a main color to the remaining two color data are calculated.

For example, when G 2 is a main color, M 2 =G 2 , and R 2 /M 2 and B 2 /M 2 are calculated.

For the main color M 1 of input data, M 1 ×(R 2 /M 2 ) and M 1 ×(B 2 /M 2 ) are calculated.

If data represents a pixel to be color-converted, (M 1 ×(R 2 /M 2 ), M 1 , and M 1 ×(B 2 /M 2 )) are output; if it does not represent a pixel to be color-converted, (R i , G i , and B i ) are output.

Thus, all the same hue portions having gradation are detected, and color-converted data according to the gradation can be output.

FIG. 8 is a block diagram showing a color judgement circuit. This circuit detects a pixel to be color-converted.

The circuit shown in FIG. 8 includes a smoothing unit 50 b for smoothing input data R IN 1 b , G IN 2 b , and B IN 3 b , a selector 51 b for selecting one (main color) of the -outputs from the smoothing unit, selectors 52 b R , 52 b G , and 52 b B each for selecting one of the output from the selector 51 b and a fixed value R 0 , G 0 , or B 0 , OR gate 54 b R , 54 b G , or 54 b B , selectors 63 b , 64 b R , 64 b G , and 64 b B for setting a select signal in the selectors 51 b , 52 b R , 52 b G , and 52 b B based on area signals Ar 10 and Ar 20 , and multipliers 56 b R , 56 b G , 56 b B , 57 b R , 57 b G , and 57 b B for calculating upper and lower limits.

Upper limit ratio registers 58 b R , 58 b G , and 58 b B , and lower limit ratio registers 59 b R , 59 b G , and 59 b B set by the CPU 20 can be set up with data for performing color detection of a plurality of areas on the basis of an area signal Ar 30 .

The area signals Ar 10 , Ar 20 , and Ar 30 are signals generated based on the area signal Ar 4 b shown in FIG. 7 , and are respectively output through necessary numbers of DF/Fs. The circuit of FIG. 8 also includes an AND gate 61 b , an OR gate 62 b , and a register 67 b.

An actual operation will be described below. One of data R′, G′, and B′, obtained by smoothing data R IN 1 b , G IN 2 b , and B IN 3 b is selected by the selector 51 b based on a select signal S 1 set by the CPU 20 , thereby selecting main color data. Note that the CPU 20 sets different data A and B in registers 65 b and 66 b , and the selector 63 b selects one of the data A and B in accordance with the signal Ar 10 , and sends the selected data as the select signal S 1 to the selector 51 b.

In this manner, the two registers 65 b and 66 b are prepared, the different data are input to the A and B inputs of the selector 63 b , and one of these data is selected in accordance with the area signal Ar 10 . With this arrangement, color detection can be separately performed for a plurality of areas. The area signal Ar 10 need not be a signal for only a rectangular area but can be one for a non-rectangular area.

Each of the next selectors 52 b R , 52 b G , and 52 b B selects one of data R 0 , G 0 , or B 0 , set by the CPU 20 , and the main color data, selected by the selector 51 b in accordance with a select signal generated based on outputs 53 ba to 53 bc from a decoder 53 b (not shown) and a fixed color mode signal S 2 . Note that the selectors 64 b R , 64 b G , and 64 b B select one of the data A and B in accordance with the area signal Ar 20 , so that they can detect different colors for a plurality of areas as in the selector 63 b . In this case, the data R 0 , G 0 , and B 0 are selected in conventional color conversion (fixed color mode) and for a main color in gradation color judgement, and the main color data is selected for colors other than the main color in gradation color conversion.

An operator can select fixed or gradation color judgement, whichever is desired, from an operation unit. Alternatively, the fixed or gradation color judgement selection can be selected by software on the basis of color data (non-converted color data) input from an input device, e.g., a digitizer.

The outputs from these selectors 52 b R , 52 b G , and 52 b B and upper and lower limit values of data R′, G′, and B′ from the upper limit ratio registers 58 b R , 58 b G , and 58 b B and the lower limit ratio registers 59 b R , 59 b G , and 59 b B are multiplied with each other by multipliers 56 b R , 56 b G , and 56 b B , and 57 b R , 57 b G , and 57 b B , and the products are set in window comparators 60 b R , 60 b G , and 60 b B .

The AND gate 61 b checks if main color data falls within a predetermined range and if two colors other than the main color fall within a predetermined range in the window comparators 60 b R , 60 b G , and 60 b B . The register 67 b can set “1” according to an enable signal 68 b from the judgement unit regardless of a judgement signal. In this case, a color to be converted is present in a portion which is set to be “1”.

With this arrangement, fixed or gradation color judgement can be performed for a plurality of areas.

FIG. 9 is a block diagram of a color conversion circuit. This circuit selects a color-converted signal or an original signal on the basis of the output 7 b from the color detection unit 5 b.

In FIG. 9 , the color conversion unit 25 b comprises a selector 111 b , registers 112 b R1 , 112 b R2 , 112 b G1 , 112 b G2 , 112 b B1 , and 112 b B2 in each of which a ratio of a converted color to main color data (maximum value) is set, multipliers 113 b R , 113 b G , and 113 b B , selectors 114 b R , 114 b G , and 114 b B , selectors 115 b R , 115 b G , and 115 b B , an AND gate 32 b , selectors 117 b , 112 b R , 112 b G , 112 b B , 116 b R , 116 b G , and 116 b B for setting data, which is set by the CPU 20 in accordance with area signals Ar 50 , Ar 60 , and Ar 70 generated based on the-area signal Ar′ 24 b in FIG. 7 , in the selector 111 b , the multipliers 113 b R , 113 b G , and 113 b B , the selectors 114 b R , 114 b G , 114 b B , respectively, and a delay circuit 118 b.

The actual operation will be described below.

The selector lllb selects one of input signals (main color) R IN ′ 21 b , G IN ′ 22 b , and B IN ′ 23 b in accordance with a select signal S 5 . The signal S 5 is generated such that an area signal Ar 40 causes the selector 117 b to select one of A and B inputs corresponding to two data set by the CPU 20 . In this manner, color conversion processing for a plurality of areas can be achieved.

The signal selected by the selector 111 b is multiplied with register values set by the CPU 20 by the multipliers 113 b R , 113 b G , and 113 b B. In this case, the area signal Ar 50 causes the selectors 112 b R , 112 b G , and 112 b B to select pairs of register values 112 b R1 · 112 b R2 , 112 b G1 · 112 b G2 , and 112 b B1 · 112 b B2 , thus also achieving color conversion processing for a plurality of areas.

Each of the selectors 114 b R , 114 b G , and 114 b B selects one of the products and a fixed value selected by the selector 116 b R , 116 b G , or 116 b B from a pair of fixed values R O ′·R O ″, G O ′·G O ″, or B O 40 ·B O ″ set by the CPU 20 in accordance with a mode signal S 6 . In this case, the mode signal S 6 is selected by the area signal Ar 60 in the same manner as in the signal S 5 .

Finally, each of the selectors 115 b R , 115 b G , and 115 b B selects one of data R IN ″, G IN ″, and B IN ″ (obtained by delaying the data R IN ′, G IN ′, and B IN ′ to adjust timings) and the output from the selector 114 b R , 114 b G , or 114 b B . As a result, data R OUT , G OUT , and B OUT are output. In addition, a hit signal H OUT is also output in synchronism with the data R OUT , G OUT , and B OUT .

A select signal S B ′ is obtained by delaying an AND product of a color judgement result 34 b and a color conversion enable signal BHi 27 b . The signal BHi (for example, a non-rectangular enable signal as the dotted line in FIG. 10 ) is input so that color conversion processing can be performed for a non-rectangular area. In this case, an area signal is generated on the basis of the area connected by an alternate long and short dashed lines, i.e., coordinates of an uppermost left position (“a” in FIG. 10 ), an uppermost right position (“b” in FIG. 10 ), a lowermost right position (“c” in FIG. 10 ), and a lowermost left position (“d” in FIG. 10 ). The non-rectangular area signal BHi is an area signal which is input from an input device such as a digitizer, and is developed in the 100-dpi binary memory L. When color conversion is performed using the non-rectangular enable signal, an enable area can be designated along a boundary of a portion to be converted. Therefore, a color detection threshold range can be widened as compared to conventional color conversion using a rectangle. Therefore, the detection power can be increased and an output image subjected to gradation color conversion with high precision can be obtained.

Color conversion having a lightness according to a main color of the color detection unit 5 b (for example, when red is gradation-color-converted to blue, light red is converted to light blue, and dark red is converted to dark blue) or fixed value color conversion can be performed as desired for a plurality of areas.

As will be described later, mosaic processing, texture processing, trimming processing, masking processing, and the like can be executed for only an area (non-rectangular or rectangular area) of a specific color on the basis of the hit signal H OUT .

The area signals Ar 10 , Ar 20 , and Ar 30 are generated based on the area signal Ar 4 b , and the area signals Ar 40 , Ar 50 , Ar 60 , and Ar 70 are generated based on the area signal Ar′ 24 b . These signals are generated based on an area signal 134 from the area signal generation circuit J (FIG. 2 ). These signals need not always be rectangular area signals but may be non-rectangular area signals. More specifically, the non-rectangular area signal BHi stored in the 100-dpi binary memory and based on non-rectangular area information may be used.

A method of generating the signal BHi will be described later. The signal BHi can include both rectangular and non-rectangular area signals.

As described above, according to this embodiment, since a color conversion area can be set based not only on a rectangular area signal but also on a non-rectangular area signal, color conversion processing can be executed with higher precision.

As shown in FIG. 2 , the outputs 103 , 104 , and 105 from the color conversion circuit B are supplied to the LOG conversion circuit C for converting image data proportional to a reflectance to density data, the character/image area separation circuit I for discriminating between a character area, a halftone area, and a dot area on an original, and the external apparatus interface M for causing this system to communicate data with an external apparatus through cables 135 , 136 , and 137 .

Input color image data proportional to a light amount is input to the LOG conversion circuit C ( FIG. 2 ) to match it with spectral luminous efficiency characteristics of the human eye.

In this circuit, the data is converted so that white=00 H and black=FF H . Since input gamma characteristics vary depending on types of image source input to the image read sensor (e.g., a normal reflective original, a transparent original, (e.g., a film projector), a transparent original of another type (e.g., a negative film, a positive film, or a film sensitivity), or an exposure state), a plurality of LOG conversion LUTs (Look-Up Tables) are-prepared, as shown in FIGS. 11A and 11B , and are selectively used according to applications. The LUTs are selected by signal lines lg 0 , lg 1 , and lg 2 in accordance with an instruction input from the operation unit 1000 or the like as an I/O port. Data output for. B, G, and R correspond to density values of an output image. Since signals B (blue), G (green), and R (red) correspond to toner amounts of Y (yellow), M (magenta), and C (cyan), the following image data correspond to yellow, magenta, and cyan.

A color correction circuit performs color correction of color component image data from an original image obtained by the LOG conversion, i.e., yellow, magenta, and cyan components as follows. It is known that spectral characteristics of color separation filters arranged in correspondence with pixels in the color read sensors have unnecessary transmission regions, as indicated by hatched portions in FIG. 13 , and color toners (Y, M, and C) transferred to a transfer sheet have unnecessary absorption components, as shown in FIG. 14 . Thus, as is well known, masking correction is executed to calculate the following linear equation of the color-component image data Yi, Mi, and Ci to perform color correction: $$ [ Yo Mo Co ] = [ a Y1 - a Y2 - a Y3 ⁢ - b M1 b M2 - b M3 ⁢ - c C1 - c C2 c C3 ] ⁡ [ Yi Mi Ci ]

Furthermore, a black addition operation for calculating Min(Yi, Mi, Ci) (minimum value of Yi, Mi, and Ci) using Yi, Mi, and Ci, and adding a black toner based on the calculated value as a black component, and an undercolor removal (UCR) operation for decreasing amounts of color agents to be added in accordance with an amount of an added black component are often executed. FIG. 12A shows a circuit arrangement of the color correction circuit D for performing masking, black addition, and UCR. The characteristic features of this arrangement are:

(1) This arrangement has two systems of masking matrices, and these matrices can be switched at high speed according to “1/0” of one signal line.

(2) The presence/absence of UCR can be switched at high speed according to “1/0” of one signal line.

(3) This arrangement has two systems of circuits for determining a black toner amount, and these circuits can be switched at high speed according to “1/0” of a signal line.

Prior to image reading, desired first and second matrix coefficients M 1 and M 2 are set by a bus connected to the CPU 20 . In this embodiment, we have: $$ M 1 = ( a ⁢   ⁢ Y 1 - a ⁢   ⁢ Y 2 - a ⁢   ⁢ Y 3 ⁢ - b ⁢   ⁢ M 1 b ⁢   ⁢ M 2 - b ⁢   ⁢ M 3 ⁢ - c C1 - c C2 c C3 ) , M 2 = ( αY 1 - αY 2 - αY 3 ⁢ - βM 1 βM 2 - βM 3 ⁢ - γ ⁢   ⁢ C 1 - γ ⁢   ⁢ C 2 γ ⁢   ⁢ C 3 )

The matrix coefficients M 1 are set in registers 87 d to 95 d , and the coefficients M 2 are set in registers 96 d to 104 d.

Each of selectors 111 d to 122 d , 135 d , 131 d , and 136 d selects an A input when its S terminal=“1” and selects a B input when its S terminal=“0”. Therefore, when the matrix M 1 is selected, a switching signal MAREA 364 is set to be “1”; when the matrix M 2 is selected, the signal 364 is set to be “0”.

A selector 123 d obtains outputs a, b, and c based on the truth table shown in FIG. 12B according to select signals C 0 and C 1 ( 366 d and 367 d ). The select signals C 0 , C 1 , and C 2 are set to be (C 2 , C 1 , C 0 )=(0, 0, 0), (0, 0, 1), (0, 1, 0), and (1, 0, 0), and (0, 1, 1) for a monochrome signal in the order of, e.g., Y. M, C, and Bk, thereby obtaining desirably color-corrected color signals. Assuming that (C 0 , C 1 , C 2 )=(0, 0, 0) and MAREA=“1”, the contents of the registers 87 d , 88 d , and 89 d , i.e., (a Y1 , −b M1 , −c C1 ) appear at the outputs (a, b, c) of the selector 123 d . On the other hand, a black component signal 374 d calculated by Min(Yi, Xi, Ci)=k based on the input signals Yi, Mi, and Ci undergoes linear conversion given by Y=ax−b (where a and b are constants) by a linear converter 137 d , and the obtained signal is input to B inputs of subtracters 124 d , 125 d , and 126 d . The subtracters 124 d to 126 d calculate Y=Yi−(ak−b), M=Mi−(ak−b), and C=Ci−(ak−b) as UCR processing, and output the results to multipliers 127 d , 128 d , and 129 d for performing masking calculations.

The multipliers 127 d , 128 d , and 129 d receive (a Y1 , −b M1 , −c C1 ) at their A inputs, and the above-mentioned [Yi−(ak−b), Mi−(ak−b), Ci−(ak−b)]=[Yi, Mi, Ci] at their B inputs. Thus, as can be seen from FIG. 12A , Y OUT =Yi×(a Y1 )+Mi×(−b M1 )+Ci×(−c C1 ) is obtained under the condition of C 2 =0 (Y or M or C). Thus, yellow image data subjected to masking color correction and UCR processing is obtained. Similarly, the following data are output to D OUT :

M OUT =Yi ×(− a Y2 )+ Mi ×(− b M2 )+ Ci ×(− c C2 )

C OUT =Yi ×(− a Y3 )+ Mi ×(− b M3 )+ Ci ×(− c C3 )

Color selection is controlled by the CPU 20 in accordance with an output order to a color printer and the truth table shown in FIG. 12B based on (C 0 , C 1 , C 2 ). Registers 105 d to 107 d , and 108 d to 110 d are used to form a monochromatic image. An output can be obtained by performing weighting addition of colors by MONO=k 1 Yi+l 1 Mi+m 1 Ci.

When a Bk signal is output, C 2 =1 according to the select signal C 2 ( 368 ). input to the selector 131 d , that is, a Bk signal is subjected to linear conversion given by Y=cx−d by a linear converter 133 d , and is output from the selector 131 d . A black component signal BkMJ 110 is output to an outline portion of a black character on the basis of the output from the character/image area separation circuit I (to be described later). Color switching signals C 0 ′, C 1 ′, and C 2 ′ 366 to 368 are set by an output port 501 connected to the CPU bus 22 , and the signal MAREA 364 is output-from the area signal generation circuit J. Gate circuits 150 d to 153 d control so that when DHi=“1” based on the non-rectangular area signal DHi 22 read out from a binary memory (bit map memory) L 537 , signals C 0 ′, C 1 ′, C 2 ′=“1, 1, 0”, thereby automatically outputting data for a monochromatic image.

Character/Image Area Separation Circuit

FIG. 15A shows the character/image area separation circuit I. The character/image separation circuit I, using read image data checks if the image data represents a character or an image or in chromatic or achromatic color. The processing flow of this circuit will be described below with reference to FIGS. 15A to 15 C.

The data R (red) 103 , G (green) 104 , and B (blue) 105 input from the color conversion circuit B to the character/image area separation circuit I are input to a minimum value detection circuit MIN(R,G,B) 101 I, and a maximum value detection circuit MAX(R,G,B) 102 I. These blocks select maximum and minimum values based on three different luminance signals of input R, G. and B data. A difference between the selected signals is calculated by a subtracter 104 I. If the difference is large, i.e., when input R, G, and B data are not uniform, it indicates that input signals are not achromatic color signals representing black or white but chromatic color signals deviated to a certain color. Of course, when the difference is small, the R, G, and B signals are at almost the same levels, and are achromatic signals which are not deviated to a certain color. This difference signal is output to a delay circuit Q as a gray signal GR 125 . This difference is compared with a threshold value arbitrarily set in a register 111 I by the CPU 20 by a comparator 121 I, and a comparison result is output to the delay circuit Q as a gray judgement signal GRB 126 . The phases of these signals GR 125 and GRBi 126 are matched with those of other signals by the delay circuit Q. Thereafter, these signals are input to the character/image correction circuit E (to be described later), and are used as processing judgement signals.

Meanwhile, the minimum value signal obtained by the circuit MIN(R,G,B) 101 I is also input to an edge emphasis circuit 103 I. The edge emphasis circuit 1031 performs the following calculation using adjacent pixel data in the main scan direction, thereby performing edge emphasis: $$ D OUT = 9 8 ⁢   ⁢ D i - 1 16 ⁢   ⁢ ( D i - 1 + D i + 1 )

D OUT : edge-emphasized image data

Di: ith pixel data

Note that the edge emphasis is not limited to the above-mentioned method, and various other known methods may be used. Line memories for performing a delay of 2 lines or 5 lines in the sub scan direction are arranged, and a 3×3 or 5×5 pixel block is used, so that normal edge emphasis can be performed. In this case, the edge emphasis effect can be obtained not only in the main scan direction but also in the sub scan direction. Thus, the edge emphasis effect can be enhanced. With this edge emphasis, precision of black character detection (to be described below) can be effectively improved.

The image signal which is edge-emphasized in the main scan direction is then subjected to average value calculations in 5×5 and 3×3 pixel windows by 5×5 and 3×3 average circuits 109 I and 110 I. Line memories 105 I to 108 I are sub scan delay memories for performing average value processing. The average value of a total of 5×5=25 pixels calculated by the 5×5 average circuit 109 I is added to offset values independently set in offset units connected to the CPU bus 22 by adders 115 I, 120 I, and 125 I. The added 5×5 average values are input to a limiter 1 ( 113 I), a limiter 2 ( 118 I), and a limiter 3 ( 123 I). The limiters are connected to the CPU bus 22 , and limiter values can be independently set in these limiters. When the 5×5 average value is larger than a setup limiter value, an output is clipped by the limiter value. The output signals from the limiters are respectively input to a comparator 1 116 I, a comparator 2 121 I, and a comparator 3 126 I. The comparator 1 116 I compares the output from the limiter 1 113 I with the output from the 3×3 average circuit 110 I. The comparison output of the comparator 1 116 I is input to a delay circuit 117 I, so that its phase is to be matched with an output signal from a dot area judgement circuit 122 I (to be described later). The signal is binarized using average values of the 5×5 and 3×3 pixel blocks in order to prevent painting and omissions caused by the MTF at a predetermined density or more, and is filtered through a 3×3 low-pass filter, so that high-frequency components of a dot image are cut so as not to detect dots of the dot image upon binarization.

The output signal from the comparator 2 ( 121 I) is subjected to binarization with through image data so as to detect high-frequency components of an image, so that a dot area can be detected by the next dot area judgement circuit 122 I. The dot area judgement circuit 122 I recognizes a dot from a direction of an edge since a dot image is constituted by a set of dots, and counts the number of dots around it, thereby detecting a dot image. More specifically, the circuit 122 I performs dot judgement as follows.

[Dot Judgment]

The dot area judgement circuit 122 I will be described below with reference to FIG. 15B. A signal 101 J binarized by the comparator 2 ( 121 I) of the character/image area separation circuit ( FIG. 15A ) is delayed by one line in each of one-line delay memories (FIFO memories) 102 J and 103 J shown in FIG. 15 B. Thus, the binary signal 101 J, and the signals delayed by the FIFO memories 102 J and 103 J are input to an edge detection circuit 104 J. The edge detection circuit 104 J independently detects edge directions for a total of four directions, i.e., vertical, horizontal, and two oblique directions with respect to an objective pixel. After the edge directions are quantized in 4 bits by the edge detection circuit, the 4-bit edge signal is input to a dot detection circuit 109 J and a one-line delay memory (FIFO memory) 105 J. 4-bit edge signals delayed by one line each by the FIFO memory 105 J, and one-line delay memories (FIFO memories) 106 J, 107 J, and 108 J are input to the dot detection circuit 109 J. The dot detection circuit 109 J judges based on surrounding edge signals whether or not an objective pixel is a dot. For example, as indicated by hatched portions in the dot detection circuit l 09 J in FIG. 15B , a total of seven pixels of previous two lines including an objective pixel include at least one pixel corresponding to an edge in a ⊥ direction (a density gradient is present in a direction of the objective pixel), and a total of seven pixels ( pixels) of the following two lines including the objective pixel include at least one pixel corresponding to an edge in a direction (a density gradient is present in the direction of the objective pixel). In addition, when there are edges of and or and in the horizontal direction, it is determined as a dot. A dot is determined when and ⊥. After the dot judgement result is similarly delayed by one-line delay memories 110 J and 111 J, the delayed results are fattened by a fattening circuit 112 J. When there is at least one pixel which is determined as a dot in a total of 12 pixels (=3 lines×4 pixels), the fattening circuit 112 J judges the objective pixel as a dot regardless of the judgement result of the objective pixel. The fattened dot judgement result is delayed by one line by each of one-line delay memories 113 J and 114 J. The output from the fattening circuit 112 J and the signal delayed by a total of two lines by the one-line delay memories 113 J and 114 J are input to a majority-rule decision circuit 115 J. The majority-rule decision circuit 115 J samples every four pixels from lines before and after a line including the objective pixel. The circuit 115 J samples pixels from 60-pixel widths on the right and left sides of the objective pixel, that is, samples 15 pixels each from the right and left pixel widths, i.e., a total of 30 pixels from two lines, thereby calculating the number of pixels which are judged as dots. If the calculated value is larger than a preset value, it can be determined that the objective pixel is a dot.

In the copying machine of this embodiment, the moving speed of the image reading unit of the image reader is changed according to a magnification in the sub scan direction (sheet feed direction). In this case, in order to perform accurate dot judgement, FIFO memory control of the one-line delay memories 102 J, 103 J, 105 J, 106 J, 107 J, 108 J, 110 J, 111 J, 113 J, and 114 J is performed up to a predetermined magnification such that write access is made for one of two lines, and no write access is made for the other line.

Since the write access of the FIFO memories is controlled in this manner, dot judgement can be performed using an equi-magnification image even in a zoom mode. Thus, judgement precision in the zoom mode can be improved. The types of filters for edge detection, the sizes of matrices of the dot detection circuits, the fattening circuit, and the majority-rule decision circuit are not limited to those described in the above embodiment, and sub scan thinning in the zoom mode may be performed every three lines. Thus, various modifications may be made.

Sampling in an enlargement state will be described below with reference to FIG. 15C. {circle around (1)} of FIG. 15C shows an original image. When an image is read at an equi-magnification, an original image is read within dotted lines shown in {circle around (1)} in FIG. 15 C. This image is continuously written in the FIFO memories in units of lines. More specifically, as shown in {circle around (2)} in FIG. 15C , all the line data are written in the FIFO memories without omissions. An enlargement state will be described below. For the sake of simplicity, a 200% enlargement state will be described. As described above, the moving speed of the reading unit is decreased in the enlargement state. For this reason, in the 200% enlargement state, the moving speed is halved, and a one-line image is read by a width half a one-line width. {circle around (3)} in FIG. 15C shows a read image in correspondence with an original image.

As shown in {circle around (4)} in FIG. 15C , the read image data is written in the FIFO memories in the same manner as in the equi-magnification state. In this state, write access of the FIFO memories is performed while data is thinned every other line, as shown in {circle around (4)} in FIG. 15 C.

In this embodiment, the 200% enlargement state has been described. Write access is performed once per two lines. This write method can be modified according to a magnification in the zoom mode.

The judgement result from the dot area judgement circuit 122 I and the signal from the delay circuit 117 are locally ORed by an OR gate 129 I. An error judgement is eliminated from the logical sum by an error judgement and elimination circuit 130 I, and the obtained signal is output to an AND gate 132 I. The OR gate 129 I outputs a judgement signal which is judged as a halftone area or a dot area. By utilizing the characteristic that a small area is present in a character, and a large area is present in an image such as a photograph, the error judgement and elimination circuit 130 I thins an image area, and eliminates isolated image areas. More specifically, if there is at least one pixel other than that of an image such as. a photograph within a 1 (mm)×1 (mm) area around a central pixel xij, it is determined that the central pixel falls outside an image area. More specifically, binary signals within the area are logically ANDed, and only when all “1”s are obtained is the central pixel xij=1 set. After isolated image areas are removed in this manner, the fattening processing is executed to recover the thinned image area. More specifically, if there is at least one pixel of an image area such as a photograph within a 2 (mm)×2 (mm) area, the central pixel xij is determined as an image area. In the fattening processing, thinned binary signals are logically ORed within the area, and when at least one pixel is “1” (image area), the central pixel xij=1 is set.

The error judgement and elimination circuit 130 I outputs an inverted signal of the fattened binary signal. The inverted signal serves as a mask signal of halftone and dot images.

Similarly, the output from the dot area judgement circuit 122 I is directly input to an error judgement and elimination circuit 131 I and is subjected to thinning processing and fattening processing.

Note that the mask size of the thinning processing is set to be equal to or smaller than that of the fattening processing, so that the fattened judgement result can cross. More specifically, in both the error judgement and elimination circuits 130 I and 131 I, after thinning processing using a 17×17 pixel mask, another thinning is executed using a 5×5 pixel mask.

Thereafter, fattening processing is executed using a 34×34 pixel mask. An output signal SCRN 127 from the error judgement and elimination circuit 131 I serves as a judgement signal for executing smoothing processing of only a dot judgement portion in the character/image correction circuit E (to be described later) and for preventing moiré of a read image.

An output signal from the comparator 3 126 I is subjected to outline extraction so as to obtain a sharp character in the next circuit. As an extraction method, the binarized output of the comparator 3 126 I is subjected to thinning processing and fattening processing using a 5×5 pixel block, and a difference between the fattened and thinned signal is determined as an outline. An outline signal extracted in this manner is input to a delay circuit 128 I so that its phase is matched with the mask signal output from the error judgement and elimination circuit 130 I. Thereafter, a portion of the outline signal, which is judged as an image, is masked by the mask signal by an AND gate 132 I, thereby outputting an outline signal of an original character portion. The output from the AND gate 132 I is output to an outline regeneration unit 133 I.

The reason why average values in the 5×5 and 3×3 windows are calculated, as described above, is to detect a halftone area. The matrix sizes and window sizes are not limited to those described above, and average values of two different areas including an objective pixel need only be calculated.

The matrix sizes of the thinning processing and fattening processing in the error judgement and elimination circuits 130 I and 131 I can also be arbitrarily set.

As described above, according to the outline edge extraction algorithm of this embodiment, not only a frame signal is extracted but also it is logically ANDed with a mask signal based on a halftone or dot signal. Thus, character/image areas can be separated with high precision.

Since appropriate offsets can be set in average values of 5×5 pixel blocks used in detection of halftone, dot, and character areas by the CPU 20 , these areas can be precisely detected.

Furthermore, according to this embodiment, since the output signal from the dot area judgement circuit and a binary signal indicating a dot or halftone area are subjected to thinning processing and fattening processing to eliminate error judgement, an error judgement portion can be eliminated from the area signal, and image area separation can be performed with high precision.

Since a signal used in character/image area separation is the Min(R,G,B) signal, three colors, i.e., R, G, and B information, can be effectively used as compared to a case wherein a luminance signal Y is used. In particular, character/image separation in a yellowish image can be performed with high precision.

Since the edge-emphasized Min(R,G,B) signal is subjected to character/image area separation, a character portion can be easily detected, and error judgement can be easily prevented.

Outline Regeneration Unit

The outline regeneration unit 133 I executes processing for converting a pixel which is not judged as a character outline portion into a character outline portion based on information of surrounding pixels, and sends a resultant MjAr 124 to the character/image correction circuit E to execute processing, as will be described later.

More specifically, as shown in FIGS. 16A to 16 E, as for a thick character (FIG. 16 A), a dotted line portion in FIG. 16B is judged as a character portion, and is subjected to processing to be described later. As for a thin character (FIG. 16 C), however, a character portion is judged like a dotted line portion in FIG. 16D , and gaps are formed in the character portion, as indicated by hatching in FIG. 16 D. Therefore, if such a character is subjected to the processing to be described later, error judgement occurs, and the obtained character is not easy to read. In order to prevent this, outline regeneration processing for converting a portion which is not determined as a character into a character portion based on surrounding information is performed. More specifically, hatched portions are determined as character portions, so that the character portions can be-regenerated, as shown in FIG. 16 E. As a result, error judgement can be eliminated for characters in colors which are not easy to detect or for thin characters, and image quality can be improved.

FIGS. 17A to 17 H show how to regenerate an objective pixel in a character portion using surrounding information. In FIGS. 17A to 17 D, an objective pixel is determined as a character portion regardless of its information when two pixels vertically, horizontally, or obliquely adjacent to an objective pixel in a 3×3 pixel block are character portions (both S 1 and S 2 =“1”). In FIGS. 17E to 17 H, an objective pixel is determined as a character portion regardless of its information when two pixels adjacent to those horizontally, vertically, or obliquely adjacent to an objective pixel in a 5×5 pixel block are character portions (both S 1 and S 2 =“1”). In this manner, two stages (a plurality of types of blocks) of structures can overcome errors in a wide range. The size and number of pixel blocks, and types of filter can be variously modified. For example, a 7×7 pixel block may be employed.

FIGS. 18 and 19 show the outline regeneration unit for realizing the processing shown in FIGS. 17A to 17 H. The circuit shown in FIGS. 18 and 19 comprises line memories 164 i to 167 i , DF/Fs 104 i to 126 i for obtaining information around an objective pixel, AND gates 146 i to 153 i for realizing FIGS. 17A to 17 H, and an OR gate 154 i.

The four line memories and the 23 DF/Fs extract information of the pixels S 1 and S 2 in FIGS. 17A to 17 H. The AND gates 146 i to 153 i can be independently enabled/disabled by registers 155 i to 162 i corresponding to operations of FIGS. 17A to 17 H. Note that signals of the registers are controlled by the CPU 20 .

The correspondences between the AND gates 146 i to 153 i and FIGS. 17A to 17 H are as follows:

FIG. 20 shows a timing chart of a signal {overscore (WE)} (EN 1 ) and a signal {overscore (RE)} (EN 2 ) of the line memories 164 i to 167 i . The signals EN 1 and EN 2 are generated at the same timing in an equi-magnification mode, and the signal {overscore (WE)} is written once per two thinned lines in an enlargement mode (e.g., 200% to 300%). A thinning amount can be arbitrarily determined. Thus, the sizes of FIGS. 17A to 17 H can be expanded. In the enlargement mode, information is input to the line memories as an image enlarged in only the sub scan direction. Thus, the sizes of FIGS. 17A to 17 H are expanded, so that processing can be executed using an equi-magnification image even in the enlargement mode.

FIGS. 17I to 17 N are views for explaining this in more detail. FIG. 17I shows a shape of an outline regeneration filter of a 3×3 pixel block-in an equi-magnification mode. When A=B=1 or C=D=1 or E=F=1, an objective pixel is forcibly set to be 1, i.e., a character outline.

FIG. 17J shows a.shape of an 200% outline regeneration filter, and corresponds to a 3×3 pixel block in the egui-magnification mode. This block is generated as described above. A to F respectively correspond to A′ to F′. That is, A′ to F′ are set every other lines in the sub scan direction, so that character/image areas can be separated under the same condition as in the equi-magnification mode even in a zoom mode.

FIGS. 17H to 17 N show practical applications. Assume that FIG. 17M shows an input of the outline regeneration unit in the equi-magnification mode, and FIG. 17N shows an input in a 200% mode. When FIG. 17I is applied to FIG. 17M , since E=F=1, {circle around ( 1 )} can become “1”, and an outline shown in FIG. 17K can be obtained. On the other hand, when FIG. 17J is applied to FIG. 17N , since E′=F′=1, {circle around ( 1 )}′ and {circle around (1)}″ become “1”, and an outline shown in FIG. 17L is obtained. In the enlargement mode, an outline regeneration block is formed using thinned data to execute regeneration processing, so that outline regeneration having the same detection power can be performed in both the 200% enlargement mode and the equi-magnification mode.

In this embodiment, 200% enlargement has been exemplified. The same processing can be executed when a magnification is changed.

Character/Image Correction Circuit

The character/image correction circuit E executes the following processing for a black character, a color character, a dot-image, and a halftone image on the basis of the judgement signal generated by the character/image area separation circuit I.

[Processing 1] Processing for Black Character

[1-1] The signal BkMj 112 obtained by black extraction is used as a video signal.

[1-2] Y, M, and C data are subjected to subtraction according to the multi-value achromatic signal GR 125 or a setup value. Bk data is subjected to addition according to the multi-value achromatic signal GR 125 or a setup value.

[1-3] Edge emphasis is executed.

[1-4] A black character is printed at a high resolution of 400 lines (400 dpi).

[1-5] Color residual removal processing (to be described later) is executed.

[Processing 2] Processing for Color Character

[2-1] Edge emphasis is executed.

[2-2] A color character is printed at a high resolution of 400 lines (400 dpi).

[Processing 3] Processing for Dot Image

[3-1] Smoothing (two pixels in the main scan direction in this embodiment) is executed to take a moire countermeasure.

[Processing 4] Processing for Halftone Image

[4-1] Selection of smoothing (two pixels each in the main scan direction) or through processing can be enabled.

A circuit for executing the above processing operations will be described below.

FIG. 21 is a block diagram of the character/image correction unit E.

The circuit shown in FIG. 21 comprises a selector 6 e for selecting a video input signal 111 or BkMj 112 , an AND gate 6 e ′ for generating a signal for controlling the selector, a block 16 e for performing color residual removal processing (to be described later), an AND gate 16 e ′ for generating an enable signal of the removal processing, a multiplier 9 e ′ for multiplying the signal GR 125 and a setup value 10 e of an I/O port, a selector 11 e for selecting a product 10 e ′ or a setup value 7 e of an I/O port in accordance with an output 12 e of an I/O port 3 , a multiplier 15 e for multiplying an output 13 e from the selector 6 e with an output 14 e from the selector 6 e , an XOR gate 20 e for logically XORing a product 18 e and an output 9 e from an I/O port 4 , an AND gate 22 e , an adder/subtracter 24 e , line memories 26 e and 28 e for delaying one-line data, an edge emphasis block 30 e , a smoothing block 31 e , a selector 33 e for selecting through data or smoothing data, a delay circuit 32 e for performing synchronization of a control signal SCRN 127 of the selector 33 e , a selector 42 e for selecting an edge-emphasis or smoothing result, a delay circuit 36 e for performing synchronization of a control signal MjAr 124 of the selector 42 e , an OR gate 39 e for logically ORing an output 37 e from the delay circuit 36 e and an output from an I/O port 8 , an AND gate 41 e , an inverter circuit 44 e for outputting a high-resolution 400-line (dpi) signal (“L” output) to a character judgement unit, an AND gate 46 e , an OR gate 48 e , and a delay circuit 43 e for performing synchronization between a video output 113 and a signal LCHG 49 e . The character/image correction unit E is connected to the CPU bus 22 through an I/O port le.

Three sections, i.e., [1] a-section for performing color residual removal processing for removing a color signal remaining around an edge of a black character portion, and performing subtraction of Y, M, and C data of a black character judged portion at a predetermined ratio, and addition of Bk data at a predetermined ratio, [2] a section for selecting edge emphasis for a character portion, smoothing for a dot judged portion, and through data for other halftone images, and [3] a section for setting the signal LCHG at “L” level (for performing printing at a high resolution of 400 dpi) will be described below.

[1] Color Residual Removal Processing and Addition/Subtraction Processing

In this section, processing for a portion where both the signal GRBi 126 as an achromatic color and the signal MjAr 124 as a character portion are active, i.e., for a black character edge portion and its surrounding portion, that is, removal of Y, M, and C components falling outside the black character edge portion and black addition of an edge portion are executed.

A detailed operation will be described below.

This processing is executed only when a character portion is judged (MjAr 124 =“1”), a black character is determined (GRBi 126 =“1”), and a printing mode is a color mode (DHi 122 =“0”). Therefore, this processing is not executed in an ND (black and white) mode (DHi=“1”) or for a color character (GRBi=“0”).

In an original scan mode of one of Y, M, and C data of recording colors, the video input 111 is selected by the selector 6 e shown in FIG. 21 (“0” is set in an I/O- 6 ( 5 e )). The components 15 e , 20 e , 22 e , and 17 e generate data to be subtracted from video data 8 e.

For example, if “0” is set in the I/O- 3 12 e , the output data 13 e from the selector 6 e is multiplied with a value set in the I/O- 7 17 e and selected by the selector 11 e by the multiplier 15 e . In this case, the data 18 e 0 to 1 times the data 13 e is generated. when “1” is set in registers 9 e and 25 e , data of complementary number of 2 of the data 18 e are generated by the components 17 e , 20 e , and 22 e . Finally, data 8 e and 23 e are added by the adder/subtracter 24 e . In this case, however, since the data 23 e is-a complementary number of 2, subtraction of 17 e − 8 e is actually performed, and a difference is output as 25 e′.

When “1” is set in the I/O- 3 12 e , the selector 11 e selects B data.

In this case, a product obtained by multiplying the multi-value achromatic signal GR 125 (which has a larger value when it is closer to an achromatic color) generated by the character/image area separation circuit I with a value set in the I/O- 2 10 e by the multiplier 9 e is used as a multiplicator of the data 13 e . When this mode is used, coefficients can be independently changed in units of colors Y, M, and C, and a subtraction amount can be changed according to achromaticity.

When a recording color Bk is scanned, the selector 6 e selects the signal BkMj 112 (“1” is set in the I/O- 6 5 e ). The components 15 e , 20 e , 22 e , and 17 e generate data to be added to the video data 8 e . A difference from the Y, M, or C scan mode is that “0” is set in the 1 / 0 - 4 9 e . Thus, since 23 e = 8 e and Ci=0, 17 e + 8 e can be output as 25 e ′. The coefficient 14 e is generated in the same manner as in the Y, M, or C scan mode. In a mode wherein “1” is set in the I/O- 3 12 e , a coefficient is changed according to achromaticity. More specifically, when the achromaticity is large, an addition amount becomes large; otherwise, it becomes small.

FIGS. 22A to 22 D illustrate this addition/subtraction processing. Of FIGS. 22A to 22 D, FIGS. 22A and 22C show an enlarged hatched portion of a black character N. For video data Y, M, or C, a portion where a character signal portion is “1” is subtracted from the video data (FIG. 22 B), and for video data Bk, a portion where a character signal portion is “1” is added to the video signal portion (FIG. 22 D). In FIGS. 22A to 22 D, 13 e = 18 e , i.e., Y, M, or C data of a character portion is “0”, and Bk data is twice the video data.

With this processing, an outline portion of a black character is printed in an almost single black color. Portions indicated by marks “*” in FIG. 22B of Y, M, or C data falling outside an outline signal remain as residual color portions around a character, and present poor appearance.

In color residual removal processing, the residual color portions are removed. In this processing, for a portion which falls within a range of an expanded area of a character portion, and where the video data 13 e is smaller than a value to be compared set by the CPU 20 , i.e., a pixel having a possibility of a color residue outside a character portion, a minimum value of three or five pixels around the pixel is calculated.

This processing will be described below using the following circuit.

FIG. 23 shows a character area expansion circuit for expanding an area of a character portion, and comprises DF/Fs 65 e to 68 e , AND gates 69 e , 71 e , 73 e , and 75 e , and an OR gate 77 e.

When “1” is set in all I/O ports 70 e , 72 e , 74 e , and 76 e , a signal expanded by two pixels on both sides in the main scan direction is output as Sig 2 18 e if the signal MjAr 124 =“1”. When “0” is set in the I/O ports 70 e and 75 e and “1” is set in the I/O ports 71 e and 73 e , a signal expanded by one pixel on both sides in the main scan direction is output as Sig 2 18 e . This switching signal is input to the AND gate 16 e , shown in FIG. 21 .

The color residual removal circuit 16 e will be described below.

FIG. 24 is a circuit diagram of the color residual removal processing circuit.

The circuit shown in FIG. 24 comprises a 3-pixel min select circuit 57 e for selecting a minimum value of a total of three pixels, i.e., an objective pixel and two adjacent pixels from the input signal 13 e , a 5-pixel min select circuit 58 e for selecting a minimum value of a total of five pixels, i.e., an objective pixel and two pixels on both sides of the objective pixel from the input signal 13 e , a comparator 55 e for comparing the input signal 13 e and an 1 / 0 - 18 ( 54 e ), and outputting “1” when the I/O- 18 54 e is larger than the signal 13 e , selectors 61 e and 62 e , OR gates 53 e and 53 e ′, and a NAND gate 63 e.

In this arrangement, the selector 60 e selects the 3- or 5-pixel minimum value in accordance with the value of an I/O- 19 from the CPU bus 22 . The 5-pixel minimum value can enhance a color residual removal effect. The minimum values can be selected in manual selection by an operator or in automatic selection by the CPU. The number of pixels for which the minimum value is to be calculated can be arbitrarily set.

The selector 62 e selects an A input when the output from the NAND gate 63 e is “0”, i.e., when the comparator 55 e determines that the video data 13 e is smaller than the register value 54 e and an input 17 e ′ is “1”; otherwise, it selects a B input (in this case, registers 52 e and 64 e are “1”, and a register 52 e ′ is “0”).

When the B input is selected, through data is output as the data 8 e.

An EXCON 50 e can be used in place of the comparator 55 e when a signal obtained by binarizing a luminance signal is input.

When the above-mentioned color residual removal processing is executed, color misregistration around a character can be removed, and a clearer image can be obtained.

FIGS. 25A to 25 F show a portion subjected to the above-mentioned two processing operations. FIG. 25A shows a black character N, and FIG. 25B shows an area which is judged as a character in Y, M, or C data as density data. That is, character judged portions (* 2 , * 3 , * 6 , and * 7 ) become “0” by subtraction processing, and portions * 1 and * 4 are respectively set to be * 1 ←* 0 and * 4 ←* 5 by the color residual removal processing, i.e., consequently become “0”, thus obtaining a portion illustrated in FIG. 25 C.

For Bk data shown in FIG. 25D , only addition processing is performed for character judged portions (* 8 , * 9 , * 10 , and * 11 ), thereby obtaining an output with a clear black outline.

For a color character, no modification is made, as shown in FIG. 25 F.

[2] Edge Emphasis or Smoothing Processing

In this section, processing for executing edge emphasis for a character judged portion, smoothing processing for a dot portion, and outputting through data for other portions is executed.

Character portion→Since MjAr 124 =“1”, a selector 42 e selects an output of an edge emphasis circuit 30 e , which is generated. based on signals on three lines 25 e , 27 e , and 29 e , and outputs the selected output. Note that edge emphasis is executed based on a matrix and a formula shown in FIG. 26 .

Dot portion→Since SCRN 35 e =“1” and MjAr 21 e =“0”, a signal 27 e is subjected to smoothing by a smoothing circuit 31 e , and the smoothed signal is selected by and output from a selector 33 e and the selector 42 e . Note that smoothing is processing for, when an objective pixel is V N , as shown in FIG. 27 , determining (V N +V N+1 )/2 as data of V N , i.e., smoothing of main scan two pixels. Thus, moire noise which may be generated in a dot portion can be prevented.

Other portions→Other portions mean portions which are neither a character portion (character outline) nor a dot portion, i.e., halftone portions. In this case, since both MjAr 124 and SCRN 35 e =“0”, the data 27 e is directly output as the video output 113 .

When a character is a color character, the above-mentioned two processing operations are not performed even for a character judged portion.

In this embodiment, the color residual removal processing is executed in only the main scan direction. However, this processing may be executed in both the main and sub scan directions.

The types of edge emphasis filters are not limited to those described above.

Smoothing processing may also be executed in both the main and sub scan directions.

[3] Processing for Outputting Character Portion at High Resolution of 400 Lines (dpi)

A signal LCHG is output from a gate 48 e in synchronism with the video output 113 . More specifically, an inverted signal of the signal MjAr 124 is output in synchronism with a signal 43 e . For a character portion, LCHG (200/400 switching signal)=0, and for other portions, LCHG=“1”.

A character judged portion, more specifically, a character outline portion is printed by a laser beam printer at a high resolution of 400 lines (dpi), and other portions are printed with multigradation of 200 lines.

FIG. 25G shows a soft key screen of a liquid crystal touch panel 1109 of the operation unit 1000 for changing conditions of character/image separation processing. In this embodiment, five conditions can be selected by a soft key. The soft key has positions “low”, “−2”, “−1”, “normal”, and “high” from the left-hand side of FIG. 25 G. These positions will be described in detail below.

[Low]

The position “low” is used to avoid error judgement which inevitably occurs when an original from which line images and the like cannot be discriminated is copied. At this position, a limiter value of the limiter 1231 shown in FIG. 15A is set to be an appropriate value.

As shown in FIG. 25H , at the position “normal”, a limiter level is present in a bright portion of an original (limiter value=158 in this embodiment). An output exceeding this limiter value is clipped to the limiter value, as shown in FIG. 25 I. When the position “low” is selected, the limiter level is set to be “0”, as shown in FIG. 25J , and all the outputs are clipped to “0” (FIG. 25 K). For this reason, an output binarized by the comparator 3 ( 126 I) shown in FIG. 15A is all “1”s (or all “0”s), and no outline is extracted. As a result, no black character processing described above is executed for the read image signal. In this manner, the position “low” can prevent generation of an outline signal, thereby preventing processing of a portion subjected to image area separation.

[−2] [−1]

At the positions “−2” and “−1”, error judgement of an original including both characters and images is made inconspicuous. In a normal original copying mode, the resolution switching signal LCHG is controlled so that an outline portion of a black character of a character portion is printed in single black color at a high resolution. At the positions “−2” and “−1”, the resolution switching signal is controlled in the same manner as for all other image portions, a black character is not printed in single black color, and a ratio of Y, M, and C data is increased as the value of the position is decreased like “−1” and “−2”. Thus, control is made to decrease an image difference of processed images according to a judgement result.

This will be described below with reference to FIGS. 25L to 25 P. FIG. 25L shows read image data which becomes dark as a value is increased, and becomes light as a value is decreased. In image area separation of this embodiment, processing is performed for two pixels of an outline portion, as shown in FIG. 25 L. When a soft lever displayed on the touch panel is at the positions [normal] and [high], a ratio of an outline portion is increased, so that for Y, M, and C data, a Y, M, or C toner is not printed on two pixels of the outline portion of a black character and a line, as shown in FIG. 25H , and for Bk data, a black line or character can look sharp, as shown in FIG. 25 N. In the [−1] and [−2] modes, toners of Y, M, and C data can be slightly left on an outline portion, as shown in FIG. 25O , and a toner of Bk data is decreased, as shown in FIG. 25 P.

[Normal]

At the position “normal”, the above-mentioned rocessing is executed.

[High]

At the position “high”, parameters are set so that no error judgement occurs for a character, and a thin or light character is printed in single black color. More specifically, when the limiter value of the limiter 3 ( 123 I in FIG. 15A ) of the outline signal is increased, an outline signal of a highlight portion can be extracted.

In this manner, image area separation conditions and processing based on separation are changed according to an image to be read, so that error judgement can be avoided or made inconspicuous.

Since the limiter value can be easily changed by the CPU 20 , a circuit arrangement will not be complicated.

The number of levels of black character processing need not always be five. When the number of levels is increased, processing matching with an original image can be selected.

Relationship With Mode Selection

Processing according to selection of an output color mode such as a four-color mode, a thlree-color mode, a single-color mode, or the like will be described below.

A digital copying machine has a function of copying an image in a color different from an original color, e.g., a function of-copying a full-color original in monocolor. In a portion subjected to image area separation described above, a color balance is changed to meet a requirement of a clear character. For this reason, when the above-mentioned processing is performed for an input image after an image area is separated, an output image is considerably degraded.

In this embodiment, in order to provide an image processing apparatus which is free from image degradation caused by a difference in output color mode, conditions of the image area judgement means or processing means according to judgement are changed according to an output color mode.

When a monochromatic signal described in the masking unit is selected, or when a three-color mode for forming an image using only Y, M, and C toners is selected, input image processing by the image area separation processing of this embodiment is not performed.

More specifically, processing is performed as follows.

As shown in FIG. 25H , in a four-color mode for recording an image in four colors, e.g., Y. M, C, and Bk, a limiter level is present in a bright portion of an original (limiter value=158 in this embodiment). An output exceeding this limiter value is clipped to the limiter value, as shown in FIG. 25 I. In the three-color mode for recording an image in three colors, i.e., Y, M, and C, when the limiter level is set to be 0, as shown in FIG. 25J , all the output signals are clipped to 0. For this reason, an output binarized by the comparator 3 ( 126 I) in FIG. 15A becomes all “1”s (or all “0”s), no outline is extracted, and no processing is executed to a read image signal. In this manner, in the three-color mode, generation of an outline signal is prevented, so that processing of a portion where an image area is separated is inhibited.

In the single-color mode, processing for extracting a character signal is inhibited as in the three-color mode.

In this embodiment, a color copying machine which has a judgement means for judging based on input image information whether the input image information is image or character information, and a processing means for processing the input information in accordance with the judgement result, has a color mode different from a normal copying mode, and varies the processing according to the judgement result in the color mode different from the normal copying mode. Thus, processing can be simplified, and error judgement can be prevented.

Relationship Between Lamp Light Amount and Control

A digital color copying machine is required to have background color omission processing as performed in a conventional analog copying machine. A system of omitting a background color of a newspaper by changing a lamp light amount is proposed.

When the light amount of a light source is changed, however, the level of light reflected by an original also changes, and error judgement tends to occur in a separation system which judges characters or images according to a contrast or color of a read image signal.

In this embodiment, the character/image judgement conditions are changed according to an original read light amount, thereby eliminating error judgement in character/image judgement caused by a change in light amount.

Lamp light amount adjustment will be described below. FIG. 25Q shows the flow of lamp light amount adjustment. In a prescan mode of detecting a position, size, and the like of an original, data of 50 points in the main scan direction and 30 lines at equal intervals in the sub scan direction, i.e., data of a total of 1,500 points are read, and the number of data of an original is counted (S 1 ). A maximum value-of the data is detected (S 2 ), and the number of data points having values within 85% to 100% of the maximum value is counted (S 3 ). In this case, only when the maximum value is equal to or larger than 60 H (S 4 ) and ¼ of the total points have values 85% to 100% of the maximum value (S 5 ), is light amount adjustment performed (S 7 ). A light amount is set so that the maximum value becomes FF H : $$ ( Light ⁢   ⁢ Amount ⁢   ⁢ Set ⁢   ⁢ Value ) = FF H ( Maximum ⁢   ⁢ Value ) × ( Default ⁢   ⁢ Light ⁢   ⁢ Amount ⁢   ⁢ Set ⁢   ⁢ Value )

The value obtained by the above equation is set as a lamp light amount set value (S 6 ).

When the maximum value of data is less than 60 H, or when less than ¼ of the total points have values 85% to 100% of the maximum value, lamp light amount adjustment is not performed.

When the light amount adjustment is performed, values larger than the normal one are set in the offset register 2 ( 119 I) and the offset register 3 ( 124 I). When the lamp light amount is increased, the dynamic range of a read original density is narrowed. Thus, a noise component of an original is undesirably detected, error judgement in dot detection and error detection in outline extraction occur. In order to prevent error detection caused by the noise component, the offset values are increased only when the light amount adjustment is performed.

In this manner, according to this embodiment, in a copying machine having an original reading means for reading an image by optical scanning, a light amount adjusting means for adjusting a light amount of a read light source in correspondence with a density of an original to be read, a judgement means for judging that the read image information is halftone or character information, and a processing means for processing the input information on the basis of the judgement result, the judgement condition is changed when the light amount adjustment is performed.

In this embodiment, lamp light amount control is performed under a given condition. However, lamp light amount control may be executed in all the cases.

Sampling data in a prescan mode can be increased/decreased. A threshold value for determining whether or not light amount adjustment is to be executed can be changed.

A condition for judging character and image areas may be selected from a plurality of stages according to light amount adjustment.

Character/Image Synthesizing Circuit

The character/image synthesizing circuit F will be described below. FIG. 28A is a block diagram of a process and modulation circuit of a binary image signal. Color image data 138 input from an image data input unit is input to a V input of a 3 to 1 selector 45 f . An A input of the 3 to 1 selector 45 f receives a A n of a lower-bit portion (A n , B n ) 555 f read out from a memory 43 f , and a B input thereof receives B n after the lower-bit portion 555 f is latched by a latch 44 f in response to a signal VCLK 117 . Therefore, one of the V, A, and B inputs appears at an output Y of the selector 45 f on the basis of select inputs X 0 , X 1 , J 1 , and J 2 ( 114 ). Data X n consists of upper 2 bits of data in the memory, and serves as a mode signal for determining a process or modulation mode. A signal 139 is a code signal output from the area signal generation circuit, is switched in synchronism with the signal VCLK 117 under the control of the CPU 20 shown in FIG. 2 , and is input to the memory 43 f as an address signal. More specifically, when (X 10 , A 10 , B 10 )=(0.1, A 10 , B 10 ) is written in advance at an address “10” of the memory 43 f , if “10” is given between points P and Q of the code signal 139 and “0” is given between points Q and R in synchronism with scanning of a main scanning line 1 , data X n =(0, 1) is read out between P and Q, and at the same time, data (A 10 , B 10 ) is latched in (A n , B n ) FIG. 28C shows a truth table of the 3 to 1 selector 45 f . As shown in FIG. 28C , (X 1 , X 0 )=(0, 1) corresponds to a case (B). If J 1 =“1”, the A input is output to the Y output, and, hence, the constant A 10 appears at the Y output. On the other hand, if J 1 =“0”, the V input is output to the Y output, and hence, input color image data is directly output as the output 114 . In this manner, so-called butt-to-line character synthesis of a character portion having a value (A 10 ) to a color image of an apple shown in, e.g., FIG. 29B can be realized. Similarly, when (X 1 , X 0 )=(1, 0) and a signal J 1 in FIG. 29C is input to a binary input, FIFO memories 47 f to 49 f and a circuit 46 f (shown in detail in FIG. 28B ) generate a signal J 2 in FIG. 29 C. As a result, a character with a frame is output to an image of an apple, as shown in FIG. 29C , according to the truth table of FIG. 28C (outline or open type). Similarly, in FIG. 29D , a rectangular area in an apple is output at a density of (B n ), and a character in the image of the apple is output at a density of (A n ). FIG. 29A shows a case of (X 1 , X 0 )=(0, 0), i.e., no processing is performed for a binary signal regardless of changes in J 1 and J 2 .

A signal having an expanded width input to the input J 2 undergoes expansion corresponding to 3×3 pixels according to FIG. 28 B. When a hardware circuit is added, the signal can be easily expanded more.

An FHi signal 121 input to the FIFO memory 47 f is a non-rectangular area signal stored in the 100-dpi binary memory L shown in FIG. 2 . When this FHi signal 121 is used, the above-mentioned various processing modes are realized.

The outputs C 0 and C 1 ( 366 , 367 ) output from the I/O port 501 ( FIG. 2 ) in correspondence with an output color to be printed (Y, M, C, Bk) are input to the lower 2 bits of the address of the memory 43 f , and hence, are changed like “0, 0”, “0, 1”, “1, 0”, and “1, 1” in correspondence with outputs Y, M, C, and Bk. Therefore, in, e.g., a yellow (Y) output mode, addresses “0”, “4”, “8”, “12”, “16”, . . . , are selected; in a magenta (M) output mode, addresses “1”, “5”, “9”, “13”, “17”, . . . , are selected; in a cyan (C) output mode, addresses “2”, “6”, “10”, “14”, “18”, . . . , are selected; and in a black (Bk) output mode, “3”, “7”, “11”, “15”, “19”, . . . , are selected. Thus, upon operation instructions on the operation panel (to be described later), for example, X 1 to X 4 =“1, 1” (A 1 , A 2 , A 3 , A 4 )=(α 1 , α 2 , α 3 , α 4 ) and (B 1 , B 2 , B 3 , B 4 )=(β 1 , β 2 , β 3 , β 4 ) are written at addresses corresponding to the area code signal 139 for determining an area and corresponding memory addresses in the area. For example, if the signal J 1 is changed, as shown in FIG. 29D , a color is determined by a mixture of (Y, N, C, Bk)=(α 1 , α 2 , α 3 , α 4 ) during a “Lo” period of J 1 , and a color is determined by a mixture of (Y, M, C, Bk)=(β 1 , β 2 , β 3 , β 4 ) during a “Hi” period of J 1 . More specifically, an output color can be arbitrarily determined by the memory content. On the operation panel (to be described later), each of Y, M, C, and Bk is adjusted or set in units of %. Since each gradation level has 8 bits, its value can be varied within a range of 00 to 255. Therefore, a variation of 1% corresponds to 2.55 in digital value. If set values are (Y, M, C, Bk)=(y%, m%, c%, k%), values to be set (i.e., values written in the memory) are respectively (2.55y, 2.55m, 2.55c, 2.55k). In practice, rounded values are written in the predetermined memory. When densities are adjusted in units of % by an adjustment mechanism, values obtained by adding (darkening) or subtracting (lightening) 2.55Δ with respect to a variation of Δ% can be written in the memory.

In this manner, according to this embodiment, output colors Y, M, C, and Bk can be designated in units of %, and operability of color designation can be improved.

In the truth table of FIG. 28C , a column of i corresponds to an I/O table of the character/image gradation/resolution switching signal LCHG 149 . When the A or B input is output to the output Y according to the inputs X 1 , X 0 , J 1 , and J 2 , i=“0”; when the input V is output to the output Y, the input is directly output. The signal LCHG 149 is a signal for switching an output printing density. When LCHG=“0”, printing is made at, e.g., a high resolution of 400 dpi; when LCHG=“1”, printing is performed with multigradation of 200 dpi. Therefore, if LCHG=“0” when-the input A or B is selected, an inner area of a synthesized character is printed at 400 dpi, and an area other than the character is printed at 200 dpi. As a result, the character can be output sharply at a high resolution, and a halftone portion can be smoothly output with multigradation. For this purpose, the signal LCHG 149 is output from the character/image correction circuit E on the basis of the signal MjAr as the output from the character/image area separation circuit I, as described above.

Image Process and Edit Circuit

An image signal 115 subjected to color balance adjustment in the circuit P ( FIG. 2 ) and a gradation/resolution switching signal 141 are input to the image process and edit circuit G. FIG. 30 is a schematic view-of the image process and edit circuit G.

The input image signal 115 and gradation/resolution switching signal LCHG 141 are input to a texture processing unit 101 g . The texture processing unit can be roughly constituted by a texture memory 103 g for storing a texture pattern, a memory RD,WR address control unit 104 g for controlling the memory 103 g , and a calculation circuit 105 g for performing modulation processing of input image data on the basis of the stored pattern. Image data processed by the texture processing unit 101 g is then input to a zoom, mosaic, taper processing unit 102 g . The zoom, mosaic, taper processing unit comprises double buffer memories 105 g and 106 g , and a processing/control unit 107 g , and various processing operations are independently controlled by the CPU 20 . The texture processing unit 101 g , and the zoom, mosaic, taper processing unit 102 can perform texture processing and mosaic processing of independent areas in accordance with processing enable signals GHi 1 ( 119 ) and GHi 2 ( 149 ) sent from the switch circuit N.

The gradation/resolution switching signal LCHG 141 input together with the image data 115 is processed while its phase is matched with an image signal in various edit processing operations. The image process and edit circuit G will be described in detail below.

Texture Processing Unit

In the texture processing, a pattern written in the memory is cyclically read out to modulate video data. For example, the image shown in FIG. 31A is modulated by a pattern shown in FIG. 31B , thereby generating an output image, as shown in FIG. 31 C.

FIG. 32 is a circuit diagram for explaining the texture processing unit. A write section of modulation data 218 g of the texture memory 113 g and a calculation section (texture processing) of data 216 g from the texture memory 113 g and image data 215 g will be described below in turn.

[Data Write Section of Texture Memory 113 g]

In a data write mode, the color correction circuit D for performing masking, UCR, black extraction, and the like outputs (Y+M+C)/3, and the data is input from a video input 201 g . This data is selected by a selector 202 g . A selector 208 g selects data 220 g , and inputs the selected data to a terminal {overscore (WE)} of the memory 113 g and an enable signal terminal of a driver 203 g . A memory address is generated by a vertical counter 212 g which is incremented in synchronism with a horizontal sync signal HSYNC, and a horizontal counter 211 g which is incremented in synchronism with an image clock VCK. When a selector 210 g selects its B input, the address is input to an address terminal of the memory 113 g . In this manner, a density pattern of an input image is written in the memory 113 g . As this pattern, a position on an original is designated by an input device, e.g., a digitizer 58 , and image data obtained by reading the designated portion is written in the memory 113 g.

[Data Write Access by CPU]

CPU data is selected by the selector 202 g . On the other hand, the selector 208 g selects its A input, and the selected input is input to the terminal {overscore (WE)} of the memory 113 g and the enable signal terminal of the driver 203 g . The memory address is input to the address terminal of the memory 113 g when the selector 210 g selects its A input. In this manner,-an arbitrary density pattern is written in the memory.

[Calculation Section of Data 216 g of Texture Memory 113 g and Image Data 215 g]

This calculation is realized by a calculator 215 g . In this embodiment, the calculator comprises a multiplier. Only when an enable signal 128 g is enabled, a calculation of the data 216 g and 201 g is executed; when it is disabled, the input 201 g goes through the calculator.

300 g and 301 g respectively designate XOR and OR gates. When “1” and “0” are respectively set in registers 304 g and 305 g as portions for generating an enable signal using an MJ signal 308 g , i.e., a character synthesizing signal, texture processing is performed for a portion excluding a character synthesizing signal. On the other hand, when “0” and “0” are respectively set in the registers 304 g and 305 g , the texture processing is performed for a portion including the character synthesizing signal.

A gate 302 g serves to generate an enable signal using a GHi 1 signal 307 g , i.e., a non-rectangular area signal. When “0” is set in the register 306 g , the texture processing is performed for only a portion where the GHi 1 signal is enabled. In this case, if the enable signal 128 is kept enabled, non-rectangular texture processing is performed regardless-of a non-rectangular area signal, i.e., in synchronism with HSYNC. If the signal GHi 1 and the enable signal 128 are synchronized, texture-processing synchronous with a non-rectangular area signal is executed. If a 31b-bit signal is used as the signal GHi 1 , texture processing can be executed for only a specific color.

The LCGH IN signal 141 g is a gradation/resolution switching signal, is delayed by the calculator 215 g , and is output as a signal LCHG OUT 350 g . In this manner, in the texture processing unit, the gradation/resolution switching signal LCHG 141 is also subjected to predetermined delay processing in correspondence with an image subjected to the texture processing.

Mosaic, Zoom, Taper Processing Unit

The operation of the mosaic, zoom, taper processing unit 102 g of the image process and edit circuit G will be briefly described below with reference to FIG. 33 .

The image data 126 g and the LCHG signal 350 g input to the mosaic, zoom, taper processing unit 102 g is first input to a mosaic processing unit 401 g . In the mosaic processing unit 401 g , the input data are subjected to determination of the presence/absence of mosaic processing and the main scan size of a mosaic pattern, synthesis of a character, and the like in accordance with the Mj signal 145 output from the character synthesizing circuit F, the area signal GHi 2 ( 149 ) output from the switch circuit N, and a mosaic clock MCLK from a mosaic processing control unit 402 g . Thereafter, the processed data are input to a 1 to 2 selector 403 g . The area signal GHi 2 is generated on the basis of non-rectangular area information stored in the binary memory L (FIG. 2 ). In response to this signal, mosaic processing of a non-rectangular area is allowed. Note that the main scan size of the mosaic processing can be varied by controlling the mosaic clock MCLK. Control of the mosaic clock MCLK will be described in detail later.

The 1 to 2 selector 403 g outputs the input image signal and the LCHG signal to one of terminals Y 1 and Y 2 in accordance with a line memory select signal LMSEL obtained by frequency-dividing a signal HSYNC 118 by a D flip-flop 406 g.

The outputs from the terminal Y 1 of the 1 to 2 selector 403 g are connected to a line memory A 404 g and an A input of a 2 to 1 selector 407 g . The outputs from the terminal Y 2 are connected to a line memory B 405 g and a B input of the 2 to 1 selector 407 g . When an image is sent from the selector 403 g to the line memory A, the line memory A 404 g is set in a write mode, and the line memory B 405 g is set in a read mode. Similarly, when an image is sent from the selector 403 g to the line memory B 405 g , the line memory-B is set in the write mode, and the line memory A 404 g is set in the read mode. In this manner, image data alternately read out from the line memories A 404 g and B 405 g are output as continuous image data while being switched by the 2 to 1 selector 207 g in response to an inverted signal of the LISEL signal output from the D flip-flop 406 g . The output image signal from the 2 to 1 selector 407 g is subjected to predetermined enlargement processing by an enlargement processing unit 414 g and the processed signal is then output.

Read/write control of these memories will be described below. In the write and read modes, addresses supplied to the line memories A 404 g and B 405 g are incremented/decremented by up/down counters 409 g and 410 g in synchronism with the signal HSYNC as a reference of one scan period, and an image CLK. The address counters ( 409 g and 410 g ) are controlled by a counter enable signal output from the line memory address control unit 413 g , and control signals WENB and RENB, generated from a zoom control unit 415 g , for respectively controlling write and read addresses. These controlled address signals are respectively input to the 2 to 1 selectors 407 g and 408 g . The 2 to 1 selectors 407 g and 408 g supply a read address to the line memory A 404 g and a write address to the line memory B 405 g in response to the above-mentioned line memory select signal LMSEL when the line memory A 404 g is in the read mode. When the line memory A 404 g is in the write mode, an operation opposite to that described above is executed. Memory write pulses WEA and WEB to he line memories A and B are output from the zoom control unit 415 g . The memory write pulses WEA and WEB are controlled when an input image is to be reduced and when an input image is subjected to mosaic processing by a mosaic.length control signal MOZWE in the sub scan direction, which is output from the mosaic processing control unit 402 g . A detailed description of these operations will be made below.

Mosaic Processing

Mosaic processing is basically realized by repetitively outputting one image data. The mosaic processing operation will be described below with reference to FIG. 34 .

The mosaic processing control unit 402 g independently performs main and sub scan mosaic processing operations. The CPU sets variables corresponding to a desired mosaic size in latches 501 g (main scan) and 502 g (sub scan) connected to the CPU bus. The main scan mosaic processing is executed by continuously writing the same data at a plurality of addresses of the line memory. The sub scan mosaic processing is executed by thinning data to be written in the line memory every predetermined lines in a mosaic processing area.

(Main Scan Mosaic Processing)

A variable corresponding to a main scan mosaic width is set by the CPU in the latch 501 g . The latch 501 g is connected to a main scan mosaic width control counter 504 g , and loads a set value in response to an HSYNC signal and a ripple carry of the counter 504 g . The counter 504 g loads a value set in the latch 501 g in response to each HSYNC signal. When the counter 504 g counts a predetermined value, it outputs a ripple carry to a NOR gate 503 g and an AND gate 509 g . A mosaic clock MCLK from the AND gate 509 g is obtained by thinning the image clock CLK by the ripple carry from the counter 504 g . Only when the ripple carry is generated is the clock MCLK is output. The clock MCLK is then input to the mosaic processing unit 401 g.

The mosaic processing unit 401 g comprises two D flip-flops 510 g and 511 g , a selector 512 g , an AND gate 514 g , and an inverter 513 g . The flip-flops 510 g and 511 g are connected to the gradation/resolution switching signal LCHG in addition to an image signal, and hold the input image data and the LCHG signal in response to the image clock CLK ( 510 g ) and the mosaic processing clock MCLK ( 511 g ), respectively. More specifically, the gradation/resolution switching signal LCHG corresponding to one pixel is held in the flip-flops 510 g and 511 g in a phase-matched state during CLK and MCLK periods. The held image signal and LCHG signal are input to the 2 to 1 selector 512 g . The selector 512 g switches its output in accordance with a mosaic area signal GHi 2 , and a binary character signal MJ. The selector 512 g performs an operation shown in the truth table below using the AND gate 514 g and the inverter 513 g .

GHi2	Mj	Y
0	0	A
0	1	A
1	0	B
1	1	A

When the mosaic area signal GHi 2 149 is “0”, the selector 512 g outputs the signals from the flip-flop 510 g regardless of the Mj signal. When the GHi 2 signal 149 is “1” and the Mj signal is “0”, the selector 512 g outputs the signals from the flip-flop 511 g which is controlled by the mosaic clock MCLK. When the Mj signal is “1”, the selector 512 g outputs the signals from the flip-flop 510 g . With this control, a portion of an image subjected to main scan mosaic processing can be output without being processed. More specifically, no mosaic processing is performed for a character synthesized in an image by the character synthesizing circuit F (FIG. 2 ), and only an image can be subjected to mosaic processing. The outputs from

the selector 512 g are input to the 2 to 1 selector 403 g shown in FIG. 33 . In this manner, the main scan mosaic processing is performed.

(Sub Scan Mosaic Processing)

The sub scan mosaic processing is controlled by the latch 502 g connected to the CPU bus, a counter 505 g , and a NOR gate 503 g as in the main scan mosaic control. The sub scan mosaic width control counter 505 g generates a ripple carry pulse in synchronism with an ITOP signal 144 and by counting an HSYNC signal 118 . The ripple carry pulse is input to an OR gate 508 g together with an inverted signal {overscore (GHi 2 )} of the mosaic area signal GHi 2 149 , and the character signal Mj. The sub scan mosaic control signal MOZWE is subjected to control shown in the truth table below.

	GHi2	Mj	RC	MOZWE
	0	X	X	1
	1	0	0	0
	1	0	1	1
	1	1	X	1

The MOZWE signal output in these combinations is input to the zoom control unit 415 g , and controls a write pulse generated by a line memory write pulse generation circuit (not shown) in a NAND gate 515 g . The write pulse generation circuit can vary an output clock rate of, e.g., a rate multiplier normally used in zoom control. Since this circuit falls outside-the scope of the present invention, a detailed description thereof will be omitted in this embodiment. A WR pulse controlled by the MOZWE signal is output alternately as the pulses WEA and WEB from the 1 to 2 selector in response to the switching signal LMSEL which switches pulses in response to the HSYNC signal 118 . With the above-mentioned control, even when the mosaic area signal GHi 2 149 is “1”, if the Mj signal goes to “1” level, write access of the memory is performed. Thus, a portion of a sub-scan mosaic-processed image can be output without being processed. FIG. 35A shows a distribution of density values in units of pixels for a given recording color when mosaic processing is actually executed. In the mosaic processing shown in FIG. 35A , pixels in a 3×3 pixel block are used as typical pixel values. In this processing, a character “A”, i.e., hatched pixels in FIG. 35A are not subjected to mosaic processing based on the character signal Mj. More specifically, when a synthesized character overlaps a mosaic processing area, the character has a priority over the mosaic processing. Therefore, when the mosaic processing is performed, an image can be formed, so that a character can be read. A mosaic area is not limited to a rectangular area. For example, mosaic processing can be executed to a non-rectangular area.

(Inclination and Taper Processing)

Inclination processing will be described below with reference to FIGS. 33 and 36 .

FIG. 36 shows the internal arrangement of the line emory address control unit 413 g shown in FIG. 33 . The line memory address control unit 413 g controls enable signals of the write and read counters 409 g and 410 g . The control unit 413 g controls the counters to determine a portion of one main scan line to be written in or read out from the line memory, thereby achieving, e.g., shift and inclination of a character. An enable control signal generation circuit will be described below with reference to FIG. 36 .

A counter output of a counter 701 g is reset to “0” in response to the HSYNC signal, and the counter 701 g then counts the image clocks CLK 117 . The output Q of the counter 701 g is input to comparators 706 g , 707 g , 709 g , and 710 g . The A input sides of the comparators excluding the comparator 709 g are independent latches (not shown) connected to the CPU bus 22 . When arbitrarily set values and the output from the counter 701 g coincide with each other, these comparators output pulses. The output of the comparator 706 g is connected to the J input of the J-K flip-flop 708 g , and the output from the comparator 707 g is connected to the K input. The J-K flip-flop 708 g outputs “1” from when the comparator 706 g outputs a pulse until the comparator 707 g outputs a pulse. This output is used as a write address counter control signal, and the write address counter is enabled during only a “1” period to generate an address to the line memory. A read address counter control signal similarly controls the read address counter. The A input of the comparator 709 g is connected to a selector 703 g to vary an input value to the comparator depending on a case wherein inclination processing may or may not be performed. When the inclination processing is not performed, a value set in a latch (not shown) connected to the CPU bus 22 is input to the A input of the selector 703 g , and the A input is output from the selector 703 g in response to a select signal output from a latch (not shown). The following operations are the same as those of the comparators 706 g and 707 g . When the inclination processing is performed, a value input to the A input of the selector 703 g is also input to a selector 702 g as a preset value. When the select signals input to the selectors 702 g and 703 g select their B inputs, the output from the selector 702 g is added to a value set in a latch (not shown) by an adder 704 g . The sum represents a change amount per line based on an inclination angle, and if a required angle is represented by θ, the change amount can be given by tan θ. The sum is input to a flip-flop 705 g which receives the HSYNC signal 118 as a clock, and is held by the flip-flop 705 g for one main scan period. The output from the flip-flop 705 g is connected to the B inputs of the selectors 702 g and 703 g . When this addition is repeated, the output from the selector to the comparator 709 g changes at a predetermined rate for each scan period, so that the start of the read address counter can be varied from the HSYNC signal at a predetermined rate. Thus, data are read out from the line memories A 404 g and B 405 g at timings shifted from the HSYNC signal, thus allowing the inclination processing. The above-mentioned change amount can be either a positive or negative value. When the change amount is positive, the read timing is shifted in a direction to separate from the HSYNC signal; when it is negative, the read timing is shifted in a direction to be closer to the HSYNC signal. The select signals of the selectors 702 g and 703 g are changed in synchronism with the HSYNC signal, so that a portion of an image can be converted to an inclined character.

As an enlargement processing methods, 0th, linear, SINC interpolation methods, and the like are known. However, since this operation is not incorporated in the present invention, a detailed description thereof will be omitted. When a main scan magnification is changed in synchronism with the HSYNC signal for each scan line while the inclination processing is being executed, taper processing can be realized.

The above-mentioned processing operations can also be performed for a non-rectangular area in accordance with the non-rectangular area signal GHi as in the mosaic processing and texture processing.

In these processing operations, the input gradation/resolution switching signal is processed while its phase is matched with an image signal. More specifically, the switching signal LCHG 142 is similarly processed as an image signal is processed in the zoom, inclination, taper processing modes, and the like. The output image data 114 and the output gradation/resolution switching signal LCHG 142 are output to the edge emphasis circuit.

FIGS. 35B and 35C show the principle of the above-mentioned inclination processing and taper processing.

Outline Processing Unit

FIGS. 35D and 35F are views for explaining outline processing. In this embodiment, as shown in FIG. 35D , an inside signal of a character or image (an inner broken line in (I) of FIG. 35D , 103 Q in (II) thereof) and an outside signal (an outer broken line in (I) of FIG. 35D and 102Q in (II) thereof) are generated, and are logically ANDed, thereby extracting an outline. In the timing chart ((II) of FIG. 35 D), 101 Q designates a signal obtained by binarizing a multi-value original signal by a predetermined threshold value. The signal 101 Q represents a boundary portion between an original image (hatched portion) and a. background shown in (I) of FIG. 35 D. Contrary to this, 102 Q designates a signal obtained by expanding a “Hi” portion of the signal 101 Q to fatten a character portion (fattened signal), and 103 Q designates a signal by shrinking the “Hi” portion of the signal 101 Q to thin a character portion (thinned signal), and then inverting the obtained signal. 104 Q designates an AND product of the signals 102 Q and 103 Q, i.e., an extracted outline signal. A hatched portion of the signal 104 Q represents that a wider outline can be extracted. That is, a fattening width is further increased in the signal 102 Q, and a shrinking width is further increased in the signal 103 Q, so that an outline having a different width can be extracted. In other words, the width of the outline can be changed. FIG. 35F is a circuit diagram for realizing the outline processing described with reference to FIG. 35 D. This circuit is arranged in the image process and edit circuit G shown in FIG. 2 . Input multi-value image data 138 is compared with a predetermined threshold value 116 q by a comparator 2 q , thereby generating a binary signal 101 q . The threshold value 116 q is an output from a data selector 3 q , i.e., a signal selected by and output from the selector 3 q in correspondence with a certain color in accordance with outputs 110 q to 113 q from values r 1 , r 2 , r 3 , and r 4 set in a register group 4 q in units of printing colors, i.e., yellow, magenta, cyan, and black by the CPU (not shown). A binarization threshold value can be varied in units of colors in response to signals 114 q and 115 q which are switched in units of colors by the CPU (not shown), thereby varying a color outline effect. The data selector 3 q respectively selects the A, B, C, and D inputs when, for example, ( 114 q , 115 q )=(0, 0), (0, 1), (1, 0), and (1, 1), and these inputs respectively correspond to yellow, magenta, cyan, and black threshold values. The binary signal 101 q is stored in line buffers 5 q to 8 q for five lines, and is output to a next fattening circuit 150 q and a next thinning circuit 151 q . The circuit l 50 q generates a signal 102 q . When a total of 25 (or 9) pixels of a 5×5 (or 3×3) small pixel block include at least one “1” pixel, the circuit 150 q determines the value of a central pixel to be “1”. More specifically, for an original image (hatched portion) shown in (I) of FIG. 35D , an outside signal O of two pixels (or one pixel) is generated. Similarly, the circuit 151 q generates a signal 103 q . When a total of 25 (or 9) pixels of a 5×5 (or 3×3) small pixel block include at least one “0” pixel, the circuit 151 q determines the value of a central pixel to be “0”. That is, an inside signal I of two pixels (or one pixel) is formed for (I) of FIG. 35 D. Therefore, as has been described with reference to (II) of FIG. 35D , the signals 102 q and 103 q are logically ANDed by an AND gate 41 q , thus forming an outline signal 104 q . As can be seen from a circuit operation, signals 110 q and 111 q are select signals for selecting the 3×3 or 5×5 small pixel block. When the 3×3 pixel block is selected, ( 110 q , 111 q )=(0, 1). An outline width in this case corresponds to two pixels since a fattening width is one pixel and a thinning width is one pixel. When the 5×5 pixel block is selected, ( 110 q , 111 q )=(1, 1), and the outline width corresponds to four pixels. These selections are controlled by an I/O port connected to the CPU (not shown), so that an operator can switch the pixel block according to a required effect.

In FIG. 35F , a selector 45 q can switch whether the original signal 138 is directly output or the extracted outline is output. The selector 45 q selects one of the A and B inputs based on an output from a selector 45 q ′. The selector 45 q ′ outputs one of an inverted signal of the outline signal 104 q and a signal ESDL output from the I/O port connected to the CPU (not shown) as a select signal of the selector 45 q . In this case, the CPU inputs a select signal SEL to the selector 45 q′.

A selector 44 q selects one of fixed values r 5 and r 6 , which are set in registers 42 q and 43 q by the CPU, in accordance with the outline signal 104 q . All the selectors 44 q , 45 q , and 45 q ′ select the A inputs when a switching terminal S=0; they select the B inputs when S=1.

When “1” is input to the switching terminal of the selector 45 q ′, the B input terminal is selected, and the selector 45 q is switched by the signal ESDL output from the I/O port connected to the CPU (not shown). When ESDL=“0”, the A input of the selector 45 q is selected, and normal copy mode is set; when ESDL=“1”, the B input is selected, and an outline output mode is set. The registers 42 q and 43 q are set up with the fixed values r 5 and r 6 by the CPU (not shown). When the outline output 104 q is “0” in the outline output mode, the fixed value r 5 is output; when 104 q =“1”, the fixed value r 6 is output. More specifically, for example, if r 5 =00 H and r 6 =FF H , the outline portion is FF H , i.e., black, and other portions are 00 H , i.e., white, thus forming an outline image, as shown in FIG. 35 E. Since the values r 5 and r 6 are programmable, they can be changed in units of colors to obtain different effects. That is, FF H and 00 H need not always be set, and two different levels, e.g., FF H and 88 H may be set.

When “0” is set in the switching terminal S of the selector 45 q ′, the A input is selected, and an inverted signal of the outline signal 104 q is input to the switching terminal S of the selector 45 q . The selector 45 q outputs original data at the A input for an outline portion, and outputs 00 H , i.e., white as the fixed value at the B input selected by the selector 44 q for portions excluding the outline portion. In this manner, the outline portion can be subjected to processing not by the fixed value but by multi-value original data for each of Y, M, C, and K.

According to this embodiment, a mode of outputting a binary outline image output (multi-color outline processing mode) and a mode of outputting a multi-value outline image output (full-color outline processing mode) can be arbitrarily selected by an operator for each of Y, M, C, and K.

For the threshold values of outline extraction, the values r 1 , r 2 , r 3 , and r 4 are set in the registers 4 q , so that different values can be set for Y, M, C, and K, respectively. These values can also be rewritten by the CPU.

When a matrix size is selected, an outline width can be changed, thus obtaining a different outline image.

The outline extraction matrix size is not limited to the 5×5 and 3×3 sizes described above, and can be desirably changed by increasing/decreasing the numbers of line memories and gates.

The outline processing circuit Q shown in FIG. 35F is arranged in the image process and edit circuit G shown in FIG. 2 . This image process and edit circuit G also includes the texture processing unit 101 g and the zoom, mosaic, taper processing unit 102 g . Since these units are connected in series with each other, their processing operations can be desirably combined upon operation of the operation unit 1000 (to be described later). The order of these processing modes can be desirably set by a combination of a parallel circuit of the processing units and selectors.

In this embodiment, each color component input to the outline processing circuit Q is binarized to obtain an outline signal for each color component, and an outline image is output in color corresponding to the color component. However, the present invention is not limited to this method. For example, an ND image signal can be generated based on a read signal R (red), G (green), or B (blue), an outline can be extracted based on these signals, and original multi-value data, predetermined binary data or the like in units of recording colors can be substituted in the extracted outline portion to form an outline image. In this case, the ND image signal can also be generated based on one of the R, G, and B signals. In particular, since the G signal has characteristics closest to those of the neutral density signal (ND image signal), this G signal can be directly used as the ND signal in terms of a circuit arrangement.

A Y signal (luminance signal) of an NTSC system may also be used.

Non-retctanigular Area Memory

A means for storing a non-rectangular area designated in the present invention will be described below.

In conventional designated area edit processing, as a designated area, only a rectangular area, a non-rectangular area with the limited number of input points (FIG. 37 F), or a combination of the rectangular and non-rectangular areas ( FIG. 37G ) are available. Therefore, the following drawbacks are posed.

For example, as shown in FIG. 37H , since red letters “Fuji” cannot be color-converted into green letters or only a red cloud portion cannot be painted in blue, edit processing is considerably restricted.

In this embodiment, a memory for storing a non-rectangular area is arranged to accomplish such high-grade edit processing.

FIG. 37A is a block diagram showing in detail a mask bit map memory 573 L for restricting an area having an arbitrary shape, and its control. The memory corresponds to the 100-dpi memory L in the entire circuit shown in FIG. 2 , and is used as a means for generating switching signals for determining an ON (executing) or OFF (not executing) state of various image processing and editing modes, such as the above-mentioned color conversion, image trimming (non-rectangular trimming), image painting (non-rectangular painting), and the like for shapes such as those illustrated in FIG. 37 E. More specifically, in FIG. 2 , the switching-signals are supplied through signal lines BHi 123 , DHi 122 , FHi 121 , GHi 119 , PHi 145 , and AHi 148 as ON/OFF switching signals for the color conversion circuit B, the color correction circuit D, the character synthesizing circuit F, the image process and edit circuit G, the color balance circuit P, and the external apparatus image synthesizing circuit 502 .

Note that “non-rectangular area” described here does not exclude a rectangular area, but includes it.

Since a mask is formed so that 4×4 pixels are used as one block and one block corresponds to one bit of a bit map memory. Therefore, in an image having a pixel density of 16 pels/mm, for 297 mm×420 mm (A3 size), (297×420×16×16)÷16≅2 Mbits, i.e., the mask can be formed by two l-Mbit DRAM chips.

In FIG. 37A , a signal 132 input to a FIFO memory 559 L is a non-rectangular area data input line for generating a mask as described above. As the signal 132 , an output signal 421 of the binarization circuit 532 shown in FIG. 2 is input through the switch circuit N.

The binarization circuit receives the signal from the reader A or the external apparatus interface M. When the signal 132 is input, it is input to buffers 559 L, 560 L, 561 L, and 562 L corresponding to 1 bit×4 lines in order to count the number of “1”s in the 4×4 block. FIFO memories 559 L to 562 L are connected as follows. That is, as shown in FIG. 37A , the output of the FIFO memory 559 L is connected to the input of the memory 560 L, and the output of the memory 560 L is connected to the input of the memory 561 L. The outputs from the FIFO memories are latched by latches 563 L to 565 L in response to a signal VCLK, so that four bits are in parallel with each other (see the timing chart of FIG. 37 D). An output 615 L from the FIFO memory 559 L, and outputs 616 L, 617 L, and 618 L from the latches 563 L, 564 L, and 565 L are added by adders 566 L, 567 L, and 568 L (signal 602 L). The signal 602 L is compared with a value (e.g., “12”) set in a comparator 569 L through an I/o port 25 L by the CPU 22 . More specifically, it is checked if the number of “1”s in the 4×4 block is larger than a predetermined value.

In FIG. 37D , the number of “1”s in a block N is “14”, and the number of “1”s in a block (N+1) is “4”. When the signal 602 L represents “14”, an output 603 L of the comparator 569 L in FIG. 37A goes to “1” level since “14”>“12”; when the signal 602 L represents “4”, the output 603 L goes to “0” level since “4”<“12”. Therefore, the output from the comparator is latched once per 4×4 block by a latch 570 L in response to a latch pulse 605 L (FIG. 37 D), and the Q output of the latch 570 L serves as a D IN input of the memory 573 L, i.e., mask generation data. An H address counter 580 L generates a main scan address of the mask memory.

Since one address is assigned to a 4×4 block, the counter 580 L counts up in response to a clock obtained by ¼ frequency-dividing a pixel clock VCLK 608 by a frequency demultiplexer 577 L. Similarly, a V address counter 575 L generates a sub scan address of the mask memory. The counter 575 L counts up in response to a clock obtained by ¼ frequency-dividing a sync signal HSYNC for each line for the same reason as described above. The operations of the H and V address counters are controlled to be synchronized with a counting addition operation of “1”s in the 4×4 block.

Lower 2 bits 610 L and 611 L of the V address counter are logically NORed by a NOR gate 572 L to generate a signal 606 L for gating a ¼ frequency-divided clock 607 L. Then, an AND gate 571 L generates a latch signal 605 L for performing latching once per 4×4 block, as shown in the timing chart of FIG. 37C. A data bus 616 L is included in the CPU bus 22 (FIG. 2 ), and can set non-rectangular area data in the bit map memory 573 L upon an instruction from the CPU 20 . For example, as shown in FIG. 37E , a circle or an ellipse is calculated by the CPU 20 (a sequence therefor will be described later), and calculated data is written in the memory 573 L, thereby generating a regular non-rectangular mask. In this case, for example, the radius or central position of the circle can be input by numerical designation using a ten-key pad of the operation unit 1000 ( FIG. 2 ) or the digitizer 58 . An address bus. 613 L is also included in the CPU bus 22 . A signal 615 L corresponds to the write pulse WR from the CPU 20 . In a WR mode of the memory 573 L set by the CPU 20 , the write pulse goes to “Lo” level, and gates 578 L, 576 L, and 581 L are enabled. Thus, the address-bus 613 L and the data bus 616 L from the CPU 20 are connected to the memory 573 L, and predetermined non-rectangular area data is randomly written in the memory 573 L. When WR (write) and RD (read) operations are sequentially performed by the H and V address counters, gates 576 L′ and 582 L connected to the I/O port 25 L are enabled by control lines of these gates, and sequential addresses are supplied to the memory 573 L.

For example, if a mask shown in FIG. 39 is formed by the output 421 from the binarization circuit 532 or by the CPU 20 , trimming, synthesis, and the like of an image can be performed on the basis of an area surrounded by a bold line.

Furthermore, the bit map memory 573 L shown in FIG. 37A can read out reduced or enlarged data by thinning or interpolation in both the H and V directions in the read mode. FIG. 40 shows in detail the H or V address counter ( 580 L, 575 L) shown in FIG. 37 A. As shown in FIG. 40 , for example, a signal MULSEL 636 L is set to be “0” so that the B input of a selector 634 L is to be selected. A thinning circuit (rate multiplier) 635 L for an input clock 614 L thins data so that a clock CLK is generated once per three timing pulses, as shown in FIG. 41 (timing chart) (setup is made by an I/O port 641 L) ( 637 L). For example, “2” is set in a signal 630 L, and an output 638 L from an address counter 632 L and the value set in the signal 630 L (e.g., “2”) are added to each other only when a thinned output 637 L is output, and the sum is loaded in the counter. Therefore, as shown in FIG. 41 , since the counter is incremented by “+2” every third clock like 1→2→3→5→6→7→9, . . . , 80% reduction. In an enlargement mode, since MULSEL=“1” and an A input 614 L is selected, the address count is incremented like 1→2→3→3→4→5→6→6, . . . , as shown in the timing chart of FIG. 41 .

FIG. 40 shows in detail the H and V address counters 580 L and 575 L shown in FIG. 37 A. Since these circuits have the same hardware arrangement, a description except for FIG. 37A will be omitted.

When the address counters are controlled in this manner, as shown in FIGS. 42A to 42 C, an enlarged image 2 and a reduced image 1 are generated in response to an input non-rectangular area 1 . Therefore, once a non-rectangular area is input, another input operation is not necessary, and a zoom operation can be performed according to various magnifications using one mask plane.

The binarization circuit ( 532 in FIG. 2 ) and the high-density memory K will be described below. In FIG. 43A , the binarization circuit 532 compares the video signal 113 output from the character/image correction circuit E with a threshold value 141 k to obtain a binary signal. The threshold value is set by the CPU bus 22 in cooperation with the operation unit. More specifically, if the level position of the operation unit shown in FIG. 43C is set to be “M” (middle point), the threshold value is “128” with respect to an amplitude value=256 of input data. As the level position is shifted toward a “+” direction, the threshold value is changed by every “−30”; as it is shifted toward a “−” direction, the threshold value is changed by every “+30”. Therefore, in correspondence with “LOW→−2→−1→M→+1→+2→HIGH”, the threshold value is controlled to change like “218→188→158→128→98→68→38”.

As shown in FIG. 43A , two different threshold values are set by the CPU bus 22 . These threshold values are switched by a selector 35 k in accordance with a switching signal 151 , and the selected value is set in a comparator 32 k as the threshold value. The switching signal 151 from the area signal generation circuit J can set another threshold value within a specific area set by the digitizer 58 . For example, a single-color area of an original has a relatively low threshold value, and a multi-color area has a relatively high threshold value, so that a uniform binary signal can always be obtained regardless of colors of an original.

The memory K stores the binary signal 421 output as the signal 130 for one page. In this embodiment, since an image is processed at a density of 400 dpi, the memory has a capacity of about 32 Mbits. FIG. 43B shows in detail the memory K. Input data D IN 130 is gated by an enable signal HE 528 from the area signal generation circuit J in a memory write mode, and is input to a memory 37 k when a W/{overscore (R)} 1 signal 549 from the CPU 20 is at “Hi” level in the write mode. At the same time, a V address counter 35 k for counting a main scan (horizontal) sync signal HSYNC 118 in response to a vertical sync signal ITOP 144 of an image to generate a vertical address, and an H address counter 36 k for counting an image transfer clock VCLK 117 in response to the signal HSYNC 118 to generate a horizontal address corresponding to image data are to be stored. In this case, as a memory WP input (write timing signal) 551 k , a clock which is in-phase with the clock VCLK 117 is input as a strobe signal, and input data Di are sequentially stored in the memory 37 k (timing chart of FIG. 44 ). When data is read out from the memory 37 k , the control signal W/{overscore (R)} 1 is set at “Lo” level, thereby reading out output data D OUT in the same sequence as described above. Both the data write and read access operations are performed in response to a signal HE 528 . For example, when the signal HE 528 goes to “Hi” level at an input timing of D 2 and goes to “Lo” level at an input timing of D m , as shown in FIG. 44 , an image between D 2 and D m is input to the memory 37 k , no image is written in D 0 , D 1 , D m+1 , and thereafter, and data “0” is written instead. The same applies to the read mode. That is, during a period other than a “Hi” period of the signal HE, data “0” is read out. The signal HE is generated by the area signal generation circuit J. More specifically, when a character original as shown in A of FIG. 45 is placed on an original table, the signal HE in the write mode of a binary signal can be generated as shown in A of FIG. 45 , so that a binary image of only a character portion can be fetched in the memory, as shown in A′ of FIG. 45 .

Since the address counters 35 k and 36 k for reading out data from the memory 37 k have the same arrangement as that shown in FIG. 40 and are operated at the same timings shown in FIG. 41 , when a binary character image shown in FIG. 46B (which is prestored in the memory, as shown in FIGS. 46A to 46 D) is synthesized with an image shown in FIG. 46A , the two images can be synthesized after they are reduced, as shown in FIG. 46C , or the two images can be synthesized after only a character portion to be synthesized is enlarged while the size of a background image ( FIG. 46A ) is left unchanged, as shown in FIG. 46 D.

FIG. 47 shows the switch circuit for performing distribution of data from the 100-dpi binary bit map memory L ( FIG. 2 ) for a non-rectangular mask and from the 400-dpi binary memory K ( FIG. 2 ) to the image processing blocks A, B, D, F, P, and G, for switching distribution of binary video images to the memories L and K, and for selectably outputting rectangular and non-rectangular area signals in real time. Real-time switching between the rectangular and non-rectangular area signals will be described later. Mask data for restricting a non-rectangular area stored in the memory L is sent to, e.g., the color conversion circuit B described above (BHi 123 ), and color conversion is performed for a portion inside a shape shown in, e.g., FIG. 48 B. The circuit in FIG. 47 includes an I/O port in connected to the CPU bus 22 , and 2 to 1 selectors 8 n to 13 n , each of which selects the A input when a switching input S=“9”, and selects the B input when S=“0”. For example, in order to supply the output from the 100-dpi mask memory L to the color conversion circuit B, the selector 9 n can select the A input, i.e., 28 n =“1”, and an AND gate 3 n can set a 21 n input to be “1”. Similarly, other signals can be arbitrarily controlled by inputs 16 n to 31 n . Outputs 30 n and 31 n from the I/O port ln are control signals for selecting one of the binary memories L and K in which the output from the binarization circuit 532 ( FIG. 2 ) is to be stored. When 30 n =“1”, the binary input 421 is input to the 100-dpi memory L; when 31 n =“1”, it is input to the 400-dpi memory K. When AHi 148 =“1”, image data sent from an external apparatus is synthesized; when BHi 123 =“1”, color conversion is performed, as described above; and when DHi 122 =“1”, monochromatic image data is calculated and output from the color correction circuit. Signals FHi 121 , PHi 145 , GHi 1 119 , and GHi 2 149 are respectively used for character synthesis, color balance change, texture processing, and mosaic processing operations.

In this manner, the 100- and 400-dpi memories L and K are arranged, so that character information is input to the high-density, i.e., 400-dpi memory K, and area information (including rectangular and non-rectangular areas) is input to the 100-dpi memory L. Thus, character synthesis can be performed for a predetermined area, in particular, a non-rectangular area.

When a plurality of bit map memories are arranged, color window processing shown in FIG. 62 can be achieved.

FIGS. 49A to 49 F are views for explaining the area signal generation circuit J. An area includes, for example, a hatched portion of FIG. 49E , and is distinguished from other areas by a signal AREA shown in the timing chart of FIG. 49E during a sub scan period A→B. Each area is designated by-the digitizer 58 shown in FIG. 2 . FIGS. 49A to 49 D show an arrangement wherein generation positions, durations of periods, and the numbers of periods of a large number of area signals can be programmably obtained by the CPU 20 . In this arrangement, one area signal is generated by one bit of a RAM which can be accessed by the CPU. In order to obtain, for example, n area signals AREA 0 to AREAn, two n-bit RAMs are prepared ( 60 j and 61 j in FIG. 49 D). Assuming that area signals AREA 0 and AREAN shown in FIG. 49B are to be obtained, “1” is set in bits “0” of addresses x 1 and x 3 of the RAM, and “0” is set in all bits of the remaining addresses. On the other hand, “1” is set at addresses 1 , x 1 , x 2 , and x 4 of the RAM, and “0” is set in bits n of other addresses. When data in the RAM are sequentially read out in synchronism with a predetermined clock 117 with reference to the signal HSYNC 118 , data “1” are read out at timings of the addresses x 1 and x 3 , as shown in FIG. 49 C. Since the readout data are input to the J and K terminals of J-K flip-flops 62 j - 0 to 62 j -n, their outputs are subjected to a toggle operation, i.e., when data “ 1 ” is read out from the RAM and the clock CLK is input, their outputs change like “0” to “1” or “1” to “0”, thereby generating a period signal such as ARBA 0 , i.e., an area signal. When data=“0”s over all the addresses, no area period is formed, and no area is set. FIG. 49D shows the circuit arrangement of this circuit, and 60 j and 61 j designate the above-mentioned RAMs. In order to switch area periods at high speed, for example, a memory write operation for setting a different area is performed by the CPU 20 for the RAM B 61 j , while read access of the RAM A 60 j is performed in units of lines, so that period generation and memory write access by the CPU are alternately switched. Therefore, when a hatched area shown in FIG. 49F is designated, the RAMs A and B are switched like A→B→A→B→A. If (C 3 , C 4 , C 5 )=(0, 1, 0) in FIG. 49D , a counter output counted in response to the clock VCLK 117 is supplied to the RAM A 60 j (Aa) as an address through a selector 63 j . In this case, a gate 66 j is enabled, and a gate 68 j is disabled, so that all the bit width, i.e., n bits are read out from the RAM A 60 j and are input to the J-K flip-flops 62 j - 0 to 62 j -n. Thus, period signals AREA 0 to AREAn are generated in accordance with set values. Write access of the RAM B by the CPU is performed by an address bus A-Bus, a data bus D-Bus, and an access signal {overscore (R)}/{overscore (W)} during this period. In contrast to this, period signals can be generated on the basis of data set in the RAM B 61 j in the same manner as described above if (C 3 , C 4 , C 5 )=(1, 0, 1) is set, and data write access of the RAM 60 j by the CPU can also be executed.

The digitizer 58 performs area designation, and inputs coordinates of a position designated by the CPU 20 through an I/O port. For example, in FIG. 50 , if two points A and B are designated, coordinates A (X 1 ,Y 2 ) and B (X 2 ,Y 2 ) are input.

FIG. 37I is a view for explaining a method of executing process and edit processing for rectangular and non-rectangular areas when an original includes both rectangular and non-rectangular images. In FIG. 37I , sgl 1 to sgln and ArCnt designate rectangular area signals, such as outputs AREA 0 to AREAn of the rectangular area signal generation circuit shown in FIG. 49 D.

On the other hand, Hi designates a non-rectangular area signal, such as an output 133 from the bit map memory L and its control circuit shown in FIG. 37 A.

The signals sgl 1 to sgln (h 2 1 to h 2 n) are enable signals of process and edit processing. For a rectangular area, all the signals corresponding to a portion to be subjected to the process and edit processing are enabled. For a non-rectangular area, the signals corresponding to only a rectangular area which inscribes the non-rectangular area are enabled. More specifically, signals corresponding to rectangular areas indicated by dotted lines are enabled for non-rectangular areas indicated by solid lines A and B in FIG. 37 N.

The signal ArCnt (h 3 ) is enabled in synchronism with the signals sgl 1 to sgln for a rectangular area. For a non-rectangular area, the signal ArCnt is disabled.

The signal Hi (h 2 ) is enabled within a non-rectangular area. For a rectangular area, the signal Hi is disabled.

The Hi signal h 2 and the ArCnt signal h 3 are logically ORed by an OR gate h 1 , and the logical sum is logically ANDed with the signals sgl 1 to sgln (h 2 1 to h 2 n) by AND gates h 3 1 to h 3 n, respectively.

In this manner, outputs outl to outn (h 4 1 to h 4 n) allow a desired combination of rectangular and non-rectangular area signals.

FIGS. 37J to 37 M are views for explaining changes in input signals when a rectangular area signal (B) and a non-rectangular area signal (A) are present at the same time.

The signals sgl 1 to sgln ( FIG. 37K ) are enabled for the entire rectangular area, and for a rectangular area which inscribes a non-rectangular area, as described above.

The Hi signal ( FIG. 37L ) is disabled for a rectangular area, and is enabled for the entire non-rectangular area, as described above.

The signal ArCnt ( FIG. 37M ) is enabled for the entire rectangular area, and is disabled for the entire non-rectangular area, as described above.

Finally, a correspondence between FIGS. 37I and 47 will be described below.

The OR gate h 1 shown in FIG. 37I corresponds to OR gates 38 n and 39 n in FIG. 47 ; the AND gates h 3 1 to h 3 n in FIG. 37I , 4 n to 7 n , and 32 n in FIG. 47 ; area signals sgl 1 to sgln (h 2 1 to h 2 n) in FIG. 37I , 33 n to 37 n in FIG. 47 ; and the outputs outl to outn (h 4 1 to h 4 n) in FIG. 37I , DHi, FHi, PHi, GHi 1 , and GHi 2 in FIG. 47 .

In this manner, process and edit processing can be performed for a plurality areas including both rectangular and non-rectangular areas of one original.

As described above, according to this embodiment, since a means for designating a rectangular area (area signals sgtl to sgln), a means for designating a non-rectangular area (hit signals Hih 2 ), and a non-rectangular area real-time selection means (AND gates h 3 1 to h 3 n) are arranged, edit processing can be performed for an original including both rectangular and non-rectangular area designation operations.

In particular, according to this embodiment, since signals sgl 1 to sgln define a rectangular area which inscribes a non-rectangular area, a rectangular or non-rectangular area can be selected in accordance with the non-rectangular area signal Hi and the rectangular area signal ArCnt.

Area designation according to the nature of an area to be designated can be performed. For example, when an area can be roughly designated, area designation can be performed using a rectangular area; when an area must be exactly designated, area designation can be performed using a non-rectangular area. Thus, edit processing with a high degree of freedom can be efficiently performed.

The number of areas and the number of AND gates can be desirably set. The kinds.of processing performed for each area can be desirably determined by setting the I/O port in based on inputs from the operation unit 1000 .

FIG. 51 shows the interface M for performing bidirectional communication of image data with an external apparatus connected to the image processing system of this embodiment. An I/O port lm is connected to the CPU bus 22 , and outputs signals 5 m to 9 m for controlling directions of data buses A 0 to C 0 , A 1 to C 1 , and D. Bus buffers 2 m and 3 m have terminals for an output tristate control signal E. The buffer 3 m can change its direction in accordance with the D input. When E input=“1”, the buffers 2 m and 3 m output signals; when E=“0”, they are set in an output high-impedance state. A 3 to 1 selector 10 m selects one of three parallel inputs A, B, and C in accordance with select signals 6 m and 7 m . In this circuit, basically, there are bus flows of 1. (A 0 , B 0 , C 0 )→(A 1 , B 1 , C 1 ) and 2. (A 1 , B 1 , C 1 )→D. These bus flows are controlled by the CPU 20 as shown in the truth table of FIG. 52 . This system can receive both a rectangular image ( FIG. 53A ) and a non-rectangular image (FIG. 53 B), which are input from an external apparatus through the buses A 1 , A 2 , and A 3 . When a rectangular image shown in FIG. 53A is input, the I/O port 501 outputs a control signal 147 so that the switching input of the selector 503 shown in FIG. 2 is set to be “1” to select the A input. At the same time, predetermined data are written by the CPU at predetermined addresses of the RAbs 60 j and 61 j ( FIG. 51 ) in the area signal generation circuit J, which correspond to areas to be synthesized, thereby generating a rectangular area signal 129 . In an area where an image input 128 from the external apparatus is selected by the selector 507 , not only the image data 128 but also the gradation/resolution switching signal 140 are simultaneously switched. More specifically, in an area where an image from the external apparatus is input, the gradation/resolution switching signal which is generated based on a character area signal MjAr 124 ( FIG. 2 ) detected from color separation signals of an image read from an original table, is stopped, and is forcibly set at “Hi” level, thereby smoothly outputting an image area to be synthesized from the external apparatus with multigradation. As has been described above with reference to FIG. 51 , when the bit map mask signal Ahi 148 from the binary memory L is selected by the selector 503 in response to the signal 147 , synthesis of an image from the external apparatus can be realized, as shown in FIG. 53 B.

Summary of Operation Unit

FIG. 54 schematically shows an outer appearance of the operation unit 1000 according to this embodiment. A key 1100 serves as a copy start key. A key 1101 serves as a reset key, and is used to reset all set values on the operation unit to power-on values. A key 1102 is a clear/stop key, and is used to reset an input count value upon designation of a copy count or to interrupt a copying operation. A key group 1103 is a ten-key pad, and is used to input numerical values, such as a copy count, a magnification, and the like. A key 1104 is an original size detection key. A key 1105 is a center shift designation key. A key 1106 is an ALS function (black original recognition) key. When an ACS mode is ON, an original in signal black color is copied in black. A key 1107 is a remote key which is used to transfer the right of control to a connected apparatus. A key 1108 is a preheat key.

A liquid crystal display 1109 displays various kinds of information. The surface of the display 1109 serves as a touch panel. When the surface of the display 1109 is pressed by, e.g., a finger, a coordinate value of the pressed position is fetched.

In a normal or ordinary state, the display 1109 displays a magnification, a selected sheet size, a copy count, and a copy density. During setting of various copy modes, guide screens necessary for setting the corresponding modes are sequentially displayed. (The copy mode is set by soft keys displayed on the screen.) In addition, the display 1109 displays a self-diagnosis screen of a guide screen.

A key 1110 is a zoom key which serves as an enter key of a mode of designating a zoom magnification. A key 1111 is a zoom program key, which serves as an enter key of a mode of calculating a magnification based on an original size and a copy size. A key 1112 is an enlargement serial copy key, which serves as an enter key of an enlargement serial copy mode. A key 1113 is a key for setting a fitting synthesizing mode. A key 1114 is a key for setting a character synthesizing mode. A key 1115 is a key for setting a color balance. A key 1116 is a key for setting color modes, e.g., a monochrome mode, a negative/positive reversal mode, and the like. A key 1117 is a user's color key, which can set an arbitrary color mode. A key 1118 is a paint key, which can set a paint mode. A key 1119 is a key for setting a color conversion mode. A key 1120 is a key for setting an outline mode. A key 1121 is a key for setting a mirror image mode. Keys 1124 and 1123 are keys for respectively designating trimming and masking modes. A key 1122 can be used to designate an area, and processing of a portion inside the area can be set independently of other portions. A key 1129 serves as an enter key of a mode for performing an operation for reading a texture image, and the like. A key 1128 serves as an enter key of a mosaic mode, and is used to change, e.g., a mosaic size.

A key 1127 serves as an enter key of a mode for adjusting sharpness of an edge of an output image. A key 1126 is a key for setting an image repeat mode for repetitively outputting a designated image.

A key 1125 is a key for enabling inclination/taper processing of an image. A key 1135 is a key for changing a shift mode. A key 1134 is a key for setting a page serial copy mode, an arbitrary division mode, and the like. A key 1133 is used to set data associated with a projector. A key 1132 serves as an enter key of a mode of controlling an optional apparatus connected. A key 1131 is a recall key, which can recall up to previous three set contents. A key 1130 is an asterisk key. Keys 1136 to 1139 are mode memory call keys, which are used to call a mode memory to be registered. Keys 1140 to 1143 are program memory call keys, which are used to call an operation program to be registered.

Color Conversion Operation Sequence

A sequence of the color conversion operation will be described below with reference to FIG. 55 .

When the color conversion key 1119 on the operation unit is depressed, the display 1109 displays a page or image plane P 050 . An original is placed on the digitizer, and a color before conversion is designated with a pen. When an input is completed, the screen display is switched to a page P 051 . On this page, a width of the color before conversion is adjusted using touch-keys 1050 and 1051 . After the width is set, a touch key 1052 is depressed. The screen display is switched to a page P 052 , and whether or not a color density is changed after color conversion is selected using touch keys 1053 and 1054 . When “density change” is selected, the converted color has gradation in correspondence with a color density before conversion. That is, the above-mentioned gradation color conversion is executed. On the other hand, when “density unchange” is selected, the color is converted to a designated color at an equal density. When “density change/unchange” is selected, the screen display is switched to a page P 053 , a kind of color after conversion is selected. When a key 1055 is depressed on the page P 053 , an operator can designate an arbitrary color on the next page P 054 . When a color adjustment key is depressed, the screen display advances to a page P 055 , and color adjustment can be performed for each of Y, M, C, and Bk in units of 1 %.

When a key 1056 is depressed on the page P 053 , the screen display advances to a page P 056 , and a desired color of an original on the digitizer is designated with a pointing pen. On the next page P 057 , a color density can be adjusted.

When a key 1057 is depressed on the page P 053 , the screen display advances to a page P 058 , and a predetermined registration color can be selected by a number.

Trimming Area Designation Sequence

A trimming area designation sequence (the same applies to masking, and also applies to partial processing and the like in terms of a method of designating an area) will be described below with reference to FIGS. 56 and 57 .

The trimming key 1124 on the operation unit 1000 is depressed. When the display 1109 displays a page P 001 , two diagonal points of a rectangle are input using the digitizer, and a page P 002 is then displayed, so that a rectangular area can be successively input. When a plurality of areas are designated, a previous area key 1001 on the page P 001 and a succeeding area key 1002 are depressed in turn, so that designated areas on an X-Y coordinate system can be recognized like in the page P 002 .

In this embodiment, a non-rectangular area can be designated using the bit map memory. During display of the page P 001 , a touch key 1003 is depressed to display a page P 003 . On the page P 003 , a desired pattern is selected. When necessary coordinates of a circle, an oval, an R rectangle, or the like are input, the CPU 20 develops it into the bit map memory by calculations. When a free pattern is selected, a desired pattern is traced using a pointing pen of the digitizer 58 , thereby continuously inputting coordinates. The input values are processed and are recorded on a bit map.

Non-rectangular area designation will be described in detail below.

(Circular Area Designation)

When a key 1004 is depressed on the page P 003 , the display 1009 then displays a page P 004 , and a circular area can be designated.

Circular area designation will be described below with reference to the flow chart of FIG. 58 . In step S 101 , a central point is input using the digitizer 58 shown in FIG. 2 (P 004 ). The display 1009 then displays a page P 005 , and in step S 103 , one point on a circumference of a circle having a radius to be designated is input by the digitizer 58 . In step S 105 , the input coordinate value is converted to a coordinate value in the bit map memory L (100-dpi binary memory) in FIG. 2 by the CPU 20 .

In step S 107 , a coordinate value of another point on the circumference is calculated. In step S 109 , a bank of the bit map memory L is selected, and in step S 111 , the calculation results are input to the bit map memory L via the CPU bus 22 . In FIG. 37A , the data is input to the driver 578 L through the CPU DATA bus 616 L, and is then written in the bit map memory through a signal line 604 L. Since address control has already been described, a description thereof will be omitted. This operation is repeated for all the points on the circumference (S 113 ), thus completing circular area designation.

Note that in place of inputting data calculated by the CPU 20 , template information corresponding to information of two points input in advance is stored in the ROM 11 , and the two points are designated by the digitizer to directly write data in the bit map memory L without calculations.

(Oval Area Designation)

When a key 1005 is depressed on the page P 003 , the display advances to a page 007 . The oval area designation will be described below with reference to the flow chart of FIG. 59 .

In step S 202 , two diagonal points of a maximum rectangular area which inscribes an oval are designated by the digitizer 58 . Coordinate values of the circumferential portion are written in the bit map memory L in steps S 206 to S 212 in the same manner as in the circular area designation.

Coordinate values of straight line portions are written in the memory L in steps S 214 to S 220 , thus completing area designation. Note that template information may be prestored in the ROM 11 as in the circular area designation.

(R Rectangular Area Designation)

A designation method of an R rectangle is the same as that of an oval as well as a memory write access method, and a detailed description thereof will be omitted.

The circle, the oval, and the R rectangle have been exemplified. Other non-rectangular areas can be designated on the basis of template-information, as a matter of course.

On pages P 006 , P 008 , P 010 , and P 102 , a clear key ( 1009 to 1012 ) is depressed after each pattern is input, so that a content in the bit map memory can be partially deleted.

Therefore, when a pattern is erroneously designated, only two-point designation can be immediately cleared, and can be performed again.

A plurality of areas can be successively designated. When a plurality of areas are designated, upon execution of processing of overlapping areas, an area designated later is preferentially processed. Alternatively, areas designated earlier may have priority over others.

FIG. 57 shows an output example of oval trimming by the above-mentioned setting method.

Operation Sequence Associated With Character Synthesis

An operation sequence associated with character synthesis will be described below with reference to FIGS. 60 , 61 , and 62 . When the character synthesizing key 1114 on the operation unit is depressed, the liquid crystal display 1109 displays a page P 020 . When a character original 1201 to be synthesized is placed on the original table, and a touch key 1020 is depressed, the character original is read, the read image information is subjected to binarization processing, and the processed image information is stored in the bit map memory (FIG. 2 ). Since the detailed processing means have already been described, a repetitive description thereof will be avoided. In this case, in order to designate a range of an image to be stored, a touch key 1021 on the page P 020 is depressed to display a page P 021 . The character original 1201 is placed on the digitizer 58 , and a range is designated by pointing two points using the pointing pen of the digitizer. Upon completion of the designation, the screen display advances to a page P 022 , and whether a portion inside the designated range is read (trimming) or a portion outside the designated range is read. (masking) is selected using touch keys 1023 and 1024 . In some character originals, it is difficult to extract a character portion from them during binarization processing. In this case, a touch key 1022 on the page P 020 is depressed to display a page P 023 , so that the slice level of the binarization processing can be adjusted using touch keys 1025 and 1026 .

In this manner, since the slice level can be manually adjusted, appropriate binarizatidn processing can be performed according to a character color or width of an original.

Furthermore, a touch key 1027 is depressed, and an area is designated on pages P 024 ′ and P 025 ′, so that a slice level can be partially modified on a page P 026 ′.

In this manner, an area is designated, and the slice level of only the designated area can be changed. Thus, even when a black character original partially includes, e.g., yellow characters, the slice levels of black and yellow characters are separately and appropriately set, so that satisfactory binarization processing can be performed for the entire characters.

In this case, the above-mentioned processing can be executed according to non-rectangular area information stored in the binary memory L shown in FIG. 2 , as a matter of course.

Upon completion of reading of the character original, the display 1109 displays a page P 024 shown in FIG. 61 .

In order to select color background processing, a touch key 1027 on the page P 024 is depressed to display a page P 025 . A color of a character to be synthesized is selected from displayed colors. A character color can be partially changed. In this case, a touch key 1029 is depressed to display a page P 027 , and an area is designated. Thereafter, a character color is selected on a page P 030 . Furthermore, color frame making processing can be added to a frame of a character to be synthesized. In this case, a touch key 1031 on the page P 030 is depressed to display a page P 032 , and a color of a frame is selected. In this case, color adjustment can be performed as in the color conversion described above. Furthermore, a touch key 1033 is depressed, and a frame width is adjusted on a page P 041 .

A case will be described below wherein tiling processing (to be referred to as window processing hereinafter) is added to a rectangular area including characters to be synthesized. A touch key 1028 on the page P 024 is depressed to display a page P 034 , and an area is designated. Window processing is executed within a range of the designated area. Upon completion of the area designation, a character color is selected on a page P 037 . A touch key 1032 is then depressed to display a page P 039 , and a window color is selected.

In the color selection, a touch key 1030 as a color adjustment key is depressed on the page P 025 to display a page P 026 , and a density of a selected color can be changed.

Character synthesis is performed in the above-mentioned sequence. FIG. 62 shows an output example obtained when the above-mentioned setting method is actually executed.

Note that not only a rectangular area but also a non-rectangular area can be designated.

Texture Processing Setting Sequence

The texture processing will be described below with reference to FIG. 63 A.

When the texture key 1129 on the operation unit 1000 is depressed, the display 1109 displays a page P 060 . When the texture processing is to be executed, a touch key 1060 is depressed to be reverse-displayed. When an image pattern for the texture processing is loaded in the texture image memory ( 113 g in FIG. 32 ), a touch key 1061 is depressed. In this case, if the pattern has already been stored in the image memory, a page P 062 is displayed, and when no image can be displayed, a page P 061 is displayed. An original of an image to be read is placed on the original table, and a touch key 1062 is depressed, so that image data can be stored in the-texture image memory. In order to read an arbitrary portion of the original, a touch key 1063 is depressed, and designation is made on a page P 063 using the digitizer 58 . Designation can be made by pointing one central point of a 16 mm×16 mm reading range by a pointing pen.

Reading of a texture pattern by designating one point can be performed as follows.

When the touch key 1060 is depressed to set texture processing without reading a pattern, and the copy start key 1100 , or other mode keys ( 1110 to 1143 ), or a touch key 1064 is depressed to leave the page P 064 , the display 1109 generates warning as shown in a page P 065 .

The size of the reading range may be designated by an operator using the ten-key pad.

FIG. 63B shows the flow chart of the CPU 20 when a texture pattern is read;

In the texture mode, it is checked if coordinates of a central point of a portion (in this embodiment, a square is exemplified but other figures, e.g., a rectangle may be available) used as a texture pattern on an original is input from the digitizer 58 (S 631 ). In this case, the coordinate input is recognized by (x,y) coordinates of an input point, as shown in a block S 631 ′. If NO in step S 631 , an input is waited; otherwise, write start and end addresses in the horizontal and vertical directions are calculated (S 632 ′) and are set in the counters (S 632 ). In this case, if lengths a of vertical and-horizontal sides are set to be different from each other, a rectangular pattern can be formed. Image data is then read by scanning the reader A, and the image data at a predetermined position is written in the texture memory 113 g ( FIG. 32 ) (S 633 ). Thus, the storage operation of the texture pattern is completed, and a normal copying operation is performed in the above-mentioned method (step S 634 ) to synthesize the texture pattern.

According to this embodiment, when one point is designated on the digitizer, the texture pattern can be read, and operability can be remarkably improved.

Mosaic Processing Setting Sequence

FIG. 64A is a view for explaining a sequence for setting mosaic processing.

When the mosaic key 1128 on the operation unit is depressed, the display 1109 displays a page P 100 . In order to perform mosaic processing of an original image, a touch key 1400 is depressed and reverse-displayed.

A mosaic size upon execution of mosaic processing is changed on a page P 101 displayed by depressing a touch key 1401 . The mosaic size can be changed independently in both the vertical (Y) and horizontal (X) directions.

FIG. 64B is a flow chart showing a setting operation of the mosaic size. When the mosaic mode is set, the CPU 20 checks if a mosaic size (X, Y) is input from the liquid crystal touch panel 1109 (S 641 ). If NO in step S 641 , an input is waited; otherwise, parameters (X, Y) are set in mosaic processing registers (in 402 g in FIG. 34 ) in the digital processor (S 642 ). Based on these parameters, mosaic processing is executed by the above-mentioned method in a size of X mm (horizontal direction)×Y mm (vertical direction).

In this embodiment, since the mosaic size can be set independently in the vertical and horizontal directions, various needs on image edit processing can be met. In particular, this mode can be widely utilized in the field of design.

* Mode Operation Sequence

FIG. 65 is a view for explaining an * mode operation sequence.

When the * key 1130 on the operation unit 1000 is depressed, the control enters the * mode, and the display 1109 displays a page P 110 . Upon depression of a touch key 1500 , a color registration mode for registering a paint user's color and color information used in color conversion or color character is set. Upon depression of a touch key 1501 , a function of correcting an image omission caused by a printer is turned on/off. A touch key 1502 is used to start a mode memory registration mode. A touch key 1503 is used to start a mode of designating a manual feed size. A touch key 1504 is used to start a program memory registration mode. A touch key 1505 is used to start a mode of setting a default value of color balance.

(Color Registration Mode)

When the touch key 1500 is depressed during display of the page P 110 , the color registration mode is started. The display 1109 displays a page Plll, and a kind of color to be registered is selected. When pallet colors are to be changed, a touch key 1506 is depressed, and a color to be changed is selected on a page P 116 . On a page P 117 , values of yellow, magenta, cyan, and black components can be adjusted in units of 1%.

When an arbitrary color on an original is to be registered, a touch key 1507 is depressed, and a registration number is selected on a page P 118 . A color to be registered is then designated using the digitizer 58 . On a page P 120 , an original is set on the original table, and a touch key 1510 is depressed to register a desired color.

(Manual Feed Size Designation)

As shown in a page P 112 , a manual feed size can be selected from both. standard and specific sizes.

A specific size can be designated in units of 1 mm in both the horizontal (X) and vertical (Y) directions.

(Mode Memory Registration)

As shown in a page P 113 , a set mode can be registered in the mode memory.

(Program Memory Registration)

As shown in a page P 114 , a series of programs for performing area designation and predetermined processing operations can be registered.

(Color Balance Registration)

As shown in a page P 115 , color balance of each of Y, M, C, and Bk can be registered.

Program Memory Operation Sequence

A registration operation of the program memory and its use sequence will be explained below with reference to FIGS. 66 and 67 .

The program memory has a memory function of storing operation sequences associated with setting operations, and reproducing the stored sequences. In this function, necessary modes can be combined, or setting operations can be made while skipping unnecessary pages. For example, a sequence for executing zoom processing of a certain area and setting an image repeat mode will be programmed below.

The * key 1130 on the operation unit is depressed to display a page P 080 on the display, and a touch key 1200 as a program memory key is then depressed. In this embodiment, a maximum of four programs can be registered. On the page P 081 , a number to be registered is selected. Thereafter, a program registration mode is started. In the program registration mode, a page 1300 in FIG. 68 in a normal mode is displayed like a page 1301 . A touch key 1302 as a skip key is depressed when a present page is to be skipped. A touch key 1303 as a clear key is used to interrupt registration during the program memory registration mode, and to restart registration. A touch key 1304 as an end key is used to leave the program memory registration mode and to register a program in a memory having a number determined first.

The trimming key 1124 on the operation unit is depressed, and an area is designated by the digitizer. In this case, the display 1109 displays a page P 084 (FIG. 66 B). However, if no more area designation is required, a touch key 1202 is depressed to skip this page (a page P 085 is displayed in turn).

When the zoom key 1110 on the operation unit is depressed, the display 1109 displays a page P 086 (FIG 66 C). A magnification is set on this page, and a touch key 1203 is then depressed to turn a display to a page P 087 . Finally, the image repeat key 1126 on the operation unit is depressed, and a setting operation associated with the image repeat mode is performed on the page P 088 . Thereafter, a touch key 1204 is depressed to register the above program in the program memory No. 1 .

In order to call the program registered in the above-mentioned sequence, the key 1140 for calling the program memory “1” on the operation unit is depressed. The display 1109 displays a page P 091 to wait for an area input (FIG. 67 A). When an area is input using the digitizer, the display 1109 displays a page P 092 , and then turns it to the next page P 093 (FIG 67 B). When a magnification is set on this page and a touch key 1210 is depressed, the display 1109 displays a page P 094 , and the image repeat mode can be set. When a touch key 1211 is depressed, the control leaves a mode utilizing the program memory (to be referred to as a trace mode hereinafter). While the program memory is called and a programmed operation is executed, the edit mode keys ( 1110 to 1143 ) are invalidated, and an operation can be executed according to a registered program.

FIG. 69 shows a registration algorithm of the program memory. Turning of a page or image plane in step S 301 is to rewrite a display of the liquid crystal display using keys or touch keys. When the touch key 1302 is depressed to skip the presently displayed image plane (S 303 ), skip information is set in a record table when the next image plane is turned (S 305 ). In step S 307 , the number of a new image plane or. a new image plane number is set on the record table. When a clear key is depressed, the record table is entirely cleared (S 309 , S 311 ); otherwise, the flow returns to.step S 301 to display the next image plane. FIG. 71 shows a format of a record table. FIG. 70 shows an algorithm of an operation after the program memory is called.

If it is determined in step S 401 that an image plane is to be turned, it is checked if a new image plane is a standard image plane (S 403 ). If YES in step S 403 , the flow advances to step S 411 , and the next image plane number is set from the record table; otherwise, the new image plane number is compared with an image plane number predetermined in the record table (S 405 ). If a coincidence between the two numbers is detected, the flow advances to step S 409 . If a skip flag is detected, the flow returns to step S 401 while skipping step S 411 . If a noncoincidence is detected in step S 405 , recovery processing is executed (S 407 ), and an image plane is then turned.

A means for switching a printing resolution and outputting an image according to-the present invention will be described below. This means switches a printing resolution on the basis of the resolution switching signal 140 generated according to character and halftone portions separated by the above-mentioned character/image area separation circuit I, and corresponds to the driver shown in FIG. 2 . In this embodiment, a character portion is printed at a high resolution of 400 dpi, and a halftone portion is printed at 200 dpi. This means will be described in detail below. A PWM circuit 778 as a portion of the driver shown in FIG. 2 is included in a printer controller 700 of the printer 2 shown in FIG. 1 . The PWM circuit 778 receives the video data 138 as a final output of the overall circuit shown in FIG. 2 , and the resolution switching signal 143 to perform ON/OFF control of a semiconductor laser 711 L shown in FIG. 75 .

The PWM circuit 778 , as a portion of the driver shown in FIG. 2 , for supplying a signal for outputting a laser beam will be described in detail below.

FIG. 73A is a block diagram of the PWM circuit, and FIG. 73B is a timing chart thereof.

The input video data 138 is latched by a latch 900 in response to a leading edge of a clock VCLK 117 to be synchronized with clocks. The video data 138 output from the latch is subjected to gradation-correction by an LUT (look-up table) 901 comprising a ROM or RAM. The corrected image data is D/A-converted into one analog video signal by a D/A (digital-to-analog) converter 902 . The generated analog signal is input to the next comparators 910 and 911 , and is compared with triangle waves (to be described later). Signals 808 and 809 input to the other input terminal of each comparator are triangle waves ( 808 and 809 in FIG. 73B ) which are synchronized with the clock VCLK and are separately generated. More specifically, one wave is a triangle wave WV 1 which is generated by a triangle wave generation circuit 908 in accordance with a triangle wave generation reference signal 806 obtained by ½ frequency-dividing a sync clock 2 VCLK 117 ′ having a frequency twice that of the clock VCLK 801 by a J-K flip-flop 906 , and the other wave is a triangle wave WV 2 generated by a triangle wave generation circuit 909 in accordance with the clock 2 VCLK. Note that the clock 2 VCLK 117 ′ is generated by a multiplier (not shown) based on the clock VCLK 117 . The triangle waves 808 and 809 and the video data 138 are generated in synchronism with the clock VCLK, as shown in FIG. 73 B. An inverted HSYNC signal initializes the flip-flop 906 to be synchronous with an HSYNC signal 118 generated synchronous with the clock VCLK. With the above operation, signals having pulse widths shown in FIG. 73C according to the value of the input video data 138 can be obtained as outputs 810 and 811 of the comparators CMP 1 910 and CMP 2 911 . More specifically, in this system, when an output from an AND gate 913 shown in FIG. 73A is “1”, a laser is turned on, and prints dots on a print sheet; when the output is “0”, the laser is turned off, and prints nothing on the print sheet. Therefore, an OFF state of the laser can be controlled by a control signal LON ( 805 ) from the CPU 20 . FIG. 73C shows a state wherein the level of an image signal Di changes from “black” to “white” from the left to the right. Since “white” data is input as “FF” and “black” data is input as “00” to the PWM circuit, the output from the D/A converter 902 changes like Di shown in FIG. 73 C. In contrast to this, since the triangle waves change, as indicated by WV 1 (i) and WV 2 (ii), the pulse widths of the outputs of the comparators CMP 1 and CMP 2 are decreased as the level shifts from “black” to “white”, as indicated by PW 1 and PW 2 . As can be seen from FIG. 73C , when PW 1 is selected, dots are formed on a print sheet to have intervals of P 1 →P 2 , and a change in pulse width has a dynamic range of W 1 . On the other hand, when PW 2 is selected, dots are formed to have intervals of P 3 →P 4 →P 5 →P 6 , and a dynamic range of a change-in pulse width is W 2 . Thus, the dynamic range of PW 2 is ½ that of PW 1 . For example, a printing density (resolution) is set to be about 200 lines/inch for PW 1 , and is set to be about 400 lines/inch for PW 2 . As can be understood from this, when PWl is selected, gradation can be improved about twice that of PW 2 , while when PW 2 is selected, a resolution can-be remarkably improved. Thus, the reader ( FIG. 1 ) supplies the signal LCHG 143 so that when a high resolution is required, PW 2 is selected, and when multigradation is required, PW 1 is selected. More specifically, a selector 912 shown in FIG. 73A selects the A input, i.e., PW 1 , when LCHG 143 =“0”. When LCHG=“1”, PW 2 is output from an output terminal {overscore (O)} of the selector 912 . The laser is turned on by a finally obtained pulse width, thereby printing dots.

The LUT 901 is a table conversion ROM for gradation correction. The LUT 901 receives address signals C 2 812 ′, C 1 812 , and C 0 813 , a table switching signal 814 , and a video signal 815 , and outputs corrected video data. When the signal LCHG 143 is set to be “0” to select PW 1 , a binary counter 903 outputs all “0”s, and a PW 1 correction table in the LUT 901 can be selected. The signals C 0 , C 1 , and C 2 are switched according to a color signal to be output. For example, when C 0 , C 1 , C 2 =“0, 0, 0”, a yellow signal is output; when “0, 1, 0”, magenta; when “1, 0, 0”, cyan; and when “1, 1, 0”, black as in the masking processing. That is, gradation correction characteristics are switched in units of color images to be printed. In this manner, differences in gradation characteristics caused by differences in image reproduction characteristics of the laser beam printer depending on colors can be compensated for. Upon combination of C 2 , C 0 , and C 1 , gradation correction over a wide range can be performed. For example,. gradation switching characteristics of each color can be switched according to a kind of input image. When the signal LCHG is set to be “1” to select PW 1 , the binary counter counts sync signals of a line, and outputs “1”→“2”→“1”→“2”→, . . . , to the address input 814 of the LUT. Thus, a gradation correction table is switched in units of lines, thus further improving gradation.

This will be described in more detail with reference to FIGS. 74A and 74B . A curve A shown in FIG. 74A is an input data vs. printing density characteristic curve when input data is changed from “FF”, i.e., “white” to “0”, i.e., “black”. A standard characteristic curve K is preferable, and hence, a gradation correction table is set up with a characteristic curve B as characteristics opposite to the curve A. FIG. 74A shows gradation correction characteristics A and B in units of lines when PW 1 is selected. When a pulse width in the main scan direction (laser scan direction) is varied by the above-mentioned triangle wave, two stages of gradation are provided in the sub scan direction (image feed direction), thus further improving gradation characteristics. More specifically, a portion suffering from an abrupt change in density is reproduced based mainly on the characteristic curve A, and flat gradation is reproduced by the characteristic curve B. Therefore, even when PW 2 is selected, as described above, a certain gradation level can be assured at a high resolution. When PW 1 is selected, very good gradation characteristics can be guaranteed.

The pulse-width modulated video signal is applied to a laser driver 711 L through a line 224 , thereby modulating a laser beam LB.

Note that the signals C 0 , C 1 , C 2 , and LON in FIG. 73 are output from a control circuit (not shown) in the printer controller 700 shown in FIG. 2 .

A case will be examined below wherein a color original including a character area is to be processed. Referring back to the overall circuit diagram of FIG. 2 , a processing sequence will be described below. More specifically, after input image data including both character and halftone images passes through an input circuit (A block), one is input to the LOG conversion circuit (C) and the color correction circuit (D) to obtain an appropriate image, and the other is input to a detection circuit (I) for separating a halftone area. Thus, detection signals MjAr ( 124 ) to SCRN ( 127 ) according to character and halftone areas are output. Of these detection signals, the signal MjAr ( 124 ) is a signal representing a character portion. The character/image correction circuit E generates the resolution switching signal LCHG ( 140 in FIG. 2 , 140 in FIG. 21 ) based on the signal MjAr, as has been described above. As shown in FIG. 2 , the signal LCHG 140 is separately sent to the printer to be parallel to multi-value video signals 113 , 114 , 115 , 116 , and 138 , and serves as a switching signal for outputting a character portion at a high resolution (400 dpi) and outputting a halftone portion with multigradation (200 dpi).

The following processing is performed, as described above.

[Image Forming Operation]

The laser beam LB modulated in correspondence with image output data 816 is horizontally scanned at high speed in an angular interval of arrows A-B by a polygonal mirror 712 which is rotated at high speed, and forms an image on the surface of a photosensitive drum 715 via an f/θ lens 713 and a mirror 714 , thus performing dot-exposure corresponding to image data (FIG. 75 ). One horizontal scan period of the laser beam corresponds to that of an original image, and corresponds to a width of {fraction (1/16)} mm in a feed direction (sub scan direction) in this embodiment.

On the other hand, the photosensitive drum 715 is rotated at a constant speed in a direction of an arrow L shown in FIG. 75 . Since scanning of the laser beam is performed in the main scan direction of the drum and the photosensitive drum 715 is rotated at a constant speed in the sub scan direction, an image is sequentially exposed, thus forming a latent image. A toner image is formed by uniform charging by a charger 717 prior to exposure, the above-mentioned exposure, toner and developing by a developing sleeve 731 . For example, when a latent image is developed by a yellow toner of a developing sleeve 713 Y in correspondence with the first original exposure-scanning in the color reader, a toner image corresponding to a yellow component of an original 3 is formed on the photosensitive drum 715 .

The yellow toner image is transferred to and formed on a sheet 791 whose leading end is carried by grippers 751 and which is wound around a transfer drum 716 by a transfer charger 729 arranged at a contact point between the photosensitive drum 715 and the transfer drum 716 . The same processing is repeated for M (magenta), C (cyan), and Bk (black) images to overlap the corresponding toner images on the sheet 791 , thus forming a full-color image using four colors of toners.

Thereafter, the sheet 791 is peeled from the transfer drum 716 by a movable peeling pawl 750 shown in FIG. 1 , and is then guided to an image fixing unit 743 by a conveyor belt 742 . Thus, the toner images on the sheet 791 are welded and fixed by heat and press rollers 744 and 745 of the fixing unit 743 .

In this embodiment, the printing driver drives the color laser beam printer. The present invention can also be applied to color image copying machines such as a thermal transfer color printer, an ink-jet color printer, and the like for obtaining a color image as long as they have a function of switching a resolution according to images.

As described above, an image processing apparatus of this embodiment comprises a means for inputting image data (A in FIG. 2 ), a generation means for generating a non-rectangular area signal (CPU 20 ), a storage means for storing the non-rectangular area signal (L in FIG. 2 ), a read control means for reading out the non-rectangular area signal from the storage means in synchronism with an image input by the input means (J in FIG. 2 , and the like), and a processing means for processing the input image data on the basis of the readout non-rectangular area signal (G in FIG. 2 , and the like).

More specifically, since the non-rectangular area signal generation means, the non-rectangular area signal storage means, and a means for reading the stored non-rectangular area signal in synchronism with image reading are arranged, edit processing can be executed based on the non-rectangular area signal representing, e.g., a circle or oval pattern, and prestored in a program memory.

In this embodiment, a circle, an oval, and the like have been exemplified as non-rectangular areas. The present invention can be similarly applied to various other non-rectangular patterns such as a triangle, a rhombus, and the like.

According to the present invention, various edit processing operations such as trimming and masking can be executed using a non-rectangular area having a predetermined pattern, consequently, higher-grade image processing can be attained. Thus, the present invention is applicable to the field of design.

According to this embodiment, the area signal generation means for generating an area using coordinate inputs of at least two points on the basis of selected non-rectangular area data is arranged, so that a non-rectangular area can be generated by a simple operation.

More specifically, an area can be generated by designating the center of a circle and one point on its circumference (FIG. 76 A), or designating coordinates of two points generating a largest rectangle which inscribes an oval (FIG. 76 B).

The non-rectangular pattern is not limited to a circle and an oval. For example, a triangular area can be designated by designating coordinates of a barycenter, and a vertex of a vertical angle, or a square area can be designated by designating coordinates of one vertex of a right angle, thus designating other non-rectangular areas.

More specifically, a plurality of positions on the digitizer need only be designated to specify a non-rectangular pattern. Coordinates to be designated vary depending on the number of parameters to be specified. The non-rectangular patterns may be prestored in a ROM or may be calculated by the CPU upon input of predetermined coordinates.

According to this embodiment, edit processing such as trimming and masking can be easily executed by using a predetermined non-rectangular area pattern and higher-grade image processing can be performed. Thus, the present invention can be widely applied to the field of design.

More specifically, in this embodiment, the above-mentioned objects are achieved by arranging a means for inputting image data (A in FIG. 2 , and the like), a generation means for generating a non-rectangular area signal based on predetermined coordinate designation (CPU 20 in FIG. 2 , and the like), a storage means for storing the non-rectangular area signal (L in FIG. 2 ), a read control means for reading out the stored non-rectangular area signal in synchronism with an image input (J in FIG. 2 , and the like), and a processing means for processing the input image data on the basis of the readout non-rectangular area signal (G in FIG. 2 , and the like).

As described above, according to the present invention, a non-rectangular area can be easily designated within a short period of time.

Furthermore, according to this embodiment, a generation means for generating a signal for defining a non-rectangular image area, a storage means for storing the output from the generation means, a means for designating a specific color to be detected, and another storage means for storing the output from the specific color designation means and the signal for defining the non-rectangular image area are arranged, so that color conversion processing of a non-rectangular area can be performed.

As described above, according to this embodiment, since color conversion processing can be executed for a non-rectangular area, the following two effects, i.e., higher-grade high-precision color conversion processing, can be performed:

(1) When a plurality of areas including a color to be converted are too adjacent to each other to be divided by rectangular areas, color conversion processing can be executed for one of the areas.

(2) When color conversion is performed for an area consisting of multi-gradational colors, since a detection width can be increased, color conversion processing can be performed for a desired area.

The present invention is especially effective for gradational color conversion, and is also effective for normal color conversion (where converted colors have no gradation).

In this embodiment, the above-mentioned objects are attained by arranging a means for detecting a specific color in a color image on the basis of input image data (B in FIG. 2 ), a generation means for generating a non-rectangular image area signal (J in FIG. 2 ), and a conversion means for converting the detected specific color into another color on the basis of the output from the detection means and the non-rectangular image area signal (B in FIG. 2 ).

As described above, according to the present invention, high-quality image processing operations can be performed.

Claims

1. An image processing apparatus comprising:selection means for selecting a type of non-rectangular area from a plurality of types of non-rectangular areas, said plurality of types of non-rectangular areas having predetermined fixed shapes; display means for displaying, automatically after the selection by said selection means, guidance information for an operator in accordance with the type of non-rectangular area selected by said selection means, the guidance information providing the operator with instructions for performing one or more subsequent operations; and designation means capable of use by the operator for designating a size of the non-rectangular area in accordance with the guidance information displayed by said display means, wherein said guidance information comprises a sentence which informs the operator of an operation to designate the non-rectangular area, wherein said display means comprises a touch panel for inputting an instruction of an operator, said designation means comprises a pointing device different from said touch panel, and wherein said guidance information comprises a sentence which informs the operator of usage of both said touch panel and said pointing device to perform the operation.

2. An apparatus according to claim 1, further comprising developing means for developing non-rectangular area data on a memory in accordance with the non-rectangular area designated by said designation means.

3. An apparatus according to claim 2, further comprising:input means for inputting image data line-by-line; control means for reading out the non-rectangular area data developed by said developing means from said memory in synchronism with the line-by-line input of the image data by said input means; and process means for processing said image data in the designated non-rectangular area represented by the non-rectangular area data developed by said development means.

4. An apparatus according to claim 3, wherein said input means comprises image read means for scanning an original to generate image data, and said image read means comprises red, blue and green CCD line sensors.

5. An apparatus according to claim 3, wherein said input means comprises image read means for scanning an original to generate image data.

6. An apparatus according to claim 3, wherein said process means executes, for the non-rectangular area, at least one of a color conversion process, a mosaic process, a texture process, a trimming process, a masking process, an image synthesis process, an outline process, an image repeat process, a paint process, a mirror image process and an inclination process.

7. An apparatus according to claim 3, further comprising output means for outputting image data processed by said process means.

8. An apparatus according to claim 7, wherein said output means comprises a laser beam printer.

9. An apparatus according to claim 7, wherein said output means comprises a printer having a head of a type causing film boiling by heat energy to inject an ink droplet.

10. An apparatus according to claim 2, wherein said memory is a bit map memory.

11. An apparatus according to claim 1, wherein the type of non-rectangular area is at least one of a circle, an oval, a rounded rectangle and a triangle.

12. An apparatus according to claim 1, wherein selection means comprises key input means.

13. An apparatus according to claim 1, further comprising size designation means for designating a size of the non-rectangular area and a position of the non-rectangular area on an image represented by the image data input by said input means.

14. An apparatus according to claim 1, wherein said display means is a liquid crystal display.

15. An apparatus according to claim 1, wherein said display means displays a figure representing the type of non-rectangular area.

16. An apparatus according to claim 1, wherein said display means displays a character representing the type of non-rectangular area.

17. An apparatus according to claim 1, wherein the guidance information which informs the operator of an operation that should be performed to designate the size of the non-rectangular area comprises a sentence.

18. An image processing method comprising the steps of:selecting a type of non-rectangular area from a plurality of types of non-rectangular areas, said plurality of types of non-rectangular areas having predetermined fixed shapes; displaying, automatically after the selection, guidance information for an operator in accordance with the type of non-rectangular area, the guidance information providing the operator with instructions for performing one or more subsequent operations; and designating a size of the non-rectangular area in accordance with the guidance information, wherein said guidance information comprises a sentence which informs the operator of an operation to designate the non-rectangular area, and wherein said guidance information comprises a sentence which informs the operator of a usage of both a touch panel and a pointing device to perform the operation.

19. An apparatus according to claim 18, wherein the guidance information which informs the operator of an operation that should be performed to designate the size of the non-rectangular area comprises a sentence.